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Nonvolatile Digital Computing with Ferroelectric FET

20200027508 ยท 2020-01-23

    Inventors

    Cpc classification

    International classification

    Abstract

    Embodiments include nonvolatile a memory (NVM) device that can be configured for logic switching and/or digital computing. For example, embodiments of the NVM device can be configured as any one or combination of a memory cell, a D flip flop (DFF), a Backup and Restore circuit (B&R circuit), and/or a latch for a DFF. Any of the NVM devices can have a Fe field effect transistors (FeFET) configured to exploit the I.sub.DSV.sub.G hysteresis of the steep switch at low voltage for logic memory synergy. The FeFET-based devices can be configured to include a wide hysteresis, a steep hysteresis edge, and high ratio between the two I.sub.DS states at V.sub.G=0.

    Claims

    1. A nonvolatile memory (NVM) device, comprising a circuit topology having at least one Fe field effect transistor (FeFET) configured to exhibit a wide current-voltage (I-V) hysteresis covering zero gate bias.

    2. The NVM device recited in claim 1, wherein: the circuit topology is configured as a backup and restore circuit (B&R circuit); the B&R circuit comprising: a first transistor, M.sub.1, M.sub.1 having an M.sub.1-source, an M.sub.1-gate, and an M.sub.1-drain; a second transistor, M.sub.2, M.sub.2 having an M.sub.2-source, an M.sub.2-gate, and an M.sub.2-drain; a third transistor, M.sub.3, M.sub.3 having an M.sub.3-source, an M.sub.3-gate, and an M.sub.3-drain; a fourth transistor, M.sub.4, M.sub.4 having an M.sub.4-source, an M.sub.4-gate, and an M.sub.4-drain; a fifth transistor, M.sub.5, M.sub.5 having an M.sub.5-source, an M.sub.5-gate, and an M.sub.5-drain; a sixth transistor, M.sub.6, M.sub.6 having an M.sub.6-source, an M.sub.6-gate, and an M.sub.6-drain; a seventh transistor, M.sub.7, M.sub.7 having an M.sub.7-source, an M.sub.7-gate, and an M.sub.7-drain; an eighth transistor, M.sub.8, M.sub.8 having an M.sub.8-source, an M.sub.8-gate, and an M.sub.8-drain; a first branch and a second branch, the first branch including M.sub.1, M.sub.2, M.sub.5, M.sub.7, and a ground, GND, the second branch including M.sub.3, M.sub.4, M.sub.6, and M.sub.8; each of M.sub.1, M.sub.2, M.sub.3, M.sub.4, M.sub.7, and M.sub.8 is a metal-oxide-semiconductor field-effect transistor (MOSFET) and each of M.sub.5 and M.sub.6 is a FeFET; M.sub.1-gate being connected to a backup control signal input, B.sub.kp_input and M.sub.3-gate; M.sub.1-drain being connected to M.sub.2-drain; M.sub.1-drain being configured to be connected to a slave latch via the first branch; M.sub.1-source being connected to M.sub.5-source and M.sub.7-drain; M.sub.2-drain being connected to M.sub.1-drain; M.sub.2-drain being configured to be connected to the slave latch via the first branch; M.sub.2-gate being connected to a backup and restore control signal input, B.sub.kp+R.sub.str and M.sub.3-gate; M.sub.2-source being connected to M.sub.6-gate, M.sub.5-drain, M.sub.5-gate, M.sub.6-drain, and M.sub.3-source; M.sub.3-drain being connected to M.sub.4-drain; M.sub.3-drain being configured to be connected to the slave latch via the second branch; M.sub.3-gate being connected to B.sub.kp+R.sub.str and M.sub.1-gate; M.sub.3-source being connected to M.sub.5-gate, M.sub.6-drain, M.sub.5-drain, M.sub.2-source, and M.sub.6-gate; M.sub.4-drain being connected to M.sub.3-drain; M.sub.4-drain being configured to be connected to the slave latch via the second branch; M.sub.4-gate being connected to a backup control signal output, B.sub.kp_output; M.sub.4-source being connected to M.sub.6-source and M.sub.8-drain; M.sub.5-drain being connected to M.sub.2-source, M.sub.5-gate, M.sub.6-gate, M.sub.6-drain, and M.sub.3-source; M.sub.5-gate being connected to M.sub.3-source, M.sub.6-drain, M.sub.6-gate, M.sub.2-source, and M.sub.5-drain; M.sub.5-source being connected to M.sub.7-drain and M.sub.1-source; M.sub.6-drain being connected to M.sub.3-source, M.sub.5-gate, M.sub.6-gate, M.sub.5-drain, and M.sub.2-source; M.sub.6-gate being connected to M.sub.2-source, M.sub.5-drain, M.sub.5-gate, M.sub.6-drain, and M.sub.3-source; M.sub.6-source being connected to M.sub.4-source and M.sub.8-drain; M.sub.7-drain being connected to M.sub.1-source and M.sub.5-source; M.sub.7-gate being connected to a restore input control signal, R.sub.str; M.sub.7-source being connected to GND via the first branch; M.sub.8-drain being connected to M.sub.4-source and M.sub.6-source; M.sub.8-gate being connected to M.sub.7-gate; and M.sub.8-source being connected to GND via the second branch.

    3. The NVM device recited in claim 1, wherein: the circuit topology is configured as a D-Flip Flop (DFF); the DFF comprising a master latch, a slave latch, and a backup and restore circuit (B&R circuit); the master latch comprising: a first master inverter M.sub.INV1, a second master inverter, M.sub.INV2, a third master inverter, M.sub.INV3, and a master transmission gate, M.sub.GATE; input of M.sub.INV1 being connected to a data input signal, D; output of M.sub.INV1 being connected to input of M.sub.INV2; input of M.sub.INV2 being connected to output of M.sub.INV1; output of M.sub.INV2 being connected to input of M.sub.INV3; input of M.sub.INV3 being connected to output of M.sub.INV2; output of M.sub.INV3 being connected to input of M.sub.GATE; input of M.sub.GATE being connected to output of M.sub.INV3; and output of M.sub.GATE being connected to input of M.sub.INV2 and output of M.sub.INV1; the slave latch comprising: a first slave inverter, S.sub.INV1, a second slave inverter, S.sub.INV2, a third slave inverter, S.sub.INV3, and a slave transmission gate, S.sub.GATE; input of S.sub.INV1 being connected to output of M.sub.INV2; input of S.sub.INV2 being connected to output of S.sub.INV1; output of S.sub.INV2 being connected to input of S.sub.INV3 and to a data output Q; input of S.sub.INV3 being connected to output of S.sub.INV2; output of S.sub.INV3 being connected to input of S.sub.GATE; and output of S.sub.GATE being connected to input of S.sub.INV2 and output of S.sub.INV1; and the B&R circuit comprising: a first transistor, M.sub.1, M.sub.1 having an M.sub.1-source, an M.sub.1-gate, and an M.sub.1-drain; a second transistor, M.sub.2, M.sub.2 having an M.sub.2-source, an M.sub.2-gate, and an M.sub.2-drain; a third transistor, M.sub.3, M.sub.3 having an M.sub.3-source, an M.sub.3-gate, and an M.sub.3-drain; a fourth transistor, M.sub.4, M.sub.4 having an M.sub.4-source, an M.sub.4-gate, and an M.sub.4-drain; a fifth transistor, M.sub.5, M.sub.5 having an M.sub.5-source, an M.sub.5-gate, and an M.sub.5-drain; a sixth transistor, M.sub.6, M.sub.6 having an M.sub.6-source, an M.sub.6-gate, and an M.sub.6-drain; a seventh transistor, M.sub.7, M.sub.7 having an M.sub.7-source, an M.sub.7-gate, and an M.sub.7-drain; an eighth transistor, M.sub.8, M.sub.8 having an M.sub.8-source, an M.sub.8-gate, and an M.sub.8-drain; a first branch and a second branch, the first branch including M.sub.1, M.sub.2, M.sub.5, M.sub.7, and a ground, GND, the second branch including M.sub.3, M.sub.4, M.sub.6, and M.sub.8; each of M.sub.1, M.sub.2, M.sub.3, M.sub.4, M.sub.7, and M.sub.8 is a metal-oxide-semiconductor field-effect transistor (MOSFET) and each of M.sub.5 and M.sub.6 is a FeFET; M.sub.1-gate is connected to a backup control signal input, B.sub.kp_input and M.sub.3-gate; M.sub.1-drain is connected to M.sub.2-drain; M.sub.1-drain is configured to be connected to the slave latch via the first branch; M.sub.1-source is connected to M.sub.5-source and M.sub.7-drain; M.sub.2-drain is connected to M.sub.1-drain; M.sub.2-drain is configured to be connected to the slave latch via the first branch; M.sub.2-gate is connected to a backup and restore control signal input, B.sub.kp+R.sub.str and M.sub.3-gate; M.sub.2-source is connected to M.sub.6-gate, M.sub.5-drain, M.sub.5-gate, M.sub.6-drain, and M.sub.3-source; M.sub.3-drain is connected to M.sub.4-drain; M.sub.3-drain is configured to be connected to the slave latch via the second branch; M.sub.3-gate is connected to B.sub.kp+R.sub.str and M.sub.1-gate; M.sub.3-source is connected to M.sub.5-gate, M.sub.6-drain, M.sub.5-drain, M.sub.2-source, and M.sub.6-gate; M.sub.4-drain is connected to M.sub.3-drain; M.sub.4-drain is configured to be connected to the slave latch via the second branch; M.sub.4-gate is connected to a backup control signal output, B.sub.kp_output; M.sub.4-source is connected to M.sub.6-source and M.sub.8-drain; M.sub.5-drain is connected to M.sub.2-source, M.sub.5-gate, M.sub.6-gate, M.sub.6-drain, and M.sub.3-source; M.sub.5-gate is connected to M.sub.3-source, M.sub.6-drain, M.sub.6-gate, M.sub.2-source, and M.sub.5-drain; M.sub.5-source is connected to M.sub.7-drain and M.sub.1-source; M.sub.6-drain is connected to M.sub.3-source, M.sub.5-gate, M.sub.6-gate, M.sub.5-drain, and M.sub.2-source; M.sub.6-gate is connected to M.sub.2-source, M.sub.5-drain, M.sub.5-gate, M.sub.6-drain, and M.sub.3-source; M.sub.6-source is connected to M.sub.4-source and M.sub.8-drain; M.sub.7-drain is connected to M.sub.1-source and M.sub.5-source; M.sub.7-gate is connected to a restore input control signal, R.sub.str; M.sub.7-source is connected to GND via the first branch; M.sub.8-drain is connected to M.sub.4-source and M.sub.6-source; M.sub.8-gate is connected to M.sub.7-gate; and M.sub.8-source is connected to GND via the second branch.

    4. (canceled)

    5. The NVM device recited in claim 1, wherein: the circuit topology is configured as a latch configured to have an input D; the latch comprising: a first transistor, M.sub.1, M.sub.1 having an M.sub.1-source, an M.sub.1-gate, and an M.sub.1-drain; a second transistor, M.sub.2, M.sub.2 having an M.sub.2-source, an M.sub.2-gate, and an M.sub.2-drain; a third transistor, M.sub.3, M.sub.3 having an M.sub.3-source, an M.sub.3-gate, and an M.sub.3-drain; a fourth transistor, M.sub.4, M.sub.4 having an M.sub.4-source, an M.sub.4-gate, and an M.sub.4-drain; a fifth transistor, M.sub.5, M.sub.5 having an M.sub.5-source, an M.sub.5-gate, and an M.sub.5-drain; a sixth transistor, M.sub.6, M.sub.6 having an M.sub.6-source, an M.sub.6-gate, and an M.sub.6-drain; a seventh transistor, M.sub.7, M.sub.7 having an M.sub.7-source, an M.sub.7-gate, and an M.sub.7-drain; an eighth transistor, M.sub.8, M.sub.8 having an M.sub.8-source, an M.sub.8-gate, and an M.sub.8-drain; a ninth transistor, M.sub.9, M.sub.9 having an M.sub.9-source, an M.sub.9-gate, and an M.sub.9-drain; a tenth transistor, M.sub.10, M.sub.10 having an M.sub.10-source, an M.sub.10-gate, and an M.sub.10-drain; an eleventh transistor, M.sub.11, M.sub.11 having an M.sub.11-source, an M.sub.11-gate, and an M.sub.11-drain; a twelfth transistor, M.sub.12, M.sub.12 having an M.sub.12-source, an M.sub.12-gate, and an M.sub.12-drain; a thirteenth transistor, M.sub.5b, M.sub.5b having an M.sub.5b-source, an M.sub.5b-gate, and an M.sub.5b-drain; a fourteenth transistor, M.sub.6b, M.sub.6b having an M.sub.6b-source, an M.sub.6b-gate, and an M.sub.6b-drain; each of M.sub.1, M.sub.2, M.sub.3, M.sub.4, M.sub.7, M.sub.8, M.sub.9, M.sub.10, and M.sub.11 is a metal oxide semiconductor field effect transistor (MOSFET); each of M.sub.5 and M.sub.6 is a FeFET; M.sub.1-drain being connected to M.sub.2-drain and a data input D; M.sub.1-gate being connected to a clock driver, CLK; M.sub.1-source being connected to M.sub.2-source, M.sub.3-gate, M.sub.5-gate, M.sub.7-gate, M-source, M.sub.12-source, M.sub.3-source, M.sub.9-source, M.sub.10-source, M.sub.5-drain, and M.sub.5b-drain; M.sub.2-drain being connected to M.sub.1-drain and data input D; M.sub.2-gate being connected to CLK; M.sub.2-source being connected to M.sub.1-source, M.sub.3-gate, M.sub.5-gate, M.sub.7-gate, M-source, M.sub.12-source, M.sub.3-source, M.sub.9-source, M.sub.10-source, M.sub.5-drain, and M.sub.5b-drain; M.sub.3-drain being connected to a voltage supply, V.sub.DD; M.sub.3-gate being connected to M.sub.1-source, M.sub.2-source, M.sub.5-gate, M.sub.7-gate, M.sub.11-source, M.sub.12-source, M.sub.3-source, M.sub.9-source, M.sub.10-source, M.sub.5-drain, and M.sub.5b-drain; M.sub.3-source can be connected to M.sub.1-source, M.sub.2-source, M.sub.5-gate, M.sub.7-gate, M.sub.11-source, M.sub.12-source, M.sub.3-gate, M.sub.9-source, M.sub.10 source, M.sub.5-drain, and M.sub.5b-drain; M.sub.4-drain being connected to V.sub.DD; M.sub.4-gate being connected to a data output QN, a data output Q, M.sub.6-gate, M.sub.8-gate, M.sub.4-source, M.sub.9-drain, M.sub.10-drain, M.sub.11-drain, M.sub.12-drain, M.sub.6b-drain, and M.sub.6-drain; M.sub.4-source being connected to data output QN, data output Q, M.sub.6-gate, M.sub.8-gate, M.sub.4-gate, M.sub.9-drain, M.sub.10-drain, M.sub.11-drain, M.sub.12-drain, M.sub.6b-drain, and M.sub.6-drain; M.sub.5-drain being connected to M.sub.1-source, M.sub.2-source, M.sub.5-gate, M.sub.7-gate, M.sub.11-source, M.sub.12-source, M.sub.3-source, M.sub.9-source, M.sub.10-source, and M.sub.5b-drain; M.sub.5-gate being connected to M.sub.1-source, M.sub.2-source, M.sub.5-drain, M.sub.7-gate, M.sub.11-source, M.sub.12-source, M.sub.3-source, M.sub.9-source, M.sub.10-source, M.sub.5b-gate, and M.sub.5b-drain; M.sub.5-source being connected to M.sub.7-drain; M.sub.5b-drain being connected to M.sub.1-source, M.sub.2-source, M.sub.5-gate, M.sub.7-gate, M.sub.11-source, M.sub.12-source, M.sub.3-source, M.sub.9-source, M.sub.10-source, and M.sub.5-drain; M.sub.5b-gate being connected to M.sub.5-gate; M.sub.5b-source being connected to ground, GND; M.sub.6-drain being connected to data output QN, data output Q, M.sub.6-gate, M.sub.8-gate, M.sub.4-source, M.sub.9-drain, M.sub.10-drain, M.sub.11-drain, M.sub.12-drain, M.sub.6b-drain, and M.sub.4-gate; M.sub.6-gate being connected to data output QN, data output Q, M.sub.6-drain, M.sub.6b-gate, M.sub.8-gate, M.sub.4-source, M.sub.9-drain, M.sub.10-drain, M.sub.11-drain, M.sub.12-drain, M.sub.6b-drain, and M.sub.4-gate; M.sub.6-source being connected to M.sub.8-drain; M.sub.6b-drain being connected to data output QN, data output Q, M.sub.6-gate, M.sub.8-gate, M.sub.4-source, M.sub.9-drain, M.sub.10-drain, M.sub.11-drain, M.sub.12-drain, M.sub.4-gate, and M.sub.6-drain; M.sub.6b-gate being connected to M.sub.6-gate; M.sub.6b-source being connected to GND; M.sub.7-drain being connected to M.sub.5-source; M.sub.7-gate being connected to M.sub.1-source, M.sub.2-source, M.sub.5-gate, M.sub.5-drain, M.sub.11-source, M.sub.12-source, M.sub.3-source, M.sub.9-source, M.sub.10-source, and M.sub.5b-drain; M.sub.7-source being connected to GND; M.sub.8-drain being connected to M.sub.6-source; M.sub.8-gate being connected to data output QN, data output Q, M.sub.6-gate, M.sub.4-gate, M.sub.4-source, M.sub.9-drain, M.sub.10-drain, M.sub.11-drain, M.sub.12-drain, M.sub.6b-drain, and M.sub.6-drain. M.sub.8-source can be connected to GND; M.sub.9-drain being connected to data output QN, data output Q, M.sub.6-gate, M.sub.8-gate, M.sub.4-source, M.sub.4-gate, M.sub.10-drain, M.sub.11-drain, M.sub.12-drain, M.sub.6b-drain, and M.sub.6-drain; M.sub.9-gate being connected to V.sub.DD; M.sub.9-source being connected to M.sub.1-source, M.sub.2-source, M.sub.5-gate, M.sub.7-gate, M.sub.11-source, M.sub.12-source, M.sub.3-source, M.sub.5-drain, M.sub.10-source, and M.sub.5b-drain; M.sub.10-drain being connected to data output QN, data output Q, M.sub.6-gate, M.sub.8-gate, M.sub.4-source, M.sub.9-drain, M.sub.4-gate, M.sub.11-drain, M.sub.12-drain, M.sub.6b-drain, and M.sub.6-drain; M.sub.10-gate being connected to GND; M.sub.10-source being connected to M.sub.1-source, M.sub.2-source, M.sub.5-gate, M.sub.7-gate, M.sub.11-source, M.sub.12-source, M.sub.3-source, M.sub.9-source, M.sub.5-drain, and M.sub.5b-drain; M.sub.11-drain being connected to data output QN, data output Q, M.sub.6-gate, M.sub.8-gate, M.sub.4-source, M.sub.9-drain, M.sub.10-drain, M.sub.4-gate, M.sub.12-drain, M.sub.6b-drain, and M.sub.6-drain; M.sub.11-gate being connected to CLK; M.sub.11-source being connected to M.sub.1-source, M.sub.2-source, M.sub.5-gate, M.sub.7-gate, M.sub.5-drain, M.sub.12-source, M.sub.3-source, M.sub.9-source, M.sub.10-source, and M.sub.5b-drain; M.sub.12-drain being connected to data output QN, data output Q, M.sub.6-gate, M.sub.8-gate, M.sub.4-source, M.sub.9-drain, M.sub.10-drain, M.sub.11-drain, M.sub.4-gate, M.sub.6b-drain, and M.sub.6-drain; M.sub.12-gate being connected to CLK; and M.sub.12-source being connected to M.sub.1-source, M.sub.2-source, M.sub.5-gate, M.sub.7-gate, M.sub.11-source, M.sub.5-drain, M.sub.3-source, M.sub.9-source, M.sub.10-source, and M.sub.5b-drain.

    6. The NVM device recited in claim 1, wherein: the circuit topology is configured as a latch configured to have a differential-driving input pair D/DN; the latch comprising: a first transistor, M.sub.1, M.sub.1 having an M.sub.1-source, an M.sub.1-gate, and an M.sub.1-drain; a second transistor, M.sub.2, M.sub.2 having an M.sub.2-source, an M.sub.2-gate, and an M.sub.2-drain; a third transistor, M.sub.3, M.sub.3 having an M.sub.3-source, an M.sub.3-gate, and an M.sub.3-drain; a fourth transistor, M.sub.4, M.sub.4 having an M.sub.4-source, an M.sub.4-gate, and an M.sub.4-drain; a fifth transistor, M.sub.5, M.sub.5 having an M.sub.5-source, an M.sub.5-gate, and an M.sub.5-drain; a sixth transistor, M.sub.6, M.sub.6 having an M.sub.6-source, an M.sub.6-gate, and an M.sub.6-drain; a seventh transistor, M.sub.7. M.sub.7 having an M.sub.7-source, an M.sub.7-gate, and an M.sub.7-drain; an eighth transistor, M.sub.8, M.sub.8 having an M.sub.8-source, an M.sub.8-gate, and an M.sub.8-drain; each of M.sub.1, M.sub.2, M.sub.3, M.sub.4, M.sub.7, and M.sub.8 is a metal oxide semiconductor field effect transistor (MOSFET); each of M.sub.5 and M.sub.6 is a FeFET; M.sub.1-drain being connected to a data input D; M.sub.1-gate being connected to a clock driver, CLK; M.sub.1-source being connected to M.sub.5-gate, M.sub.3-gate, M.sub.5-source, M.sub.2-source, M.sub.7-gate, M.sub.7-drain, a data output Q, a data output QN, M.sub.6-source, M.sub.8-drain, M.sub.8-gate, M.sub.6-gate, and M.sub.4-gate; M.sub.2-drain being connected to data input DN; M.sub.2-gate being connected to M.sub.1-gate; M.sub.2-source being connected to M.sub.5-gate, M.sub.3-gate, M.sub.5-source, M.sub.1-source, M.sub.7-gate, M.sub.7-drain, a data output Q, a data output QN, M.sub.6-source, M.sub.8-drain, M.sub.8-gate, M.sub.6-gate, and M.sub.4-gate; M.sub.3-drain being connected to a voltage supply, V.sub.DD; M.sub.3-gate being connected to M.sub.5-gate, M.sub.1-source, M.sub.5-source, M.sub.2-source, M.sub.7-gate, M.sub.7-drain, data output Q, data output QN, M.sub.6-source, M.sub.8-drain, M.sub.8-gate, M.sub.6-gate, and M.sub.4-gate; M.sub.3-source being connected to M.sub.5-drain; M.sub.4-drain being connected to V.sub.DD; M.sub.4-gate being connected to M.sub.5-gate, M.sub.3-gate, M.sub.5-source, M.sub.2-source, M.sub.7-gate, M.sub.7-drain, data output Q, data output QN, M.sub.6-source, M.sub.8-drain, M.sub.8-gate, M.sub.6-gate, and M.sub.1-source; M.sub.4-source being connected to M.sub.6-drain; M.sub.5-drain being connected to M.sub.3-source; M5-gate being connected to M.sub.1-source, M.sub.3-gate, M.sub.5-source, M.sub.2-source, M.sub.7-gate, M.sub.7-drain, data output Q, data output QN, M.sub.6-source, M.sub.8-drain, M.sub.8-gate, M.sub.6-gate, and M.sub.4-gate; M.sub.5-source being connected to M.sub.5-gate, M.sub.3-gate, M.sub.1-source, M.sub.2-source, M.sub.7-gate, M.sub.7-drain, data output Q, data output QN, M.sub.6-source, M.sub.8-drain, M.sub.8-gate, M.sub.6-gate, and M.sub.4-gate; M.sub.6-drain being connected to M.sub.4-source; M.sub.6-gate being connected to M.sub.5-gate, M.sub.3-gate, M.sub.5-source, M.sub.2-source, M.sub.7-gate, M.sub.7-drain, data output Q, data output QN, M.sub.6-source, M.sub.8-drain, M.sub.8-gate, M.sub.1-source, and M.sub.4-gate; M.sub.6-source being connected to M.sub.5-gate, M.sub.3-gate, M.sub.5-source, M.sub.2-source, M.sub.7-gate, M.sub.7-drain, data output Q, data output QN, M.sub.1-source, M.sub.8-drain, M.sub.8-gate, M.sub.6-gate, and M.sub.4-gate; M.sub.7-drain being connected to M.sub.5-gate, M.sub.3-gate, M.sub.5-source, M.sub.2-source, M.sub.7-gate, M.sub.1-source, data output Q, data output QN, M.sub.6-source, M.sub.8-drain, M.sub.8-gate, M.sub.6-gate, and M.sub.4-gate; M.sub.7-gate being connected to M.sub.5-gate, M.sub.3-gate, M.sub.5-source, M.sub.2-source, M.sub.1-source, M.sub.7-drain, data output Q, data output QN, M.sub.6-source, M.sub.8-drain, M.sub.8-gate, M.sub.6-gate, and M.sub.4-gate; M.sub.7-source being connected to ground, GND; M.sub.8-drain being connected to M.sub.5-gate, M.sub.3-gate, M.sub.5-source, M.sub.2-source, M.sub.7-gate, M.sub.7-drain, data output Q, data output QN, M.sub.6-source, M.sub.1-source, M.sub.8-gate, M.sub.6-gate, and M.sub.4-gate; M.sub.8-gate being connected to M.sub.5-gate, M.sub.3-gate, M.sub.5-source, M.sub.2-source, M.sub.7-gate, M.sub.7-drain, data output Q, data output QN, M.sub.6-source, M.sub.8-drain, M.sub.1-source, M.sub.6-gate, and M.sub.4-gate; and M.sub.8-source being connected to GND.

    7. The NVM device recited in claim 1, wherein: the circuit topology is configured as a latch configured to have a differential-driving input pair D/DN; the latch comprising: a first transistor, M.sub.1, M.sub.1 having an M.sub.1-source, an M.sub.1-gate, and an M.sub.1-drain; a second transistor, M.sub.2, M.sub.2 having an M.sub.2-source, an M.sub.2-gate, and an M.sub.2-drain; a third transistor, M.sub.3, M.sub.3 having an M.sub.3-source, an M.sub.3-gate, and an M.sub.3-drain; a fourth transistor, M.sub.4, M.sub.4 having an M.sub.4-source, an M.sub.4-gate, and an M.sub.4-drain; a fifth transistor, M.sub.5, M.sub.5 having an M.sub.5-source, an M.sub.5-gate, and an M.sub.5-drain; a sixth transistor, M.sub.6, M.sub.6 having an M.sub.6-source, an M.sub.6-gate, and an M.sub.6-drain; a seventh transistor, M.sub.7. M.sub.7 having an M.sub.7-source, an M.sub.7-gate, and an M.sub.7-drain; an eighth transistor, M.sub.8, M.sub.8 having an M.sub.8-source, an M.sub.8-gate, and an M.sub.8-drain; a ninth transistor, M.sub.9, M.sub.9 having an M.sub.9-source, an M.sub.9-gate, and an M.sub.9-drain; a tenth transistor, M.sub.10, M.sub.10 having an M.sub.10-source, an M.sub.10-gate, and an M.sub.10-drain; each of M.sub.1, M.sub.2, M.sub.3, M.sub.4, M.sub.9, and M.sub.10 is a metal oxide semiconductor field effect transistor (MOSFET); each of M.sub.5, M.sub.6, M.sub.7, and M.sub.8 is a FeFET; M.sub.1-drain being connected to a data input D; M.sub.1-gate being connected to a clock driver, CLK; M.sub.1-source being connected to M.sub.5-gate, M.sub.3-gate, M.sub.2-source, M.sub.7-gate, M.sub.9-gate, M.sub.5-source, M.sub.6-source, a data output Q, M.sub.6-gate, M.sub.4-gate, M.sub.7-drain, M.sub.8-drain, a data output QN, M.sub.8-gate, and M.sub.10-gate; M.sub.2-drain being connected to a data input DN; M.sub.2-gate being connected to M.sub.1-gate; M.sub.2-source being connected to M.sub.5-gate, M.sub.3-gate, M.sub.1-source, M.sub.7-gate, M.sub.9-gate, M.sub.5-source, M.sub.6-source, data output Q, M.sub.6-gate, M.sub.4-gate, M.sub.7-drain, M.sub.8-drain, data output QN, M.sub.8-gate, and M.sub.10-gate; M.sub.3-drain being connected to a voltage supply, V.sub.DD; M.sub.3-gate being connected to M.sub.5-gate, M.sub.1-source, M.sub.2-source, M.sub.7-gate, M.sub.9-gate, M.sub.5-source, M.sub.6-source, data output Q, M.sub.6-gate, M.sub.4-gate, M.sub.7-drain, M.sub.8-drain, data output QN, M.sub.8-gate, and M.sub.10-gate; M.sub.3-source being connected to M.sub.5-drain; M.sub.4-drain being connected to V.sub.DD; M.sub.4-gate being connected to M.sub.5-gate, M.sub.3-gate, M.sub.2-source, M.sub.7-gate, M.sub.9-gate, M.sub.5-source, M.sub.6-source, data output Q, M.sub.6-gate, M.sub.1-source, M.sub.7-drain, M.sub.8-drain, data output QN, M.sub.8-gate, and M.sub.10-gate; M.sub.4-source being connected to M.sub.6-drain; M.sub.5-drain being connected to M.sub.3-source; M.sub.5-gate c being connected to M.sub.1-source, M.sub.3-gate, M.sub.2-source, M.sub.7-gate, M.sub.9-gate, M.sub.5-source, M.sub.6-source, data output Q, M.sub.6-gate, M.sub.4-gate, M.sub.7-drain, M.sub.8-drain, data output QN, M.sub.8-gate, and M.sub.10-gate; M.sub.5-source being connected to M.sub.5-gate, M.sub.3-gate, M.sub.2-source, M.sub.7-gate, M.sub.9-gate, M.sub.1-source, M.sub.6-source, data output Q, M.sub.6-gate, M.sub.4-gate, M.sub.7-drain, M.sub.8-drain, data output QN, M.sub.8-gate, and M.sub.10-gate; M.sub.6-drain being connected to M.sub.4-source; M.sub.6-gate being connected to M.sub.5-gate, M.sub.3-gate, M.sub.2-source, M.sub.7-gate, M.sub.9-gate, M.sub.5-source, M.sub.6-source, data output Q, M.sub.1-source, M.sub.4-gate, M.sub.7-drain, M.sub.8-drain, data output QN, M.sub.8-gate, and M.sub.10-gate; M.sub.6-source being connected to M.sub.5-gate, M.sub.3-gate, M.sub.2-source, M.sub.7-gate, M.sub.9-gate, M.sub.5-source, M.sub.1-source, data output Q, M.sub.6-gate, M.sub.4-gate, M.sub.7-drain, M.sub.8-drain, data output QN, M.sub.8-gate, and M.sub.10-gate; M.sub.7-drain can be connected to M.sub.5-gate, M.sub.3-gate, M.sub.2-source, M.sub.7-gate, M.sub.9-gate, M.sub.5-source, M.sub.6-source, data output Q, M.sub.6-gate, M.sub.4-gate, M.sub.1-source, M.sub.8-drain, data output QN, M.sub.8-gate, and M.sub.10-gate; M.sub.7-gate can be connected to M.sub.5-gate, M.sub.3-gate, M.sub.2-source, M.sub.1-source, M.sub.9-gate, M.sub.5-source, M.sub.6-source, data output Q, M.sub.6-gate, M.sub.4-gate, M.sub.7-drain, M.sub.8-drain, data output QN, M.sub.8-gate, and M.sub.10-gate; M.sub.7-source can be connected to M.sub.9-drain; M.sub.10-drain can be connected to M.sub.8-source; M.sub.10-gate can be connected to M.sub.5-gate, M.sub.3-gate, M.sub.2-source, M.sub.7-gate, M.sub.9-gate, M.sub.5-source, M.sub.6-source, data output Q, M.sub.6-gate, M.sub.4-gate, M.sub.7-drain, M.sub.8-drain, data output QN, M.sub.8-gate, and M.sub.1-source; and M.sub.10-source can be connected to ground, GND.

    8-18. (canceled)

    19. The NVM device recited in claim 1, wherein: the circuit topology is configured as a 2-transistor (2T) memory cell; the 2T-memory cell comprising: a first transistor T.sub.1, a second transistor T.sub.2, a bit line, BL, a first Wordline, WLW, and a second Wordline, WLR; T.sub.1 being a metal oxide semiconductor field effect transistor (MOSFET) and T.sub.2 being a FeFET; T.sub.1 having a T.sub.1-source, a T.sub.1-gate, and a T.sub.1-drain; T.sub.2 having a T.sub.2-source, a T.sub.2-gate, and a T.sub.2-drain; WLW being configured to receive and/or transmit a write signal for write operations; WLR being configured to receive and/or transmit a read signal for read operations; T.sub.2-drain being connected to BL and WLW; T.sub.2-gate being connected to WLW; T.sub.2-source being connected to T.sub.1-drain; T.sub.1-gate being connected to WLR and BL; and T.sub.1-source being connected to ground, GND.

    20. The NVM device recited in claim 19, further comprising a plurality of 2T-memory cells arrange in a memory cell array.

    21. The NVM device recited in claim 20, wherein the memory cell array comprises: a first 2T-memory cell, a second 2T-memory cell, a third 2T-memory cell, a third 2T-memory cell, a fourth 2T-memory cell, a fifth 2T-memory cell, a sixth 2T-memory cell, a seventh 2T-memory cell, and an eighth 2T-memory cell, each memory cell having a T.sub.1 and a T.sub.2, wherein T.sub.1 is a MOSFET and T.sub.2 is a FeEFT, wherein: the first 2T-memory cell has a first T.sub.1 and a first T.sub.2; the second 2T-memory cell has a second T.sub.1 and a second T.sub.2; the third 2T-memory cell has a third T.sub.1 and a third T.sub.2; the fourth 2T-memory cell has a fourth T.sub.1 and a fourth T.sub.2; the fifth 2T-memory cell has a fifth T.sub.1 and a fifth T.sub.2; the sixth 2T-memory cell 124 has a sixth T.sub.1 and a sixth T.sub.2; the seventh 2T-memory cell has a seventh T.sub.1 and a seventh T.sub.2; the eighth 2T-memory cell 124 has an eighth T.sub.1 and a eighth T.sub.2; and a first BL, BL1, a second BL, BL2, a third BL, BL3, and a fourth BL, BL4; a first WLW, WLW1, a second WLW, WLW2, a first WLR, WLR1, and a second WLR, WLR2, wherein each of WLW1 and WLW2 is configured to receive and/or transmit a write signal for write operations, and each of WLR1 and WLR2 is configured to receive and/or transmit a read signal for read operations; the first cell T.sub.2-drain being connected to BL1 and WLW1; the first cell T.sub.2-gate being connected to WLW1; the first cell T.sub.2-source being connected to first cell T.sub.1-drain; the first cell T.sub.1-gate being connected to WLR1 and BL1; the first cell T.sub.1-source being connected to ground, GND; the second cell T.sub.2-drain being connected to BL2 and WLW1; the second cell T.sub.2-gate being connected to WLW1; the second cell T.sub.2-source being connected to second cell T.sub.1-drain; the second cell T.sub.1-gate being connected to WLR1 and BL2; the second cell T.sub.1-source being connected to GND; the third cell T.sub.2-drain being connected to BL3 and WLW1; the third cell T.sub.2-gate being connected to WLW1; the third cell T.sub.2-source being connected to third cell T.sub.1-drain; the third cell T.sub.1-gate being connected to WLR1 and BL3; the third cell T.sub.1-source being connected to GND; the fourth cell T.sub.2-drain being connected to BL4 and WLW1; the fourth cell T.sub.2-gate being connected to WLW1; the fourth cell T.sub.2-source being connected to fourth cell T.sub.1-drain; the fourth cell T.sub.1-gate being connected to WLR1 and BL4; the fourth cell T.sub.1-source being connected to GND; the fifth cell T.sub.2-drain being connected to BL1 and WLW2; the fifth cell T.sub.2-gate being connected to WLW2; the fifth cell T.sub.2-source being connected to fifth cell T.sub.1-drain; the fifth cell T.sub.1-gate being connected to WLR2 and BL1; the fifth cell T.sub.1-source being connected to GND; the sixth cell T.sub.2-drain being connected to BL2 and WLW2; the sixth cell T.sub.2-gate being connected to WLW2; the sixth cell T.sub.2-source being connected to sixth cell T.sub.1-drain; the sixth cell T.sub.1-gate being connected to WLR2 and BL2; the sixth cell T.sub.1-source being connected to GND; the seventh cell T.sub.2-drain being connected to BL3 and WLW2; the seventh cell T.sub.2-gate being connected to WLW2; the seventh cell T.sub.2-source being connected to seventh cell T.sub.1-drain; the seventh cell T.sub.1-gate being connected to WLR2 and BL3; the seventh cell T.sub.1-source being connected to GND; the eighth cell T.sub.2-drain being connected to BL4 and WLW2; the eighth cell T.sub.2-gate being connected to WLW2; the eighth cell T.sub.2-source being connected to eighth cell T.sub.1-drain; the eighth cell T.sub.1-gate being connected to WLR2 and BL4; and the eighth cell T.sub.1-source being connected to GND.

    22. The NVM device recited in claim 1, wherein: the circuit topology is configured as a 3-transistor (3T) memory cell; the 3T-memory cell comprising: a first transistor, T.sub.1, a second transistor, T.sub.2, a third transistor T.sub.3, a first bit line, BLW, a second bit line, BLR, a Wordline Write, WLW, a Wordline Read, WLR, and a Wordline-Readline, WLRL; each of T.sub.1 and T.sub.3 is a metal oxide semiconductor field effect transistor (MOSFET), and T.sub.2 is a FeFET; T.sub.1 has a T.sub.1-source, a T.sub.1-gate, and a T.sub.1-drain; T.sub.2 has a T.sub.2-source, a T.sub.2-gate, and a T.sub.2-drain; T.sub.3 has a T.sub.3-source, a T.sub.3-gate, and a T.sub.3-drain; T.sub.1-drain being connected to T.sub.2-gate; T.sub.1-gate being connected to WLW; T.sub.1-source being connected to BLW; T.sub.2-drain being connected to T.sub.3-source; T.sub.2-gate being connected to T.sub.1-drain; T.sub.2-source being connected to WLRW; T.sub.3-drain being connected to BLR; T.sub.3-gate being connected to WLR; T.sub.3-source being connected to T.sub.2-drain; at least one of BLW, WLW, and WLRW being connected to ground, GND; and WLR being connected to a voltage supply, V.sub.DD.

    23. The NVM device recited in claim 1, wherein: the circuit topology is configured as a 3-transistor (3T) memory cell; the 3T-memory cell comprising: a first transistor, T.sub.1, a second transistor, T.sub.2, a third transistor T.sub.3, a bit line, BL, a Wordline Write, WLW, a Wordline Read, WLR, and a Wordline-Readline, WLRL; each of T.sub.1 and T.sub.3 is a metal oxide semiconductor field effect transistor (MOSFET), and T.sub.2 is a FeFET; T.sub.1 has a T.sub.1-source, a T.sub.1-gate, and a T.sub.1-drain; T.sub.2 has a T.sub.2-source, a T.sub.2-gate, and a T.sub.2-drain; T.sub.3 has a T.sub.3-source, a T.sub.3-gate, and a T.sub.3-drain; T.sub.1-drain being connected to T.sub.2-gate; T.sub.1-gate being connected to WLW; T.sub.1-source being connected to BL; T.sub.2-drain being connected to T.sub.3-drain; T.sub.2-gate being connected to T.sub.1-drain; T.sub.2-source being connected to WLRW; T.sub.3-drain being connected to T.sub.2-drain; T.sub.3-gate being connected to WLR; and T.sub.3-source being connected to BL.

    24. The NVM device recited in claim 1, wherein: the circuit topology is configured as a backup and restore circuit (B&R circuit); the B&R circuit comprising: a first transistor, M.sub.1, M.sub.1 having an M.sub.1-source, an M.sub.1-gate, and an M.sub.1-drain; a second transistor, M.sub.2, M.sub.2 having an M.sub.2-source, an M.sub.2-gate, and an M.sub.2-drain; a third transistor, M.sub.3, M.sub.3 having an M.sub.3-source, an M.sub.3-gate, and an M.sub.3-drain; a fourth transistor, M.sub.4, M.sub.4 having an M.sub.4-source, an M.sub.4-gate, and an M.sub.4-drain; a first branch comprising M.sub.1, M.sub.3, and ground, GND; a second branch comprising M.sub.2, M.sub.4, and GND; each of M.sub.1 and M.sub.2 is a metal oxide semiconductor field effect transistor (MOSFET); each of M.sub.3 and M.sub.4 is a FeFET; M.sub.1-drain being connected to M.sub.3-source; M.sub.1-gate being connected to a restore signal input signal and M.sub.2-gate; M.sub.1-source being connected to GND; M.sub.2-drain being connected to M.sub.4-source; M.sub.2-gate being connected to M.sub.1-gate; M.sub.3-drain configured to be connected to a slave latch via the first branch; M.sub.3-drain being connected to M.sub.4-gate, M.sub.4-drain, M.sub.3-gate, and to the second branch; M.sub.3-gate being connected to M.sub.4-gate, M.sub.4-drain, M.sub.3-drain, and to the second branch; M.sub.3-source being connected to M.sub.1-drain; M.sub.4-drain configured to be connected to the slave latch via the second branch; M.sub.4-drain being connected to M.sub.3-gate, M.sub.3-drain, M.sub.4-gate, and to the first branch; M.sub.4-gate being connected to M.sub.3-gate, M.sub.3-drain, M.sub.4-drain, and to the first branch; and M.sub.4-source being connected to M.sub.2-drain.

    25. The NVM device recited in claim 1, wherein: the circuit topology is configured as a D-Flip Flop (DFF); the DFF comprising a master latch, a slave latch, and a backup and restore circuit (B&R circuit); the master latch comprising: a first master inverter M.sub.INV1, a second master inverter, M.sub.INV2, a third master inverter, M.sub.INV3, and a master transmission gate, M.sub.GATE; input of M.sub.INV1 being connected to a data input signal, D; output of M.sub.INV1 being connected to input of M.sub.INV2; input of M.sub.INV2 being connected to output of M.sub.INV1; output of M.sub.INV2 being connected to input of M.sub.INV3; input of M.sub.INV3 being connected to output of M.sub.INV2; output of M.sub.INV3 being connected to input of M.sub.GATE; input of M.sub.GATE being connected to output of M.sub.INV3; and output of M.sub.GATE being connected to input of M.sub.INV2 and output of M.sub.INV1; the slave latch comprising: a first slave inverter, S.sub.INV1, a second slave inverter, S.sub.INV2, a third slave inverter, S.sub.INV3, and a slave transmission gate, S.sub.GATE; input of S.sub.INV1 being connected to output of M.sub.INV2; input of S.sub.INV2 being connected to output of S.sub.INV1; output of S.sub.INV2 being connected to input of S.sub.INV3 and to a data output Q; input of S.sub.INV3 being connected to output of S.sub.INV2; output of S.sub.INV3 being connected to input of S.sub.GATE; and output of S.sub.GATE being connected to input of S.sub.INV2 and output of S.sub.INV1; and the B&R circuit comprising: a first transistor, M.sub.1, M.sub.1 having an M.sub.1-source, an M.sub.1-gate, and an M.sub.1-drain; a second transistor, M.sub.2, M.sub.2 having an M.sub.2-source, an M.sub.2-gate, and an M.sub.2-drain; a third transistor, M.sub.3, M.sub.3 having an M.sub.3-source, an M.sub.3-gate, and an M.sub.3-drain; a fourth transistor, M.sub.4, M.sub.4 having an M.sub.4-source, an M.sub.4-gate, and an M.sub.4-drain; a first branch comprising M.sub.1, M.sub.3, and ground, GND; a second branch comprising M.sub.2, M.sub.4, and GND; each of M.sub.1 and M.sub.2 is a metal oxide semiconductor field effect transistor (MOSFET); each of M.sub.3 and M.sub.4 is a FeFET; M.sub.1-drain being connected to M.sub.3-source; M.sub.1-gate being connected to a restore signal input signal and M.sub.2-gate; M.sub.1-source being connected to GND; M.sub.2-drain being connected to M.sub.4-source; M.sub.2-gate being connected to M.sub.1-gate; M.sub.3-drain configured to be connected to a slave latch via the first branch; M.sub.3-drain being connected to M.sub.4-gate, M.sub.4-drain, M.sub.3-gate, and to the second branch; M.sub.3-gate being connected to M.sub.4-gate, M.sub.4-drain, M.sub.3-drain, and to the second branch; M.sub.3-source being connected to M.sub.1-drain; M.sub.4-drain configured to be connected to the slave latch via the second branch; M.sub.4-drain being connected to M.sub.3-gate, M.sub.3-drain, M.sub.4-gate, and to the first branch; M.sub.4-gate being connected to M.sub.3-gate, M.sub.3-drain, M.sub.4-drain, and to the first branch; and M.sub.4-source being connected to M.sub.2-drain.

    26. The NVM device recited in claim 24, wherein: M.sub.3-drain being connected to output of S.sub.GATE, output of S.sub.INV1, and input of S.sub.INV2; M.sub.4-drain being connected to input of S.sub.INV3, output of S.sub.INV2, and data output Q.

    Description

    BRIEF DESCRIPTION OF THE DRAWINGS

    [0033] The above and other objects, aspects, features, advantages and possible applications of the present innovation will be more apparent from the following more particular description thereof, presented in conjunction with the following drawings. Like reference numbers used in the drawings may identify like components.

    [0034] FIG. 1 is an exemplary schematic showing an exemplary device structure of an embodiment of a P-type noncapacitive field effect transistor (NCFET) with externally connected BiFeO3 ferroelectric material.

    [0035] FIG. 2 is a graph showing an I.sub.DV.sub.G hysteresis curve with two stable nonvolatile states at V.sub.GS=0 for an embodiment of a NCFET.

    [0036] FIG. 3 is an exemplary schematic showing polarization switching by the gate voltage for embodiment of a NCFET.

    [0037] FIG. 4 is a graph showing an I.sub.DV.sub.G hysteresis curve around V.sub.G=0 for an embodiment of a P-type NCFET.

    [0038] FIG. 5 is an exemplary schematic showing an embodiment of a backup and restore (B&R) circuit.

    [0039] FIG. 6 is an exemplary schematic showing an embodiment of a D flip flop (DFF).

    [0040] FIG. 7 is an exemplary schematic showing an exemplary process flow for an embodiment of the DFF in a backup operation.

    [0041] FIG. 8 shows an exemplary process flow for an embodiment of the DFF in a restore operation.

    [0042] FIG. 9 a graph showing transient waveform snapshots of an embodiment of the DFF 120 with the CLK period equal to 4 ns during normal Power On operations. A few nS after power supply goes off, the internal nodes Q and QN were manually pulled down to ground to mimic real scenarios.

    [0043] FIG. 10 is a graph showing the impact on I.sub.DSV.sub.GS curves by varying ferroelectric layer thickness (T.sub.FE) (baseline 6 nm) on an embodiment of the NCFET.

    [0044] FIG. 11 is a graph showing the impact on I.sub.DSV.sub.GS curves by of changing ferroelectric layer area (A.sub.FE) (baseline 100% of 378 nm.sup.2) on an embodiment of the NCFET.

    [0045] FIG. 12 is a graph showing the impact on backup time and restore time by varying T.sub.FE on an embodiment of the NCFET.

    [0046] FIG. 13 is a graph showing the impact on backup time and restore time by varying A.sub.FE on an embodiment of the NCFET.

    [0047] FIG. 14 is a graph showing the impact on backup energy and restore energy by varying T.sub.FE on an embodiment of the NCFET.

    [0048] FIG. 15 is a graph showing the impact on backup energy and restore energy by varying A.sub.FE on an embodiment of the NCFET.

    [0049] FIG. 16 is a graph showing energy-delay performance overhead of an embodiment of a DFF under a supply voltage from 0.30 V to 0.80 V, wherein the kinetic coefficient is 0.25.

    [0050] FIGS. 17-20 are is graphs showing performance indicators for an embodiment of a DFF in regards to local mismatches in ferroelectric layer thickness and area in NCFETs used to make the DFF. FIG. 17 is a graph showing the impact on backup latency due to variations, FIG. 18 is a graph showing the impact on backup energy, FIG. 19 is a graph showing the impact on restore latency, and FIG. 20 is a graph showing the impact on restore energy.

    [0051] FIG. 21 is a graph showing a sample of power income versus time for a typical VLSI computing system for computation energy, restore energy, and backup energy.

    [0052] FIG. 22 is a graph showing energy harvesting utilization for a conventional volatile processor and a non-volatile processor.

    [0053] FIG. 23 is an exemplary schematic showing a set up for a conventional DFF device.

    [0054] FIG. 24 is an exemplary schematic showing an exemplary set up for an embodiment of an intrinsic nonvolatile area-efficient DFF device.

    [0055] FIG. 25 is an exemplary schematic showing an exemplary schematic for an embodiment of an N-type FeFET.

    [0056] FIG. 26 is an exemplary schematic showing an exemplary schematic for a capacitance network of an embodiment of an N-type FeFET.

    [0057] FIG. 27 is a graph showing I.sub.DSV.sub.G curves demonstrating steep-switching and hysteresis with the baseline MOSFET curve.

    [0058] FIG. 28 is a graph showing the effect of tuning ferroelectric negative capacitance of an embodiment of a FeFET.

    [0059] FIG. 29 is an exemplary schematic showing an embodiment of a slave latch configured with a differential-driving input pair D/DN using N-type FeFETs.

    [0060] FIG. 30 is an exemplary schematic showing an embodiment of a slave latch configured with a driving input D.

    [0061] FIG. 31 is a conventional CMOS volatile latch that was used as a baseline to compare to the latch topology of FIG. 29.

    [0062] FIG. 32 is an exemplary schematic showing a conventional CMOS volatile latch that was used as a baseline to compare to the latch topology of FIG. 30.

    [0063] FIG. 33 is an exemplary schematic showing an exemplary steady state operation of the latch topology of FIG. 29.

    [0064] FIG. 34 is an exemplary schematic showing an exemplary transition state operation of the latch topology of FIG. 29.

    [0065] FIG. 35 is a graph showing transient waveforms for sample and hold operations with a steady supply for an embodiment of the latch.

    [0066] FIG. 36 is a graph showing the polarization switching progress for an embodiment of the latch with a higher data-rate.

    [0067] FIG. 37 is a graph showing transient waveforms with backup and restore operations due to power failures for an embodiment of the latch.

    [0068] FIG. 38 is an exemplary schematic showing an embodiment of a slave latch configured with a differential-driving input pair D/DN using P-type FeFETs.

    [0069] FIG. 39 is an exemplary schematic showing an embodiment of a slave latch configured with a differential-driving input pair D/DN using both N-type FeFETs and P-type FeFETs.

    [0070] FIG. 40 is an exemplary schematic illustrating the operating mechanism of the latch topology of FIG. 30 during sampling, showing charging and discharging routes.

    [0071] FIG. 41 is an exemplary schematic illustrating the operating mechanism of the latch topology of FIG. 30 in a hold phase, showing charging and discharging routes.

    [0072] FIG. 42 is a graph showing the transient simulation waveforms of the latch topology of FIG. 30.

    [0073] FIG. 43 is a graph showing energy versus delay comparison between CMOS latches and embodiments of the latches for 1 fan-out driving strength. V.sub.DD ranges from 1.0V to 0.5V from left to right.

    [0074] FIG. 44 is a graph showing energy versus delay comparison between CMOS latches and embodiments of the latches for 4 fan-out driving strength (only CMOS transistors are increased to 4). V.sub.DD ranges from 1.0V to 0.5V from left to right.

    [0075] FIG. 45 is a graph showing supply voltage as a function of backup time for an embodiment of a latch.

    [0076] FIG. 46 is a graph showing supply voltage as a function of restore time for an embodiment of a latch.

    [0077] FIG. 47 is a graph showing supply voltage as a function of backup energy for an embodiment of a latch.

    [0078] FIG. 48 is a graph showing supply voltage as a function of restore energy for an embodiment of a latch.

    [0079] FIG. 49 is an exemplary schematic showing an embodiment of a DFF with its slave latch replaced with an embodiment of the latch topology of FIG. 29.

    [0080] FIG. 50 is an exemplary schematic showing another embodiment of a DFF with its slave latch replaced with an embodiment of the latch topology of FIG. 29.

    [0081] FIG. 51 is an exemplary schematic showing another embodiment of a DFF with its slave latch replaced with an embodiment of the latch topology of FIG. 30.

    [0082] FIG. 52 is an exemplary schematic showing a conventional CMOS DFF for comparison to an embodiment of the DFF disclosed herein.

    [0083] FIG. 53 is a graph showing the transient simulation waveforms of an embodiment of the DFF.

    [0084] FIG. 54 is a graph showing supply voltage as a function of backup energy for an embodiment of a DFF compared to conventional DFFs.

    [0085] FIG. 55 is a graph showing supply voltage as a function of restore energy for an embodiment of a DFF compared to conventional DFFs.

    [0086] FIG. 56 is a graph showing supply voltage as a function of backup time for an embodiment of a DFF compared to conventional DFFs.

    [0087] FIG. 57 is a graph showing supply voltage as a function of restore time f for an embodiment of a DFF compared to conventional DFFs.

    [0088] FIG. 58 is a graph comparing the energy versus delay between embodiments of the DFF and conventional DFF designs.

    [0089] FIG. 59 is an exemplary schematic showing a simulation setup for analyzing the impact of V.sub.TH variation on an embodiment

    [0090] FIG. 60 is a graph showing yield simulation results considering V.sub.TH variation at different supply voltages for an embodiment of a latch and an embodiment of a DFF.

    [0091] FIG. 61 is an exemplary schematic showing a schematic for an N-type FeFET.

    [0092] FIG. 62 is an exemplary schematic showing a fin-structured FeFET device.

    [0093] FIG. 63 is a graph showing a typical hysteretic G.sub.DSV.sub.GS extracted form one fin of a fin-structured FeFET device at V.sub.DS=10 mV.

    [0094] FIG. 64 is a graph showing an exemplary energy landscape plot for an embodiment of a FeFET.

    [0095] FIG. 65 is a graph showing static internal states with an embodiment of the FeFET biased at V.sub.GS=0.

    [0096] FIG. 66 is an exemplary schematic showing an embodiment of a 2T-memory cell.

    [0097] FIG. 67 is an exemplary schematic showing the operating status of the 2T-memory cell 1 of FIG. 66 in power-off mode and in power-on idle mode.

    [0098] FIG. 68 is an exemplary schematic showing the operating status of the 2T-memory cell 1 of FIG. 66 in voltage-mode read 0 and voltage-mode read 1.

    [0099] FIG. 69 is an exemplary schematic showing the operating status of the 2T-memory cell 1 of FIG. 66 in voltage-mode write 0 and voltage-mode write 1.

    [0100] FIG. 70 is a graph showing a snapshot of a SPICE transient simulation waveform of an embodiment of the memory cell array, showing polarization statuses for the FeFET transistors in the array.

    [0101] FIG. 71 is an exemplary schematic showing an embodiment of a 3T-memory cell having a two-bit line topology and a single-bit line topology.

    [0102] FIG. 72 is an exemplary schematic showing an embodiment of a 3T-memory cell in write mode using a two-step write method.

    [0103] FIG. 73 is a graph showing SPICE transient simulation waveforms for an embodiment of the memory cell.

    [0104] FIG. 74 is an exemplary schematic showing a comparison between supply voltage ranges required for write for a conventional memory cell and for an embodiment of the memory cell.

    [0105] FIG. 75 is a graph showing the simulated write energy per cell versus the write latency for embodiments of the memory cell, as compared to a conventional memory cell.

    [0106] FIG. 76 is a graph showing energy and latency for an embodiment of the memory cell as a function of .

    [0107] FIG. 77 is a graph showing the simulated read energy per cell versus read latency for an embodiment of the memory cell.

    [0108] FIG. 78 is a graph showing typical 10 nm n-type FeFET G.sub.DSV.sub.G curves with over 5 orders of magnitudes in the sensed drain-source channel conductions (G.sub.DS) between the bistable ON/OFF nonvolatile states sensed at zero V.sub.G.

    [0109] FIG. 79 is an exemplary schematic showing an embodiment of the 4T B&R circuitry.

    [0110] FIG. 80 is an exemplary schematic showing an embodiment of a DFF with an embodiment of the 4T B&R circuitry.

    [0111] FIG. 81 is an exemplary schematic showing an embodiment of the DFF in a backup operation.

    [0112] FIG. 82 is an exemplary schematic showing an embodiment of the DFF 120 in a restore operation.

    [0113] FIG. 83 is a graph showing transient waveforms of an embodiment of the DFF.

    [0114] FIG. 84 is a graph showing V.sub.DD v. backup time for embodiments of the DFF.

    [0115] FIG. 85 is a graph showing V.sub.DD v. backup energy for embodiments of the DFF.

    [0116] FIG. 86 is a graph showing V.sub.DD v. restore energy for embodiments of the DFF.

    [0117] FIG. 87 is a graph showing clock to Q energy v. clock to Q delay for embodiments of the DFF.

    [0118] FIG. 88 is a graph showing the backup time versus backup energy for an embodiment of the DFF and compares it to conventional DFF devices.

    [0119] FIG. 89 is a graph showing a normal mode energy-delay overhead analysis for an embodiment of the DFF and compares it to conventional DFF devices.

    DETAILED DESCRIPTION OF THE INVENTION

    [0120] The following description is of exemplary embodiments that are presently contemplated for carrying out the present invention. This description is not to be taken in a limiting sense, but is made merely for the purpose of describing the general principles and features of the present invention. The scope of the present invention is not limited by this description.

    [0121] Embodiments include nonvolatile a memory (NVM) device 100 that can be configured for logic switching and/or digital computing. For example, embodiments of the NVM device 100 can be configured as any one or combination of a memory cell 124, a D flip flop (DFF) 120, a Backup and Restore circuit (B&R circuit) 116, and/or a latch 118, 122 for a DFF 120.

    [0122] Referring to FIGS. 1-3, in some embodiments, the NVM device 100 can include at least one field effect transistor (FET) 102. The FET 102 can include a substrate 104 having a drain 106, a source 108, and a gate 110 formed thereon. The drain 106, source 108, and gate 110 can be separate by a metal layer 112. Embodiments of the FET 102 can be a ferroelectric FET (FeFET) 102. For example, the FeFET 102 may include a ferroelectric layer 114 within the gate 110 of the FET 102. It should be noted that a FeFET 102 can be referred to as a negative capacitance or differential capacitance FET (NCFET) because its charge decreases as the applied voltage increases within a certain voltage range. The FeFET 102 can be configured to exhibit a wide current-voltage (I-V) hysteresis covering zero gate bias. This may be achieved by tuning at least a portion of the thickness of the ferroelectric layer.

    [0123] Topologies for embodiments of the NVM devices 100 disclosed herein can include at least one FeFET 102 configured to have a wide current-voltage (I-V) hysteresis covering zero gate bias. For example, circuit topologies of embodiments of the NVM devices 100 can be configured to exploit the wide hysteresis feature that can be obtained from the use of an embodiment of the FeFET 102. Embodiments of the FeFET 102 can be configured to behave concurrently as a nonvolatile memory and a logic device with inherent compatibility with Boolean signaling. These and other features can reduce the complexity and energy consumption of the interface with logic gates. Additionally, embodiments of the FeFET 102 can provide a memory operation without static current during a write operation. In some embodiments, the FeFET 102, when used embodiments of the NVM devices 100 can be configured to exhibit a steep hysteresis edge and a high ratio between the two drain-source current states (I.sub.DS states) at a gate voltage (V.sub.G)=0. These two states can be the two locally stable states shown in FIG. 2. The I-V curve of FIG. 2 was obtained based on the LK-equation modeling method, with 10 nm predictive technology model (PTM) complementary metal-oxide-semiconductor (CMOS) FinFET as the integrated MOSFET. A FinFET is a tri-gate transistor in which the gate 110 is formed on at least two sides of the channel 111. The LK-equation coefficients are: alpha=1.05e9 m/F, beta=1e7 m.sup.5/F/coul.sup.2, and gamma=6e11 m.sup.9/F/coul.sup.4. One state can switch to the other by applying a sufficiently high-amplitude positive or negative V.sub.GS that exceeds the coercive voltage, as shown with an N-type FeFET in FIG. 3.

    [0124] Capacitance matching may be beneficial to obtain the characteristics in FIGS. 2-3. In addition, V.sub.TH shifting in the baseline MOSFET can be done to locate the hysteresis window around V.sub.G=0. This can include centering the hysteresis at V.sub.G=0. The shifting of V.sub.TH described herein can be done to generate NVM devices 100 with added non-volatility, as compared to conventional nonvolatile memory devices. As can be seen in FIG. 4 embodiments of the NVM device 100 can be generated that provide steep hysteresis edges with a slope below 10 mV/decade for above 7 orders in magnitude between the two I.sub.DS hysteresis states at V.sub.G=0. A steep-slope transition edge can be used to provide a wide gate voltage range in which the polarization of the NVM device 100 stays stable against noise. In addition, NVM devices 100 can be generated with a higher ON-state current and a lower OFF-state current. A higher ON-state current and a lower OFF-state current can lead to faster restore and immunity to device variations.

    [0125] Embodiments of the NVM device 100 can be configured as a B&R circuit 116 and/or a DFF 120 having an embodiment of the DFF 120 as part of its accessory circuitry. Such a NVM device 100 can be configured to maintain its state during a power outage and/or during an intermittent power supply. This can be useful for nonvolatile computing (e.g., prevent computation progress loss due to either an unexpected or scheduled power outage). For example, embodiments of the B&R circuit 116 and/or a DFF 120 can be used for backing up memory and DFF states to on-chip nonvolatile memory elements. Nonvolatile computing techniques can also be useful for energy harvesting, and in particular energy harvesting with Internet-of-Things (IoT) applications where frequent check-pointing is generally required under the notoriously intermittent supply provided by energy harvesting mechanisms. Nonvolatile computing techniques, via in situ backup methods, can also provide more energy savings in power-gating applications (e.g., cut off leakage power for higher energy efficiency).

    [0126] FIG. 5 shows an embodiment of a B&R circuit 116. The B&R circuit 116 can have a first transistor, M.sub.1. M.sub.1 can have an M.sub.1-source, an M.sub.1-gate, and an M.sub.1-drain. The B&R circuit 116 can have a second transistor, M.sub.2. M.sub.2 can have an M.sub.2-source, an M.sub.2-gate, and an M.sub.2-drain. The B&R circuit 116 can have a third transistor, M.sub.3. M.sub.3 can have an M.sub.3-source, an M.sub.3-gate, and an M.sub.3-drain. The B&R circuit 116 can have a fourth transistor, M.sub.4. M.sub.4 can have an M.sub.4-source, an M.sub.4-gate, and an M.sub.4-drain. The B&R circuit 116 can have a fifth transistor, M.sub.5. M.sub.5 can have an M.sub.5-source, an M.sub.5-gate, and an M.sub.5-drain. The B&R circuit 116 can have a sixth transistor, M.sub.6. M.sub.6 can have an M.sub.6-source, an M.sub.6-gate, and an M.sub.6-drain. The B&R circuit 116 can have a seventh transistor, M.sub.7. M.sub.7 can have an M.sub.7-source, an M.sub.7-gate, and an M.sub.7-drain. The B&R circuit 116 can have an eighth transistor, M.sub.8. M.sub.8 can have an M.sub.8-source, an M.sub.8-gate, and an M.sub.8-drain. Any one or combination of the transistors of the B&R circuit 116 can be a metal oxide semiconductor field effect transistor (MOSFET) or a FeFET 102.

    [0127] The B&R circuit 116 can further include a first branch 101 and a second branch 103. The first branch 101 can include M.sub.1, M.sub.2, M.sub.5, M.sub.7, and GND. The second branch 103 can include M.sub.3, M.sub.4, M.sub.6, and M.sub.8. Depending on the inputs, either the first branch 101 or the second branch 103 operates as a backup branch or a restore branch. For example, when the first branch 101 operates as a backup branch, the second branch 103 operates as a restore branch. When the first branch 101 operates as a restore branch, the second branch 103 operates as a backup branch. Particular note should be made to the cross-coupled circuit connection between M.sub.5 and the second branch 103 and M.sub.6 and the first branch 101. This can facilitate backup and restore operations in only one step without static current consumptions.

    [0128] In some embodiments, the B&R circuit 116 can be connected to a slave latch 118. (See FIG. 6). This can be done to generate a DFF 120. For example, the first branch 101 and the second branch 103 can be connected to a slave latch 118 to form a DFF 120.

    [0129] In at least one embodiment, M.sub.1, M.sub.2, M.sub.3, M.sub.4, M.sub.7, and M.sub.8 are MOSFETs. In at least one embodiment, M.sub.5 and M.sub.6 are FeFETs 102. M.sub.1-gate can be connected to a backup control signal input, B.sub.kp_input and M.sub.3-gate. M.sub.1-drain can be connected to M.sub.2-drain. M.sub.1-drain can be configured to be connected to a slave latch 118, which can be via the first branch 101. M.sub.1-source can be connected to M.sub.5-source and M.sub.7-drain. M.sub.2-drain can be connected to M.sub.1-drain. M.sub.2-drain can be configured to be connected to the slave latch 118, which can be via the first branch 101. M.sub.2-gate can be connected to a backup and restore control signal input, B.sub.kp+R.sub.str and M.sub.3-gate. M.sub.2-source can be connected to M.sub.6-gate, M.sub.5-drain, M.sub.5-gate, M.sub.6-drain, and M.sub.3-source. M.sub.3-drain can be connected to M.sub.4-drain. M.sub.3-drain can be configured to be connected to the slave latch 118, which can be via the second branch 103. M.sub.3-gate can be connected to B.sub.kp+R.sub.str and M.sub.1-gate. M.sub.3-source can be connected to M.sub.5-gate, M.sub.6-drain, M.sub.5-drain, M.sub.2-source, and M.sub.6-gate. M.sub.4-drain can be connected to M.sub.3-drain. M.sub.4-drain can be configured to be connected to the slave latch 118, which can be via the second branch 103. M.sub.4-gate can be connected to a backup control signal output, B.sub.kp_output. M.sub.4-source can be connected to M.sub.6-source and M.sub.8-drain. M.sub.5-drain can be connected to M.sub.2-source, M.sub.5-gate, M.sub.6-gate, M.sub.6-drain, and M.sub.3-source. M.sub.5-gate can be connected to M.sub.3-source, M.sub.6-drain, M.sub.6-gate, M.sub.2-source, and M.sub.5-drain. M.sub.5-source can be connected to M.sub.7-drain and M.sub.1-source. M.sub.6-drain can be connected to M.sub.3-source, M.sub.5-gate, M.sub.6-gate, M.sub.5-drain, and M.sub.2-source. M.sub.6-gate can be connected to M.sub.2-source, M.sub.5-drain, M.sub.5-gate, M.sub.6-drain, and M.sub.3-source. M.sub.6-source can be connected to M.sub.4-source and M.sub.8-drain. M.sub.7-drain can be connected to M.sub.1-source and M.sub.5-source. M.sub.7-gate can be connected to a restore input control signal, R.sub.str. M.sub.7-source can be connected to ground, GND, which can be via the first branch 101. M.sub.8-drain can be connected to M.sub.4-source and M.sub.6-source. M.sub.8-gate can be connected to M.sub.7-gate. M.sub.8-source can be connected to GND, which can be via the second branch 103.

    [0130] Referring to FIG. 6, in some embodiments the B&R circuit 116 can be used to generate a DFF 120. For example, embodiments of the DFF 120 can include a master latch 122 and a slave latch 118 in connection with an embodiment of the B&R circuit 116. In some embodiments, the DFF 120 can include a master latch 122 and a slave latch 118 in connection with the B&R circuit 116, and be configured for digital computing operations (e.g., backup and restore purposes). In at least one embodiment, the back and restore operations can be associated with the slave latch 118 only.

    [0131] The master latch 122 can have a first master inverter M.sub.INV1, a second master inverter, M.sub.INV2, a third master inverter, M.sub.INV3, and a master transmission gate, M.sub.GATE. The input of M.sub.INV1 can be connected to a data input signal, D. The output of M.sub.INV1 can be connected to the input of M.sub.INV2. The input of M.sub.INV2 can be connected to the output of M.sub.INV1. The output of M.sub.INV2 can be connected to the input of M.sub.INV3. The input of M.sub.INV3 can be connected to the output of M.sub.INV2. The output of M.sub.INV3 can be connected to the input of M.sub.GATE. The input of M.sub.GATE can be connected to the output of M.sub.INV3. The output of M.sub.GATE can be connected to the input of M.sub.INV2 and the output of M.sub.INV1.

    [0132] The slave latch 118 can have a first slave inverter, S.sub.INV1, a second slave inverter, S.sub.INV2, a third slave inverter, S.sub.INV3, and a slave transmission gate, S.sub.GATE. The input of S.sub.INV1 can be connected to the output of M.sub.INV2. The input of S.sub.INV2 can be connected to the output of S.sub.INV1. The output of S.sub.INV2 can be connected to the input of S.sub.INV3 and to a data output Q. The input of S.sub.INV3 can be connected to the output of S.sub.INV2. The output of S.sub.INV3 can be connected to the input of S.sub.GATE. The output of S.sub.GATE can be connected to the input of S.sub.INV2 and the output of S.sub.INV1.

    [0133] A clock driver, CLK can be used to generate an in-phase clock signal, c, and opposite-phase clock signal, cn, for M.sub.INV1, M.sub.GATE, S.sub.INV1, and/or S.sub.GATE. Embodiments of the CLK can include a first clock inverter, CLK.sub.INV1, having an output connected to an input of a second clock inverter, CLK.sub.INV2. CLK.sub.INV1 can be configured to generate cn. CLK.sub.INV2 can be configured to generate c. Each of M.sub.GATE and S.sub.GATE can be a gate circuit for transmitting or blocking the output signal from the master latch 122 or slave latch 118, respectively, in response to the clock signal from CLK. For example, the DFF 120 can be configured such that each of M.sub.GATE and S.sub.GATE passes the output signal of the master latch 122 or slave latch 118, respectively, when the clock signal is HIGH (e.g., M.sub.GATE or S.sub.GATE becomes conductive). Each of M.sub.GATE and S.sub.GATE can be configured to block the output signal of the master latch 116 or slave latch 118, respectively, when the clock signal is LOW (e.g., M.sub.GATE or S.sub.GATE becomes non-conductive).

    [0134] Each of M.sub.1-drain and M.sub.2-drain can be connected to the output of S.sub.GATE, the output of S.sub.INV1, and the input of S.sub.INV2. For example, the first branch 101 can be connected to the output of S.sub.GATE, the output of S.sub.INV1, and the input of S.sub.INV2. Each of M.sub.3-drain and M.sub.4-drain can be connected to the input of S.sub.INV3, the output of S.sub.INV2, and data output Q. For example, the second branch 103 can be connected to the input of S.sub.INV3, the output of S.sub.INV2, and data output Q.

    [0135] In some embodiments, when both B.sub.k and R.sub.str are low, the interface transistors (M.sub.1, M.sub.2, M.sub.3, and M.sub.4) between the slave latch 118 and the B&R circuit 116 are turned OFF by the gate signal B.sub.k and R.sub.str. This can cause the master latch 122 and slave latch 118 portions of the DFF 120 to function the same as a conventional positive-edge triggered DFF.

    [0136] FIG. 7 shows the DFF 120 circuit state transition in the slave latch 118 during a backup operation. In a backup operation, a feedback network is generates. For example, when a supply outage is about to come, the backup control signal B.sub.kp becomes high and turns ON the interface transistors (M.sub.1, M.sub.2, M.sub.3, and M.sub.4). Note that the pull-down transistors (M.sub.7 and M.sub.8), gated by R.sub.str, are turned OFF. Using Q=1 (corresponding to a high supply voltage, V.sub.DD) and QN=0 (corresponding to GND), the feedback network quickly biases M.sub.5 and M.sub.6 to switch to (or maintain) a positive polarization for M.sub.5 and a negative polarization for M.sub.6, respectively. The polarization switching is straightforward as the M.sub.5-gate is biased at voltage levels opposite to M.sub.5-drain and M.sub.5-source (e.g, V.sub.DDV.sub.TH for a high voltage level and GND at a low level). Additionally, M.sub.6-gate is biased at voltage levels opposite to M.sub.6-drain and M.sub.6-source terminals (e.g, V.sub.DDV.sub.TH for a high voltage level and GND at a low level). After the polarization switching is accomplished, the removal of V.sub.DD (the removal of V.sub.DD being a supply outage) will not affect the stored polarization states, regardless of the B.sub.kp and R.sub.str control signal levels. Note that the backup operation does not need to change the polarization if the state of the previous backup is the same. Operations with Q=0 (corresponding to GND) and QN=1 (corresponding to a high supply voltage, V.sub.DD) would be similar.

    [0137] FIG. 8 shows the DFF 120 circuit state transition for a restore operation. During the entire restore operation, the CLK and B.sub.kp are set to be low (C=0 and CN=1), and R.sub.str is set to be high. This can guarantee that the slave latch 118 is isolated from the master latch 122. As a result, the sensed resistance from node Q and to GND and from QN to V.sub.DD determines the final settled Q and QN voltage levels. For the positively polarized FeFET (either M.sub.5 or M.sub.6) its drain-to-source resistance is orders of magnitude lower than the other negatively polarized FeFET (either M.sub.6 or M.sub.5), which leads to a much stronger pull-down effect on the settling of the branch within which M.sub.5 or M.sub.6 is located. The positive feedback network can further enhance the difference in magnitude, and finally lead to a full settling down as V.sub.DD recovers.

    [0138] FIG. 9 is a transient waveform snapshot, showing operations of an embodiment of the DFF 120 with a steady V.sub.DD and backup and restore operations due to power failures. The clock frequency was set to 0.25 GHz when the power supply was stable. It should be noted, however, that the clock frequency can be much faster because the isolated accessory backup and restore circuitry has negligible impact on the normal operation. To prevent the backup and restore operations from being interrupted, however, CLK can be kept low. The polarization state, as shown in FIG. 9 remains stable in the power-OFF periods. Thanks to the simple timing requirement and the small control load, there is no need for a second supply network to deliver power for the control signals.

    [0139] It should be noted that embodiments of the DFF 120 and/or B&R circuit 116 can be built with P-type transistors connecting to V.sub.DD with effective control signals at a low voltage.

    [0140] Any one or combination of the parameters of any one or combination of FeFETs 102 can be tuned by adjusting the thickness, T.sub.FE, of the ferroelectric layer 114 and/or the area, A.sub.FE, of the ferroelectric layer 114. Adjusting T.sub.FE and/or A.sub.FE cab facilitate generating an NVM device 100 with improved energy-delay overhead during normal operations, improved backup and restore energy and delay, improved retention time, and improved yield and reliability. Improving the backup and restore energy can be beneficial for NVM devices 100 used in energy-harvesting systems experiencing intermittent power supplies. Conventional nonvolatile memory devices are limited in improvements to overall energy efficiency, as more energy spent for backup and restore operations generally results in less energy for computation. For example, for check-pointing applications, the backup and restore energy indicates a certain period of power-off time (break-even time (BET)), below which no energy savings could be achieved. Improved backup and restore time can also be beneficial for some applications when a fast response is preferred (e.g., fine-time-granularity power-gating scenarios and fast-response processors).

    [0141] FIG. 10 shows the impact on I.sub.DSV.sub.GS curves by varying T.sub.FE (baseline 6 nm) on an embodiment of the FeFET 102. FIG. 11 shows the impact on I.sub.DSV.sub.GS curves by of changing A.sub.FE (baseline 100% of 378 nm.sup.2) on an embodiment of the FeFET 102. FIG. 12 shows the impact on backup time and restore time by varying T.sub.FE on an embodiment of the FeFET 102. FIG. 13 shows the impact on backup time and restore time by varying A.sub.FE on an embodiment of the FeFET 102. FIG. 14 shows the impact on backup energy and restore energy by varying T.sub.FE on an embodiment of the FeFET 102. FIG. 15 shows the impact on backup energy and restore energy by varying A.sub.FE on an embodiment of the FeFET 102. In FIGS. 10-15, V.sub.DD=0.5V, kinetic coefficient =0.25, alpha=1.05e9 m/F, beta=1e7 m.sup.5/F/coul.sup.2, and gamma=6e11 m.sup.9/F/coul.sup.4.

    [0142] FIGS. 10-15 show how changes in T.sub.FE and A.sub.FE affect the I-V characteristics and the performance of a DFF 120 using an embodiment of the FeFET 102. It can be seen that increasing T.sub.FE can increase the coercive voltage or energy barrier to flip the polarization, leading to longer retention time and more time to switch the polarization. A larger T.sub.FE can also reduce the restore time with a higher ON/OFF resistance ratio and a lower ON-state resistance. It can also be seen that variation of T.sub.FE from 5 nm to 7 nm slightly affects the backup and restore energy by less than 10%. Meanwhile, decreasing A.sub.FE also changes the capacitance matching between CFE and CMOS, leading to a different I-V with a higher coercive voltage, a lower ON-state current, and longer polarization switching time. Considering the inevitable T.sub.FE and A.sub.FE variations in the fabrication process, T.sub.FE and A.sub.FE should be carefully optimized considering the supply voltage range, the retention model, and the application requirements on the retention time, and backup and restore energy and latency.

    [0143] A design performance evaluation using SPICE simulations was conducted using an embodiment of the DFF 120. T.sub.FE was set to 6 nm and A.sub.FE was set to 378 nm.sup.2 (equal to 3fin_widthchannel_length) for one fin, for the optimized tradeoff. These parameter values, unless otherwise stated, were be used in the performance evaluation. A physics-based ferroelectric capacitance model in was employed to build FeFETs 102 with 10 nm PTM CMOS FinFET as the integrated MOSFET for the simulation. In the model, the ferroelectric material was calibrated by experimental results of lead zirconium titanate (PZT) films on hafnium oxide (HfO.sub.2) buffer. To reflect different polarization switching speed, in the FeFET model, the kinetic coefficient was varied from 0.04 to 0.25. The baseline CMOS volatile DFF (a conventional DFF, which is annotated as CMOS DFF in FIG. 16) was optimized with the minimum area and a similar clock-to-Q delay between 0 and 1 outputs (the number of fins for N-type MOS (NMOS) and P-type MOS (PMOS) is 1 and 2, respectively). The DFFs 120 were simulated with a 2.0 fF load capacitor and 20 ps rising and falling time for D and CLK inputs.

    [0144] It is contemplated that for DFFs 120 used in practical applications, energy-delay performance would be critical because the DFF 120 would still operate with a steady supply for a large portion of time. Therefore, it is meaningful that the additional acquired non-volatility does not cause high energy-delay overheads. FIG. 16 shows these overheads over the baseline CMOS volatile DFF design. Due to the normally-OFF configuration of the backup and restore circuitry, the energy-delay product (EDP) overhead is lower than 2.1% for V.sub.DDs above 0.4 V. If a larger-size baseline DFF is used, this EDP overhead becomes even more negligible, because the backup and restore circuitry does not need to be scaled up by the same ratio due to the low (high) OFF-state (ON-state) FeFET resistance. In addition, thanks to the normally-OFF configuration, the additional backup and restore operations have little impact on the DFF setup time and hold time requirement.

    [0145] With semiconductor manufacturing, a process corner is a design-of-experiments technique that refers to a variation of fabrication parameters. Process corners represent the extremes of these parameter variations within which a circuit that has been etched onto the wafer must function correctly. A circuit running on devices fabricated at these process corners may run slower or faster than specified and at lower or higher temperatures and voltages, but defining bounds of these variations provides a means to measure whether the circuit is able to function satisfactorily. In order to verify the robustness of a circuit design, corner lots can be fabricated (e.g., groups of wafers with process parameters adjusted according to extremes), and used for testing. Shmoo plots can be used to identify the boundary limit beyond which a device begins to fail. Corner-lot analysis can be an effective means of testing in digital electronics. The naming convention of the process corners includes identifying three process corners: 1) typical-typical (TT) process corner, the slow-slow (SS) process corner, and a fast-fast (FF) process corner. Existing nonvolatile memory and DFF designs suffer from the non-idealities of the nonvolatile storage devices inside, especially the variations and low resistance ratio between different states of resistive memory devices. In such approaches, the worst-corner devices often greatly limit the overall system performance. For example, write pulse duration for conventional devices is much longer than average to ensure high yield, resulting in high energy consumption. Therefore, it is important to analyze how the DFF 120 performs with FeFET variations.

    [0146] FIGS. 10-15 demonstrate how embodiments of the DFF 120 behave with global T.sub.FE and A.sub.FE variations (all devices vary from the design target by the same amount). FIGS. 17-20 provide more scenarios and data analyses to account for local mismatches (i.e., the two FeFETs in one DFF 120 having different T.sub.FE). In FIGS. 17-20, the curves with square indictors are for three sets of the DFF 120, where the results represent operating in a range of V.sub.DD with T.sub.FE diverting away from 6 nm by 10% to +5%. The curves with oval indicators are for conventional DFF devices. The curves with triangle indicators are for conventional iron capacitive (FeCap) DFF devices. These simulation results show that the major impact was on the backup latency in low V.sub.DD scenarios, while the impact on other metrics was comparatively much less significant than that brought by a different supply voltage. The impact of additional noise that causes a non-zero initial Q/QN voltage opposite to the desired value was also analyzed through comprehensive simulations. Noise up to 200 mV was fully tolerable for correct operations, even with the above mentioned local FeFET mismatches. Such unwanted initial charge at Q or QN will be quickly discharged by the restore branches. Proper timing, the low ON-state and high OFF-state resistance of the FeFETs at different polarization states enable this feature.

    [0147] The kinetic coefficient affects the polarization switching time significantly. Different practical kinetic coefficient values were adopted in the simulations to reflect different polarization switching times, as shown in Table 1.

    TABLE-US-00001 TABLE 1 Performance Comparisons between DFF Designs Con- Con- Con- Embodiment ventional ventional ventional of device device device the disclosed measured simulated simulated* DFF** Tech. size 130 nm 710 nm 180 nm 10 nm Voltage 1.5 V 1.0 V 1.8 V 0.3 V-0.8 V Material PZT MJT ReRAM 6 nm HfO2, Capacitive PZT device P = 0.04, p = 0.10, p = 0.25 T.sub.Backup+Restore 2.67 S >10 S 1.3 S 277 pS, 583 pS, 1.29 pS E.sub.Backup+Restore 2.4 pJ 382 fJ 735 fJ 1.38 fJ Break-Even / 0.83 1.47 mS 55.9 nS Time S@25 C. *The results are for a conventional topology DFF of operating at 0.8 V supply (rise to 2.4 V for ReRAM write) for the shortest break-even time. **Backup and restore performance in this table is simulated at 0.5 V supply. MJT = multi-junction technology ReRAM = resistive Random Access Memory

    [0148] The data in FIGS. 17-20 show a comparison of the backup and restore performance of the DFF 120 with conventional DFF designs. The graphs show that the DFF 120 exhibits more than 6.0 reduction in the restore energy and 30 reduction in the backup energy. The DFF 120 also performs better in backup latency, and significantly outperforms the others with more than 50% reduction in restore latency. In addition, the DFF 120 works with general DFFs based on master-slave latch topologies, which is superior to a design that only works when the baseline DFF has set/reset ports. During restore operations, conventional DFF designs could not fully eliminate the static current when the FeFET of that DFF was in the low-resistance state. The improvement with the DFF 120 stem from the deeply embedded logic-in-memory operation due to the simple circuit structure that can carry out the backup and restore operations in only one step without static current consumptions.

    [0149] Table 1 also summarizes the DFF 120 overall performance in comparison with the conventional designs. One of the strongest advantages of the DFF 120 over conventional designs is the orders of magnitude lower energy for backup and restore operations. Such energy savings partly come from the capability of FeFETs 102 to operate effectively at a lower voltage. Two more important factors are: (a) the fundamentally different 3-terminal FeFET device operating in a novel cross-coupled circuitry that avoids static FeFET drain-source current during backup and restore operations; (b) FeFETs of a small size that can still ensure fast and robust operations with a high ON/OFF state resistance ratio even in the presence of significant local and global variations. In contrast, existing resistive memory elements in conventional DFF designs are continuously drawing current (because of their inherent two-terminal device feature) for a long period of time to ensure yield (because of required-write-time duration variations with a much lower resistance ratio). For capacitive nonvolatile memory devices, their power inefficiency arises from a complex access interface and a large capacitance value. The low-energy backup and restore operations in the DFF 120, however, enables higher-efficiency nonvolatile computing applications. For energy harvesting systems with an intermittent supply, the saved backup and restore energy could be used for computing, leading to more forward progress and higher quality of service (QoS). For general power-gating systems, the lower backup and restore energy leads to a shorter break-even time (BET) versus the leakage energy of an idle unit, indicating significant expansion of opportunity for energy savings from fine-grained power-gating.

    [0150] As noted herein, FeFETs 102, exhibiting steep-switching capability at a low voltage and the associated benefits for implementing energy-efficient Boolean logic, can be exploited to generate embodiments of the B&R circuit 116 and/or embodiments of the DFF 120. Embodiments of the DFF 120 consumes negligible static current in backup and restore operations, and remains robust even with significant global and local ferroelectric material variations across a wide 0.3 V-0.8 V supply voltage range, allowing the DFF 120 to achieve energy-efficient and low-latency backup and restore operations. Embodiments of the DFF 120 can have an ultra-low energy-delay overhead, below 2.1% in normal operations, and can operate using the same voltage supply as the Boolean logic elements with which it connects. This can facilitate energy-efficient nonvolatile computing in energy-harvesting and power-gating applications.

    [0151] Embodiments of the NVM device 100 can be configured as a latch 118, 122. For example, any of the slave latches 118 and/or master latches 122 can include an embodiment of the FeFET 102 to provide an embedded logic-in-memory operation (i.e., an intrinsic nonvolatile area-efficient latch). Embodiments of the latch 118, 122 can be used to provide an improved DFF 120.

    [0152] For example, conventional on-chip state backup solutions for DFF have a bottleneck of significant energy and/or latency penalties that can limit overall energy efficiency and computing progress. In addition, existing techniques generally rely on external controls that can limit compatibility and increases system complexity. Accordingly, advancements in nonvolatile computing can be achieved by use of an embodiment of an intrinsic nonvolatile area-efficient latch 118, 122 and/or DFF 120. Some embodiments of the latch 118, 122 and/or DFF 120 can be designed using embodiments of the FeFET 102. Some embodiments of the NVM device 100 using an embodiment of the latch 118, 122 and/or an embodiment of the DFF 102 can operate to consume fJ-level energy and ns-level intrinsic latency for a backup plus restore operation (e.g., 2.4 fJ in energy and 1.1 ns in time for a DFF 120 with a supply power of 0.80V).

    [0153] Scheduled power-gating of very large scale integration (VLSI) computing systems has been widely adopted in both low-power portable devices and high-performance cloud server centers to cut off static leakage power. With such systems states of the registers and flip-flops in the pipelining logic should be backed up to prevent loss of computation status if the supply is removed. Similarly, mandatory state backup and restore operations can be required for battery-less portable devices powered by energy-harvesting techniques. This is because the ambient energy sources, such as vibration, photovoltaics, and radio, are essentially intermittent even with sophisticated design methods. FIG. 21 shows a sample of power income versus time for a typical VLSI computing system for computation energy, restore energy, and backup energy. The power outage failures have a strong impact on the computation progress and the overall energy efficiency of IoT computing. On the one hand, the computing system will lose its computation states if these states are not successfully backed up before the power failure. With conventional systems, even when techniques of check-pointing are applied to reduce the chance of progress loss, significant overheads of energy and latency still exist for each backup and restore operation. (See FIG. 22). If the backup data are stored into out-of-chip nonvolatile memory, huge energy and latency are noticeable, mainly caused by the long-distance data transmission and constrained parallelism. It is also noted that, although a larger energy storage capacitor buffer can be used to smooth the power trace, it cannot reduce the amount of energy for each backup or restore operation. A larger capacitor also results in larger leakage current and more accumulating time to respond till it reaches an appropriate voltage level for supply regulation.

    [0154] Embedding nonvolatile memory (NVM) into the same chip can improve nonvolatile processing (NVP) by generated a DFF 120 configured to back up the computation states of each DFF into a local on-chip NVM. Table 2 summarizes some existing DFF designs based on ferroelectric capacitor devices, MTJ devices, ReRAM devices, and compares the pros and cons against an embodiment of the DFF 120. If distributed NVM cells and interface circuitry are placed close to each DFF to build a nonvolatile DFF for local parallel backup, as illustrated in FIG. 23, the backup/restore operation will be much faster but still consume high energy because of the duplicated interface circuit between the DFF and NVM cells. The high current one nonvolatile DFF backup/restore operation also limits the plausible parallelism.

    TABLE-US-00002 TABLE 2 Performance Comparison of Conventional DFF Designs to an Embodiment of an Intrinsic Nonvolatile Area-efficient DFF Device Embodiment Conventional DFF Devices of the DFF Year 2014 2014 2014 2013 2016 2018 Feature size 130 nm 130 nm 45 nm 180 nm 10 nm 10 nm Nonvolatile PZT PZT MTJ Al/TiO.sub.2/Al NCFET with HfO.sub.2 and material Capacitor Capacitor ReRAM PZT Retention 10 hours to 10 10 years 10 years Same as PZT capacitor in Time years; varying by design theory Endurance Vaiying by matenal; >10.sup.15 10.sup.5-10.sup.10; Same as PZT capacitor in possibly >10.sub.15 10.sup.15 by 2014 theory Voltage 1.5 V 1.5 V 1.1 V 1.8 V 0.4 V-0.8 V 0.4 V-1.0 V 25% more Area overhead 64% 49% 2% 35% transistors Backup time 1.64 s 2.22 s 909 ps 10 ns @ 2.4 V 1.4 ns @ 0.5 V 1.0 ns @ 0.8 V Restore time 1.25 s 2.2 s 177 ps 1.3 s @ 0.4 V 75 ps @ 0.5 V 56 ps @ 0.8 V Backup energy 2.4 pJ 3.44 pJ 82.2 fJ 735 fJ 7.0 fJ @ 0.5 V 1.3 fJ @ 0.8 V Restore energy 2.34 pJ in total 735 fJ 9.0 fJ @ 0.5 V 1.1 fJ @ 0.8 V Additional Needed Needed Needed Needed Needed Not Needed Control

    [0155] In addition, backup and restore control for distributed NV-DFFs can require additional wiring with more area and energy consumption. In addition, the processor architecture and the software needed to adapt to the control limits the compatibility of existing software and makes the operating system or processor design complicated. Furthermore, a backup triggered too early or too late will waste energy that could otherwise be saved, or result in a backup failure and rolling back in progress. These problems with conventional DFF devices are exacerbated due to the inherent nature of intermittency and unpredictability in ambient power sources.

    [0156] As will be explained in detail, embodiments of the latches 118, 122 and DFFs 120 disclosed herein can be configured to have only a few extra transistors added to a conventional CMOS design, leading to a compact cell design. No additional circuitry or a different supply voltage is needed for sensing or driving functions, as would otherwise be necessary for conventional DFFs. In addition, embodiments of the latches 118, 122 and DFFs 120 can be free from external backup and restore controls because all backup and restore operations are carried out autonomously. This can improve compatibility and reduce complexity of existing logic designs with drop-in replacement of latches and DFFs, as shown in FIG. 24. Obviating external controls can significantly reduce the control overhead for check-pointing and power-gating.

    [0157] Embodiments of the disclosed latches 118, 122 and DFFs 120 can be fast and energy-efficient, with similar delay and energy consumption to conventional volatile designs under a stable supply. Typical energy and latency for a backup plus restore operation are only at levels of fJ and ns, respectively. Note that the restore time also depends on the supply voltage recovery time. The operations could be even faster with kinetic coefficient improvement in the FeFET 102. With such a low energy and delay overhead, the utilization of harvested energy for the purpose of computing can be significantly improved. For the same reason, check-pointing and power-gating can be carried out in fine grain as needed with significantly reduced energy and delay penalties.

    [0158] Many ferroelectric materials, such as PbTiO, BaTiO, Pb(ZrTi)O, HfZrO, etc., can be used to generate an embodiment of the FeFET 102. FIGS. 25-27 illustrates a simplified concept for an embodiment of the FeFET 102 with the negative capacitor connected to the internal MOSFET gate capacitor. One interesting phenomenon that fits well with Boolean logic computation is the boosted voltage change V.sub.MOSFET at the internal MOSFET gate induced by an external FeFET gate voltage change V.sub.NCFET with |C.sub.FE|>C.sub.MOS, in which C.sub.FE and C.sub.MOS represent the ferroelectric negative capacitance and the MOSFET gate capacitance, respectively. The voltage gain at the internal MOSFET gate over the overall applied NCFET gate voltage could be approximated by G=V.sub.MOSFET/V.sub.NCFET=C.sub.FE/(C.sub.FE+C.sub.MOS)=|C.sub.FE|/(|C.sub.FE|C.sub.MOS)>1. This indicates a steep switching that enables a lower supply to achieve the same ON-OFF ratio, as shown in FIG. 27. Tuning C.sub.FE, so that |C.sub.FE|<C.sub.MOS within some voltage range, the hysteresis loop in the I.sub.DSV.sub.GS can be made to expand to the negative V.sub.GS range. (See FIG. 28). The mechanism behind this is the polarization P versus electric-field E hysteresis of the ferroelectric capacitor shown FIG. 28. The charge Q.sub.FE of the ferroelectric capacitor is a function of E and P in the way of Q.sub.FE=E+P, where is the permittivity of the vacuum, and P is typically >>E. The switching of P is electrically determined by E and a switching occurs when the applied voltage exceeds the coercive voltage. Before the polarization switching occurs, C.sub.FE is positive. As V.sub.NCFET increases from 0V to close to the IDSVGS rising edge, the voltage across the ferroelectric material V increases from the initial value of 0 to close to the coercive voltage. As V.sub.NCFET further increases, V.sub.FE steps beyond the coercive voltage, and C.sub.FE becomes negative, leading to the unstable negative total series capacitance of C.sub.FE and C.sub.MOS that triggers a very steep switching of I.sub.DS until C.sub.FE settles to be positive again. The outbound trip is similar. In both outbound and inbound curves away from the switching edges, a relatively flat I.sub.DSV.sub.GS may be observed if C.sub.FE (being positive in this region) is much smaller than C.sub.MOS, because V.sub.MOS=V.sub.NCFETC.sub.FE/(C.sub.FE+C.sub.MOS)0. Such a hysteresis feature covering V.sub.GS=0V indicates a stable remnant polarization when power is removed. Actually, a zero-polarization of the ferroelectric material is not stable as the free energy is not the lowest. It is also noted that the hysteresis width is a function of the dynamics of both C.sub.FE and C.sub.MOS, and could be typically tuned by varying the ferroelectric layer thickness, as observed in FIGS. 27 and 28.

    [0159] Referring to FIG. 29, in at least one embodiment, the latch can be configured as a latch 118, 120 that may be used to form an embodiment of a DFF 120. In one embodiment, the latch 118, 122 can be configured with a differential-driving input pair D/DN, as shown in FIG. 29. The latch 118, 122 can have a first transistor, M.sub.1. M.sub.1 can have an M.sub.1-source, an M.sub.1-gate, and an M.sub.1-drain. The latch 118, 122 can have a second transistor, M.sub.2. M.sub.2 can have an M.sub.2-source, an M.sub.2-gate, and an M.sub.2-drain. The latch 118, 122 can have a third transistor, M.sub.3. M.sub.3 can have an M.sub.3-source, an M.sub.3-gate, and an M.sub.3-drain. The latch 118, 122 can have a fourth transistor, M.sub.4. M.sub.4 can have an M.sub.4-source, an M.sub.4-gate, and an M.sub.4-drain. The slave latch 118 can have a fifth transistor, M.sub.5. M.sub.5 can have an M.sub.5-source, an M.sub.5-gate, and an M.sub.5-drain. The latch 118, 122 can have a sixth transistor, M.sub.6. M.sub.6 can have an M.sub.6-source, an M.sub.6-gate, and an M.sub.6-drain. The latch 118, 122 can have a seventh transistor, M.sub.7. M.sub.7 can have an M.sub.7-source, an M.sub.7-gate, and an M.sub.7-drain. The latch 118, 122 can have an eighth transistor, M.sub.8. M.sub.8 can have an M.sub.8-source, an M.sub.8-gate, and an M.sub.8-drain. Any one or combination of the transistors of the slave latch 118 can be a metal oxide semiconductor field effect transistor (MOSFET) or a FeFET 102.

    [0160] In at least one embodiment, M.sub.1, M.sub.2, M.sub.3, M.sub.4, M.sub.7, and M.sub.8 are MOSFETs. In at least one embodiment, M.sub.5 and M.sub.6 are FeFETs 102. M.sub.1-drain can be connected to M.sub.3-gate, M.sub.3-source, M.sub.4-source, M.sub.4-gate, data output Q, M.sub.2-drain, M.sub.5-gate, M.sub.7-gate, M.sub.5-drain, data output QN, M.sub.6-drain, M.sub.6-gate, and M.sub.8-gate. M.sub.1-gate can be connected to a clock driver CLK. M.sub.1-source can be connected to a data input D. M.sub.2-drain can be connected to M.sub.3-gate, M.sub.3-source, M.sub.4-source, M.sub.4-gate, data output Q, M.sub.1-drain, M.sub.5-gate, M.sub.7-gate, M.sub.5-drain, data output QN, M.sub.6-drain, M.sub.6-gate, and M.sub.8-gate. M.sub.2-gate can be connected to M.sub.1-gate. M.sub.2-source can be connected to a data input DN. M.sub.3-drain can be connected to a voltage supply V.sub.DD. M.sub.3-gate can be connected to M.sub.3-source, M.sub.4-source, M.sub.4-gate, data output Q, M.sub.1-drain, M.sub.2-drain, M.sub.5-gate, M.sub.7-gate, M.sub.5-drain, data output QN, M.sub.6-drain, M.sub.6-gate, and M.sub.8-gate. M.sub.3-source can be connected to M.sub.3-gate, M.sub.4-source, M.sub.4-gate, data output Q, M.sub.1-drain, M.sub.2-drain, M.sub.5-gate, M.sub.7-gate, M.sub.5-drain, data output QN, M.sub.6-drain, M.sub.6-gate, and M.sub.8-gate. M.sub.4-drain can be connected to V.sub.DD. M.sub.4-gate can be connected to M.sub.3-source, M.sub.4-source, M.sub.3-gate, data output Q, M.sub.1-drain, M.sub.2-drain, M.sub.5-gate, M.sub.7-gate, M.sub.5-drain, data output QN, M.sub.6-drain, M.sub.6-gate, and M.sub.8-gate. M.sub.4-source can be connected to M.sub.3-source, M.sub.4-gate, M.sub.3-gate, data output Q, M.sub.1-drain, M.sub.2-drain, M.sub.5-gate, M.sub.7-gate, M.sub.5-drain, data output QN, M.sub.6-drain, M.sub.6-gate, and M.sub.8-gate. M.sub.5-drain can be connected to M.sub.4-source, M.sub.3-source, M.sub.4-gate, M.sub.3-gate, data output Q, M.sub.1-drain, M.sub.2-drain, M.sub.5-gate, M.sub.7-gate, M.sub.5-drain, data output QN, M.sub.6-drain, M.sub.6-gate, and M.sub.8-gate. M.sub.5-gate can be connected to M.sub.4-source, M.sub.3-source, M.sub.4-gate, M.sub.3-gate, data output Q, M.sub.1-drain, M.sub.2-drain, M.sub.5-drain, M.sub.7-gate, M.sub.5-drain, data output QN, M.sub.6-drain, M.sub.6-gate, and M.sub.8-gate. M.sub.5-source can be connected to M.sub.7-drain. M.sub.6-drain can be connected to M.sub.4-source, M.sub.3-source, M.sub.4-gate, M.sub.3-gate, data output Q, M.sub.1-drain, M.sub.2-drain, M.sub.5-gate, M.sub.7-gate, M.sub.5-drain, data output QN, M.sub.5-drain, M.sub.6-gate, and M.sub.8-gate. M.sub.6-gate can be connected to M.sub.4-source, M.sub.3-source, M.sub.4-gate, M.sub.3-gate, data output Q, M.sub.1-drain, M.sub.2-drain, M.sub.5-gate, M.sub.7-gate, M.sub.5-drain, data output QN, M.sub.5-drain, M.sub.6-drain, and M.sub.8-gate. M.sub.6-source can be connected to M.sub.8-drain. M.sub.7-drain can be connected to M.sub.5-source. M.sub.7-gate can be connected to M.sub.6-gate, M.sub.4-source, M.sub.3-source, M.sub.4-gate, M.sub.3-gate, data output Q, M.sub.1-drain, M.sub.2-drain, M.sub.5-gate, M.sub.5-drain, data output QN, M.sub.5-drain, M.sub.6-drain, and M.sub.8-gate. M.sub.7-source can be connected to GND. M.sub.8-drain can be connected to M.sub.6-source. M.sub.8-gate can be connected to M.sub.7-gate, M.sub.6-gate, M.sub.4-source, M.sub.3-source, M.sub.4-gate, M.sub.3-gate, data output Q, M.sub.1-drain, M.sub.2-drain, M.sub.5-gate, M.sub.5-drain, data output QN, M.sub.5-drain, and M.sub.6-drain. M.sub.8-source can be connected to GND.

    [0161] Referring to FIG. 30, in at least one embodiment, the latch 118, 122 can be configured as a latch 118, 122 that may be used to form an embodiment of a DFF 120. The latch 118, 122 can be configured with an input D, as shown in FIG. 30. With the topology of FIG. 30, M.sub.7 and M.sub.8 can have a lower V.sub.TH for higher yield. The latch 118, 122 can have a first transistor, M.sub.1. M.sub.1 can have an M.sub.1-source, an M.sub.1-gate, and an M.sub.1-drain. The latch 118, 122 can have a second transistor, M.sub.2. M.sub.2 can have an M.sub.2-source, an M.sub.2-gate, and an M.sub.2-drain. The latch 118, 122 can have a third transistor, M.sub.3. M.sub.3 can have an M.sub.3-source, an M.sub.3-gate, and an M.sub.3-drain. The latch 118, 122 can have a fourth transistor, M.sub.4. M.sub.4 can have an M.sub.4-source, an M.sub.4-gate, and an M.sub.4-drain. The latch 118, 122 can have a fifth transistor, M.sub.5. M.sub.5 can have an M.sub.5-source, an M.sub.5-gate, and an M.sub.5-drain. The latch 118, 122 can have a sixth transistor, M.sub.6. M.sub.6 can have an M.sub.6-source, an M.sub.6-gate, and an M.sub.6-drain. The latch 118, 122 can have a seventh transistor, M.sub.7. M.sub.7 can have an M.sub.7-source, an M.sub.7-gate, and an M.sub.7-drain. The latch 118, 122 can have an eighth transistor, M.sub.8. M.sub.8 can have an M.sub.8-source, an M.sub.8-gate, and an M.sub.8-drain. The latch 118, 122 can have a ninth transistor, M.sub.9. M.sub.9 can have an M.sub.9-source, an M.sub.9-gate, and an M.sub.9-drain. The latch 118, 120 can have a tenth transistor, M.sub.10. M.sub.10 can have an M.sub.10-source, an M.sub.10-gate, and an M.sub.10-drain. The latch 118, 122 can have an eleventh transistor, M.sub.11. M.sub.11 can have an M.sub.11-source, an M.sub.11-gate, and an M.sub.11-drain. The latch 118, 122 can have a twelfth transistor, M.sub.12. M.sub.12 can have an M.sub.12-source, an M.sub.12-gate, and an M.sub.12-drain. The latch 118, 122 can have a thirteenth transistor, M.sub.5b. M.sub.5b can have an M.sub.5b-source, an M.sub.5b-gate, and an M.sub.5b-drain. The latch 118, 122 can have a fourteenth transistor, M.sub.6b. M.sub.6b can have an M.sub.th-source, an M.sub.6b-gate, and an M.sub.6b-drain. Any one or combination of the transistors of the slave latch 118 can be a metal oxide semiconductor field effect transistor (MOSFET) or a FeFET 102.

    [0162] In at least one embodiment, M.sub.1, M.sub.2, M.sub.3, M.sub.4, M.sub.7, M.sub.8, M.sub.9, M.sub.10, and M.sub.11 are MOSFETs. In at least one embodiment, M.sub.5 and M.sub.6 are FeFETs 102. M.sub.1-drain can be connected to M.sub.2-drain and data input D. M.sub.1-gate can be connected to a clock driver CLK. M.sub.1-source can be connected to M.sub.2-source, M.sub.3-gate, M.sub.5-gate, M.sub.7-gate, M.sub.11-source, M.sub.12-source, M.sub.3-source, M.sub.9-source, M.sub.10-source, M.sub.5-drain, and M.sub.5b-drain. M.sub.2-drain can be connected to M.sub.1-drain and data input D. M.sub.2-gate can be connected to CLK. M.sub.2-source can be connected to M.sub.1-source, M.sub.3-gate, M.sub.5-gate, M.sub.7-gate, M.sub.11-source, M.sub.12-source, M.sub.3-source, M.sub.9-source, M.sub.10-source, M.sub.5-drain, and M.sub.5b-drain. M.sub.3-drain can be connected to V.sub.DD. M.sub.3-gate can be connected to M.sub.1-source, M.sub.2-source, M.sub.5-gate, M.sub.7-gate, M.sub.11-source, M.sub.12-source, M.sub.3-source, M.sub.9-source, M.sub.10-source, M.sub.5-drain, and M.sub.5b-drain. M3-source can be connected to M.sub.1-source, M.sub.2-source, M.sub.5-gate, M.sub.7-gate, M.sub.11-source, M.sub.12-source, M.sub.3-gate, M.sub.9-source, M.sub.10-source, M.sub.5-drain, and M.sub.5b-drain. M.sub.4-drain can be connected to V.sub.DD. M.sub.4-gate can be connected to data output QN, data output Q, M.sub.6-gate, M.sub.8-gate, M.sub.4-source, M.sub.9-drain, M.sub.10-drain, M.sub.11-drain, M.sub.12-drain, M.sub.6b-drain, and M.sub.6-drain. M.sub.4-source can be connected to data output QN, data output Q, M.sub.6-gate, M.sub.8-gate, M.sub.4-gate, M.sub.9-drain, M.sub.10-drain, M.sub.11-drain, M.sub.12-drain, M.sub.6b-drain, and M.sub.6-drain. M.sub.5-drain can be connected to M.sub.1-source, M.sub.2-source, M.sub.5-gate, M.sub.7-gate, M.sub.11-source, M.sub.12-source, M.sub.3-source, M.sub.9-source, M.sub.10-source, and M.sub.5b-drain. M5-gate can be connected to M.sub.1-source, M.sub.2-source, M.sub.5-drain, M.sub.7-gate, M.sub.11-source, M.sub.12-source, M.sub.3-source, M.sub.9-source, M.sub.10-source, M.sub.5b-gate, and M.sub.5b-drain. M.sub.5-source can be connected to M.sub.7-drain. M.sub.5b-drain can be connected to M.sub.1-source, M.sub.2-source, M.sub.5-gate, M.sub.7-gate, M.sub.11-source, M.sub.12-source, M.sub.3-source, M.sub.9-source, M.sub.10-source, and M.sub.5-drain. M.sub.5b-gate can be connected to M.sub.5-gate. M.sub.5b-source can be connected to GND. M.sub.6-drain can be connected to data output QN, data output Q, M.sub.6-gate, M.sub.8-gate, M.sub.4-source, M.sub.9-drain, M.sub.10-drain, M.sub.11-drain, M.sub.12-drain, M.sub.6b-drain, and M.sub.4-gate. M.sub.6-gate can be connected to data output QN, data output Q, M.sub.6-drain, M.sub.6b-gate, M.sub.8-gate, M.sub.4-source, M.sub.9-drain, M.sub.10-drain, M.sub.11-drain, M.sub.12-drain, M.sub.6b-drain, and M.sub.4-gate. M.sub.6-source can be connected to M.sub.8-drain. M.sub.6b-drain can be connected to data output QN, data output Q, M.sub.6-gate, M.sub.8-gate, M.sub.4-source, M.sub.9-drain, M.sub.10-drain, M.sub.11-drain, M.sub.12-drain, M.sub.4-gate, and M.sub.6-drain. M.sub.6b-gate can be connected to M.sub.6-gate. M.sub.6b-source can be connected to GND. M.sub.7-drain can be connected to M.sub.5-source. M.sub.7-gate can be connected to M.sub.1-source, M.sub.2-source, M.sub.5-gate, M.sub.5-drain, M.sub.11-source, M.sub.12-source, M.sub.3-source, M.sub.9-source, M.sub.10-source, and M.sub.5b-drain. M.sub.7-source can be connected to GND. M.sub.8-drain can be connected to M.sub.6-source. M.sub.8-gate can be connected to data output QN, data output Q, M.sub.6-gate, M.sub.4-gate, M.sub.4-source, M.sub.9-drain, M.sub.10-drain, M.sub.11-drain, M.sub.12-drain, M.sub.6b-drain, and M.sub.6-drain. M.sub.8-source can be connected to GND. M.sub.9-drain can be connected to data output QN, data output Q, M.sub.6-gate, M.sub.8-gate, M.sub.4-source, M.sub.4-gate, M.sub.10-drain, M.sub.11-drain, M.sub.12-drain, M.sub.6b-drain, and M.sub.6-drain. M.sub.9-gate can be connected to V.sub.DD. M.sub.9-source can be connected to M.sub.1-source, M.sub.2-source, M.sub.5-gate, M.sub.7-gate, M.sub.11-source, M.sub.12-source, M.sub.3-source, M.sub.5-drain, M.sub.10-source, and M.sub.5b-drain. M.sub.10-drain can be connected to data output QN, data output Q, M.sub.6-gate, M.sub.8-gate, M.sub.4-source, M.sub.9-drain, M.sub.4-gate, M.sub.11-drain, M.sub.12-drain, M.sub.6b-drain, and M.sub.6-drain. M.sub.10-gate can be connected to GND. M.sub.10-source can be connected to M.sub.1-source, M.sub.2-source, M.sub.5-gate, M.sub.7-gate, M.sub.11-source, M.sub.12-source, M.sub.3-source, M.sub.9-source, M.sub.5-drain, and M.sub.5b-drain. M.sub.11-drain can be connected to data output QN, data output Q, M.sub.6-gate, M.sub.8-gate, M.sub.4-source, M.sub.9-drain, M.sub.10-drain, M.sub.4-gate, M.sub.12-drain, M.sub.6b-drain, and M.sub.6-drain. M.sub.11-gate can be connected to CLK. M.sub.11-source can be connected to M.sub.1-source, M.sub.2-source, M.sub.5-gate, M.sub.7-gate, M.sub.5-drain, M.sub.12-source, M.sub.3-source, M.sub.9-source, M.sub.10-source, and M.sub.5b-drain. M.sub.12-drain can be connected to data output QN, data output Q, M.sub.6-gate, M.sub.8-gate, M.sub.4-source, M.sub.9-drain, M.sub.10-drain, M.sub.11-drain, M.sub.4-gate, M.sub.6b-drain, and M.sub.6-drain. M.sub.12-gate can be connected to CLK. M.sub.12-source can be connected to M.sub.1-source, M.sub.2-source, M.sub.5-gate, M.sub.7-gate, M.sub.11-source, M.sub.5-drain, M.sub.3-source, M.sub.9-source, M.sub.10-source, and M.sub.5b-drain.

    [0163] FIG. 31 is a conventional CMOS volatile latch that was used as a baseline to compare to the latch topology of FIG. 29. FIG. 32 is a conventional CMOS volatile latch that was used as a baseline to compare to the latch topology of FIG. 30. As will be explained herein, the conventional volatile latches behave differently in area, energy per switching, delay, etc. When the power supply is steady, the logical transfer function for each of them is the same, as shown in Table 3. The latch 118, 122 of FIG. 29 has two extra N-type FeFETs over the CMOS counterpart design. Both latches are designed with sufficient input driving strength so as to overwrite the state by the input pair D/DN directly, when the clock signal CLK is high. When CLK is high, it connects the input differential signals D and DN to the output ports of Q and QN, respectively.

    TABLE-US-00003 TABLE 3 Function Table for Latch Topologies of FIGS. 29-32 Scenarios Operations VDD = 1; CLK = 1 Q follows D VDD = 1; CLK = 0 Q holds VDD = 0 Q = 0 VDD = 0.fwdarw.1; CLK = 0 Q restores to stored state (NV-Latch)

    [0164] FIG. 33 shows an exemplary steady state operation of the latch topology of FIG. 29 with CLK being high, using Q as logically 1 (representing V.sub.DD in voltage) and QN as logically 0 (representing GND in voltage). Controlled by Q or QN, M.sub.3 and Mg are turned OFF, and M.sub.4 and M.sub.7 are turned ON. For M.sub.5, its gate voltage is high, and the drain connecting to QN is low, its source is discharged to GND by M.sub.7. As a result, M.sub.5 is turned ON and stays at the positive polarization state with low drain-source resistance. For M.sub.6, it stays OFF at the negative polarization state with high drain-source resistance. It is noted that, a low voltage of GND at QN will turn OFF M.sub.8, and set M.sub.6 as negatively polarized (high drain-source resistance): if M.sub.6 was at a previous positive polarization (low drain-source resistance) state, M.sub.6 source would be charged to Q, which is V.sub.DD, by M.sub.6. As a result, the drain-source voltage of M.sub.6 becomes V.sub.DD. After that, M.sub.6 will remain negative in its polarization even if its source node is slowly discharged by M.sub.8.

    [0165] FIG. 35 shows the transient waveforms for an embodiment of a latch topology shown in FIG. 29 for sample and hold operations with a steady supply. The last P plot indicates polarization of the M.sub.5 and M.sub.6. At time t1 around 61 ns, when the input D is steadily 1, the rising CLK turns ON the switches and the latch output Q switches from the previous state of 0 to follow the input D with 1, along with the observable polarization switching of M.sub.5 and M.sub.6. At time t2 around 62 ns, the clock CLK turns to 0 and the latch holds the state even if D changes. At time t3 around 62.5 ns, the polarization switching is accomplished and stays stable until the latch samples the next different input state.

    [0166] In FIG. 35, all polarization switching could successfully finish before the next switching due to sufficient time window before the next switching event. In FIG. 36, with the given input pattern of D and CLK, the duration of the total time of Q to stay at the new state (i.e., 1 from 60 ns to 67 ns) is too short for the polarization switching to finish. FIG. 36 shows the polarization switching progress for an embodiment of the latch with a higher data-rate. The last P plot indicates polarization of M.sub.5 M6 for an embodiment of a latch topology shown in FIG. 29. As can be seen from FIG. 36, none of them in this 7 ns period of time succeeds in switching the polarization state, until after 67 ns when Q stays at 1 for more than 0.5 nS. Such a phenomenon of a polarization switching speed being lower than the input data rate actually reveals the possibility of having a pseudo-floating 0 of Q at the latch output, with high resistance to V.sub.DD (with turned-OFF PMOS) and also medium-to-high resistance to GND (due to partially turned-OFF FeFET in series with a turned-on NMOS). Note that a pseud-floating 1 does not exist because a Q output of 1 is always securely connected to V.sub.DD by the PMOS.

    [0167] The pseudo-floating 0 has three major effects. First, functionality will stay correct with proper noise shielding. This is because a short period of ns in time of being pseudo-floating will not have the state corrupted if external coupling noise is properly isolated. For example, most standard embedded dynamic random access memory (DRAM) cells have a retention time of a few microseconds at the internal floating MOSFET gate. After the polarization switching finishes in the order of ns or sub-ns, this pseudo-floating 0 becomes a steady 0 connecting to GND. Second, endurance will improve. Although existing research has not yet found out a fundamental bottleneck in improving the endurance or aging effects of ferroelectric materials, existing ferroelectric materials degrade faster in terms of number of full-swing switching cycles than CMOS transistors. The way above of slower polarization switching helps to reduce the number of full-swing switching activities, which improves the endurance of FeFETs. Third, delay and energy performance may also improve. First, considering the conventional volatile CMOS latch in FIG. 31, in order to overwrite the previous 0 state of Q to be 1, the new input datum of 1 has to fight with the pulling down transistor in the latch. Such a racing condition causes significant power consumption until the switching completes. On the contrary, with the latch topology of FIG. 29, considering the pseudo-floating 0 Q due to the higher resistance from Q to GND through the not-fully-ON FeFET, overwriting this 0 to be 1 has less short current or racing conditions, which improves the speed and energy performance. It is also noted that, using a high threshold NMOS transistor could also mitigate the racing fight but could not provide equally low pull-down resistance after the polarization switching finishes.

    [0168] FIG. 37 shows the transient waveforms with backup and restore operations due to power failures for the latch topology of FIG. 29. At around 180 nS and 2,175 ns, backup of 0 and 1 is carried out, respectively; at around 2,100 ns and 4,080 ns, restore of 0 and 1 is observed, respectively. The simulation is accompanied with close to a 2 ns power-down window to mimic really field scenarios.

    [0169] The latch topology shown in FIG. 29 utilizes N-type FeFETs 102. It is contemplated to use P-type FeFETs 102 (see FIG. 38), or both N-type FeFETs 102 and P-type FeFETs 102 (see FIG. 39). The operations of such latch topologies would be similar.

    [0170] Referring to FIG. 38, the latch 118, 122 can have a first transistor, M.sub.1. M.sub.1 can have an M.sub.1-source, an M.sub.1-gate, and an M.sub.1-drain. The latch 118, 122 can have a second transistor, M.sub.2. M.sub.2 can have an M.sub.2-source, an M.sub.2-gate, and an M.sub.2-drain. The latch 118, 122 can have a third transistor, M.sub.3. M.sub.3 can have an M.sub.3-source, an M.sub.3-gate, and an M.sub.3-drain. The latch 118, 122 can have a fourth transistor, M.sub.4. M.sub.4 can have an M.sub.4-source, an M.sub.4-gate, and an M.sub.4-drain. The latch 118, 122 can have a fifth transistor, M.sub.5. M.sub.5 can have an M.sub.5-source, an M.sub.5-gate, and an M.sub.5-drain. The latch 118, 122 can have a sixth transistor, M.sub.6. M.sub.6 can have an M.sub.6-source, an M.sub.6-gate, and an M.sub.6-drain. The latch 118, 122 can have a seventh transistor, M.sub.7. M.sub.7 can have an M.sub.7-source, an M.sub.7-gate, and an M.sub.7-drain. The latch 118, 122 can have an eighth transistor, M.sub.8. M.sub.8 can have an M.sub.8-source, an M.sub.8-gate, and an M.sub.8-drain. Any one or combination of the transistors of the slave latch 118 can be a metal oxide semiconductor field effect transistor (MOSFET) or a FeFET 102.

    [0171] In at least one embodiment, M.sub.1, M.sub.2, M.sub.3, M.sub.4, M.sub.7, and M.sub.8 are MOSFETs. In at least one embodiment, M.sub.5 and M.sub.6 are FeFETs 102. M1-drain can be connected to data input D. M.sub.1-gate can be connected to CLK. M.sub.1-source can be connected to M.sub.5-gate, M.sub.3-gate, M.sub.5-source, M.sub.2-source, M.sub.7-gate, M.sub.7-drain, data output Q, data output QN, M.sub.6-source, M.sub.8-drain, M.sub.8-gate, M.sub.6-gate, and M.sub.4-gate. M.sub.2-drain can be connected to data input DN. M.sub.2-gate can be connected to M.sub.1-gate. M.sub.2-source can be connected to M.sub.5-gate, M.sub.3-gate, M.sub.5-source, M.sub.1-source, M.sub.7-gate, M.sub.7-drain, data output Q, data output QN, M.sub.6-source, M.sub.8-drain, M.sub.8-gate, M.sub.6-gate, and M.sub.4-gate. M.sub.3-drain can be connected to V.sub.DD. M.sub.3-gate can be connected to M.sub.5-gate, M.sub.1-source, M.sub.5-source, M.sub.2-source, M.sub.7-gate, M.sub.7-drain, data output Q, data output QN, M.sub.6-source, M.sub.8-drain, M.sub.8-gate, M.sub.6-gate, and M.sub.4-gate. M.sub.3-source can be connected to M.sub.5-drain. M.sub.4-drain can be connected to V.sub.DD. M.sub.4-gate can be connected to M.sub.5-gate, M.sub.3-gate, M.sub.5-source, M.sub.2-source, M.sub.7-gate, M.sub.7-drain, data output Q, data output QN, M.sub.6-source, M.sub.8-drain, M.sub.8-gate, M.sub.6-gate, and M.sub.1-source. M.sub.4-source can be connected to M.sub.6-drain. M.sub.5-drain can be connected to M.sub.3-source. M5-gate can be connected to M.sub.1-source, M.sub.3-gate, M.sub.5-source, M.sub.2-source, M.sub.7-gate, M.sub.7-drain, data output Q, data output QN, M.sub.6-source, M.sub.8-drain, M.sub.8-gate, M.sub.6-gate, and M.sub.4-gate. M.sub.5-source can be connected to M.sub.5-gate, M.sub.3-gate, M.sub.1-source, M.sub.2-source, M.sub.7-gate, M.sub.7-drain, data output Q, data output QN, M.sub.6-source, M.sub.8-drain, M.sub.8-gate, M.sub.6-gate, and M.sub.4-gate. M.sub.6-drain can be connected to M.sub.4-source. M.sub.6-gate can be connected to M.sub.5-gate, M.sub.3-gate, M.sub.5-source, M.sub.2-source, M.sub.7-gate, M.sub.7-drain, data output Q, data output QN, M.sub.6-source, M.sub.8-drain, M.sub.8-gate, M.sub.1-source, and M.sub.4-gate. M.sub.6-source can be connected to M.sub.5-gate, M.sub.3-gate, M.sub.5-source, M.sub.2-source, M.sub.7-gate, M.sub.7-drain, data output Q, data output QN, M.sub.1-source, M.sub.8-drain, M.sub.8-gate, M.sub.6-gate, and M.sub.4-gate. M.sub.7-drain can be connected to M.sub.5-gate, M.sub.3-gate, M.sub.5-source, M.sub.2-source, M.sub.7-gate, M.sub.1-source, data output Q, data output QN, M.sub.6-source, M.sub.8-drain, M.sub.8-gate, M.sub.6-gate, and M.sub.4-gate. M.sub.7-gate can be connected to M.sub.5-gate, M.sub.3-gate, M.sub.5-source, M.sub.2-source, M.sub.1-source, M.sub.7-drain, data output Q, data output QN, M.sub.6-source, M.sub.8-drain, M.sub.8-gate, M.sub.6-gate, and M.sub.4-gate. M.sub.7-source can be connected to GND. M.sub.8-drain can be connected to M.sub.5-gate, M.sub.3-gate, M.sub.5-source, M.sub.2-source, M.sub.7-gate, M.sub.7-drain, data output Q, data output QN, M.sub.6-source, M.sub.1-source, M.sub.8-gate, M.sub.6-gate, and M.sub.4-gate. M.sub.8-gate can be connected to M.sub.5-gate, M.sub.3-gate, M.sub.5-source, M.sub.2-source, M.sub.7-gate, M.sub.7-drain, data output Q, data output QN, M.sub.6-source, M.sub.8-drain, M.sub.1-source, M.sub.6-gate, and M.sub.4-gate. M.sub.8-source can be connected to GND.

    [0172] Referring to FIG. 39, the latch 118, 122 can have a first transistor, M.sub.1. M.sub.1 can have an M.sub.1-source, an M.sub.1-gate, and an M.sub.1-drain. The latch 118, 122 can have a second transistor, M.sub.2. M.sub.2 can have an M.sub.2-source, an M.sub.2-gate, and an M.sub.2-drain. The latch 118, 122 can have a third transistor, M.sub.3. M.sub.3 can have an M.sub.3-source, an M.sub.3-gate, and an M.sub.3-drain. The latch 118, 122 can have a fourth transistor, M.sub.4. M.sub.4 can have an M.sub.4-source, an M.sub.4-gate, and an M.sub.4-drain. The latch 118, 122 can have a fifth transistor, M.sub.5. M.sub.5 can have an M.sub.5-source, an M.sub.5-gate, and an M.sub.5-drain. The latch 118, 122 can have a sixth transistor, M.sub.6. M.sub.6 can have an M.sub.6-source, an M.sub.6-gate, and an M.sub.6-drain. The latch 118, 122 can have a seventh transistor, M.sub.7. M.sub.7 can have an M.sub.7-source, an M.sub.7-gate, and an M.sub.7-drain. The latch 118, 122 can have an eighth transistor, M.sub.8. M.sub.8 can have an M.sub.8-source, an M.sub.8-gate, and an M.sub.8-drain. The latch 118, 122 can have a ninth transistor, M.sub.9. M.sub.9 can have an M.sub.9-source, an M.sub.9-gate, and an M.sub.9-drain. The latch 118, 122 can have a tenth transistor, M.sub.10. M.sub.10 can have an M.sub.10-source, an M.sub.10-gate, and an M.sub.10-drain. Any one or combination of the transistors of the slave latch 118 can be a metal oxide semiconductor field effect transistor (MOSFET) or a FeFET 102.

    [0173] In at least one embodiment, M.sub.1, M.sub.2, M.sub.3, M.sub.4, M.sub.9, and M.sub.10 are MOSFETs. In at least one embodiment, M.sub.5, M.sub.6, M.sub.7, and M.sub.8 are FeFETs 102. M.sub.1-drain can be connected to data input D. M.sub.1-gate can be connected to CLK. M.sub.1-source can be connected to M.sub.5-gate, M.sub.3-gate, M.sub.2-source, M.sub.7-gate, M.sub.9-gate, M.sub.5-source, M.sub.6-source, data output Q, M.sub.6-gate, M.sub.4-gate, M.sub.7-drain, M.sub.8-drain, data output QN, M.sub.8-gate, and M.sub.10-gate. M.sub.2-drain can be connected to data input DN. M.sub.2-gate can be connected to M.sub.1-gate. M.sub.2-source can be connected to M.sub.5-gate, M.sub.3-gate, M.sub.1-source, M.sub.7-gate, M.sub.9-gate, M.sub.5-source, M.sub.6-source, data output Q, M.sub.6-gate, M.sub.4-gate, M.sub.7-drain, M.sub.8-drain, data output QN, M.sub.8-gate, and M.sub.10-gate. M.sub.3-drain can be connected to V.sub.DD. M.sub.3-gate can be connected to M.sub.5-gate, M.sub.1-source, M.sub.2-source, M.sub.7-gate, M.sub.9-gate, M.sub.5-source, M.sub.6-source, data output Q, M.sub.6-gate, M.sub.4-gate, M.sub.7-drain, M.sub.8-drain, data output QN, M.sub.8-gate, and M.sub.10-gate. M.sub.3-source can be connected to M.sub.5-drain. M.sub.4-drain can be connected to V.sub.DD. M.sub.4-gate can be connected to M.sub.5-gate, M.sub.3-gate, M.sub.2-source, M.sub.7-gate, M.sub.9-gate, M.sub.5-source, M.sub.6-source, data output Q, M.sub.6-gate, M.sub.1-source, M.sub.7-drain, M.sub.8-drain, data output QN, M.sub.8-gate, and M.sub.10-gate. M.sub.4-source can be connected to M.sub.6-drain. M.sub.5-drain can be connected to M.sub.3-source. M.sub.5-gate can be connected to M.sub.1-source, M.sub.3-gate, M.sub.2-source, M.sub.7-gate, M.sub.9-gate, M.sub.5-source, M.sub.6-source, data output Q, M.sub.6-gate, M.sub.4-gate, M.sub.7-drain, M.sub.8-drain, data output QN, M.sub.8-gate, and M.sub.10-gate. M.sub.5-source can be connected to M.sub.5-gate, M.sub.3-gate, M.sub.2-source, M.sub.7-gate, M.sub.9-gate, M.sub.1-source, M.sub.6-source, data output Q, M.sub.6-gate, M.sub.4-gate, M.sub.7-drain, M.sub.8-drain, data output QN, M.sub.8-gate, and M.sub.10-gate. M.sub.6-drain can be connected to M.sub.4-source. M.sub.6-gate can be connected to M.sub.5-gate, M.sub.3-gate, M.sub.2-source, M.sub.7-gate, M.sub.9-gate, M.sub.5-source, M.sub.6-source, data output Q, M.sub.1-source, M.sub.4-gate, M.sub.7-drain, M.sub.8-drain, data output QN, M.sub.8-gate, and M.sub.10-gate. M.sub.6-source can be connected to M.sub.5-gate, M.sub.3-gate, M.sub.2-source, M.sub.7-gate, M.sub.9-gate, M.sub.5-source, M.sub.1-source, data output Q, M.sub.6-gate, M.sub.4-gate, M.sub.7-drain, M.sub.8-drain, data output QN, M.sub.8-gate, and M.sub.10-gate. M.sub.7-drain can be connected to M.sub.5-gate, M.sub.3-gate, M.sub.2-source, M.sub.7-gate, M.sub.9-gate, M.sub.5-source, M.sub.6-source, data output Q, M.sub.6-gate, M.sub.4-gate, M.sub.1-source, M.sub.8-drain, data output QN, M.sub.8-gate, and M.sub.10-gate. M.sub.7-gate can be connected to M.sub.5-gate, M.sub.3-gate, M.sub.2-source, M.sub.1-source, M.sub.9-gate, M.sub.5-source, M.sub.6-source, data output Q, M.sub.6-gate, M.sub.4-gate, M.sub.7-drain, M.sub.8-drain, data output QN, M.sub.8-gate, and M.sub.10-gate. M.sub.7-source can be connected to M.sub.9-drain. M.sub.10-drain can be connected to M.sub.8-source. M.sub.10-gate can be connected to M.sub.5-gate, M.sub.3-gate, M.sub.2-source, M.sub.7-gate, M.sub.9-gate, M.sub.5-source, M.sub.6-source, data output Q, M.sub.6-gate, M.sub.4-gate, M.sub.7-drain, M.sub.8-drain, data output QN, M.sub.8-gate, and M.sub.1-source. M.sub.10-source can be connected to GND.

    [0174] In terms of the physical layout design, the overhead of the FeFETs 102 in embodiments of the latches of FIGS. 29, 30, 38, and 39 can be mitigated by properly sharing the drain and source active region without the need for adding additional contacts for the drain and source terminals of the FeFETs 102.

    [0175] FIG. 40 illustrates the operating mechanism of the latch topology of FIG. 30 during sampling, showing charging and discharging routes. FIG. 41 illustrates the operating mechanism of the latch topology of FIG. 30 in a hold phase, showing charging and discharging routes. FIGS. 40-41 illustrate the operation theory of an embodiment of the latch topology of FIG. 30. During the sampling phase (high CLK), M.sub.3 and M.sub.5b form an inverter that can provide a fast settling output of QN and no pseudo-floating status. The always-on CMOS switch consisting of M.sub.9 and M.sub.10 delivers QN to drive the second inverter to provide Q. The feedback loop of the switch is turned OFF to prevent racing short current during this sampling phase, and will be turned on to form a stable closed loop during the hold phase (low CLK), as shown in FIG. 41. The restore operation is similar to the latch topology of FIG. 29, by sensing a different Q or QN to ground resistance and continuing to settle down to V.sub.DD or GND in the feedback loop.

    [0176] FIG. 42 shows the transient simulation waveforms of the latch topology of FIG. 30. Along with the normal sampling and hold operations with a stable V.sub.DD, it also shows successful backup and restore operations of Q=0 and Q=1 during the power outages around 5 s and 10 s, respectively.

    [0177] FIGS. 43-44 summarize the simulated energy vs CLK-to-Q delay performance of embodiments of the latch with 1 and 4 driving capabilities at different supply voltages, in comparison with the conventional CMOS volatile latches. Simulations were carried out with 1.0 fF capacitor load, and an input rise and fall time of 20 ps for the input clock, D, and DN. Energy consumption included clocking and D/DN driving. While being aware that embodiments of the latches could operate at higher frequencies, in this section of evaluation, all polarization switching was fully completed, and the energy in FIGS. 43-44 includes the energy for Q/QN setup and also polarization switching as a backup operation. As the supply voltage reduces, simulation results summarized in FIGS. 43-44 show that the energy per switching reduces and the delay increases. Embodiments of the latches have about 64% and 39% extra energy-delay product (EDP) over the CMOS latch. If there is no need for a complete polarization switching (in cases with a high data rate), it consumes less energy for each switching event.

    [0178] FIGS. 45-48 show the energy and time for backup and restore operations for embodiments of the latch. As supply voltage increases, backup and restore time decreases, and backup and restore energy increases. Being an intrinsic nonvolatile latch, simulation results in FIGS. 45-48 also show that the latches are very fast and energy-efficient for backup and restore operations. For example, under 0.8V V.sub.DD, the backup time is lower than 1.0 ns, and the intrinsic restore time is lower than 75 ns for both each embodiment of the latch. It is noted that the intrinsic restore time is obtained with an assumption of very fast supply voltage recovery in a few ps. In real scenarios the supply voltage recovers slower (usually much larger than ns) and the capability of fast intrinsic restore operation guarantees that the overall restore operation closely follow the supply recovery. The restore energy is obtained based on 0.8 s supply voltage ramp-up time to mimic real scenarios. Meanwhile, the backup and restore energy is lower than 3.0 fJ for the entire operating range of 0.5V to 1.0V. This can enable extremely low-energy backup and restore operations of the entire processor being carried out autonomously and in parallel without worrying about the peak current.

    [0179] In some embodiments an improved DFF 120 can be generated by replacing any one or combination of its master latch and slave latch with an embodiment of the latch 118, 122 disclosed herein. FIG. 49 shows an embodiment of a DFF 120 with its slave latch 118 replaced with an embodiment of the latch topology of FIG. 29. The same topology of the latch in FIG. 29 can be used but with a first slave transmission gate, S.sub.GATE1, in place of M.sub.1 and a second transmission gate, S.sub.GATE2, in place of M.sub.2. For example, the output of S.sub.GATE1 can be connected to M.sub.3-gate, M.sub.3-source, M.sub.4-source, M.sub.4-gate, data output Q, S.sub.GATE2 output, M.sub.5-gate, M.sub.7-gate, M.sub.5-drain, data output QN, M.sub.6-drain, M.sub.6-gate, and M.sub.8-gate. The output of S.sub.GATE2 can be connected to M.sub.3-gate, M.sub.3-source, M.sub.4-source, M.sub.4-gate, data output Q, S.sub.GATE1 output, M.sub.5-gate, M.sub.7-gate, M.sub.5-drain, data output QN, M.sub.6-drain, M.sub.6-gate, and M.sub.8-gate.

    [0180] The master latch 122 can be connected to the slave latch 118 via S.sub.GATE1 and S.sub.GATE2. For example, the master latch 122 can have a first master transmission gate M.sub.GATE1, a first master inverter, M.sub.INV1, a second master inverter, M.sub.INV2, and a second master transmission gate, M.sub.GATE2. The input of M.sub.GATE1 can be connected to a data input signal, D. The output of M.sub.GATE1 can be connected to the input of M.sub.INV1 and the input of S.sub.GATE1. The input of M.sub.INV1 can be connected to the output of M.sub.GATE1. The output of M.sub.INV1 can be connected to the input of M.sub.INV2 and the input of S.sub.GATE2. The input of M.sub.INV2 can be connected to the output of M.sub.INV1. The output of M.sub.INV2 can be connected to the input of M.sub.GATE2. The input of M.sub.GATE2 can be connected to the output of M.sub.INV2. The output of M.sub.GATE2 can be connected to the input of M.sub.GATE1 and the output of M.sub.INV1. From this topology, the master latch 122 and slave latch 118 can be connected with switches.

    [0181] FIG. 50 shows another embodiment of a DFF 120 with its slave latch 122 replaced with an embodiment of the latch topology of FIG. 29. The same topology of the latch in FIG. 29 can be used but with a first slave inverter, S.sub.INV1, in place of M.sub.1 and a second slave inverter, S.sub.INV2, in place of M.sub.2. For example, the output of S.sub.INV1 can be connected to M.sub.3-gate, M.sub.3-source, M.sub.4-source, M.sub.4-gate, data output Q, S.sub.INV2 output, M.sub.5-gate, M.sub.7-gate, M.sub.5-drain, data output QN, M.sub.6-drain, M.sub.6-gate, and M.sub.8-gate. The output of S.sub.INV2 can be connected to M.sub.3-gate, M.sub.3-source, M.sub.4-source, M.sub.4-gate, data output Q, S.sub.INV1 output, M.sub.5-gate, M.sub.7-gate, M.sub.5-drain, data output QN, M.sub.6-drain, M.sub.6-gate, and M.sub.8-gate.

    [0182] The master latch 122 can be connected to the slave latch 118 via S.sub.INV1 and S.sub.INV2. For example, the master latch 122 can have a first master transmission gate M.sub.GATE1, a first master inverter, M.sub.INV1, a second master inverter, M.sub.INV2, and a second master transmission gate, M.sub.GATE2. The input of M.sub.GATE1 can be connected to a data input signal, D. The output of M.sub.GATE1 can be connected to the input of M.sub.INV1 and the input of S.sub.INV1. The input of M.sub.INV1 can be connected to the output of M.sub.GATE1. The output of M.sub.INV1 can be connected to the input of M.sub.INV2 and the input of S.sub.INV2. The input of M.sub.INV2 can be connected to the output of M.sub.INV1. The output of M.sub.INV2 can be connected to the input of M.sub.GATE2. The input of M.sub.GATE2 can be connected to the output of M.sub.INV2. The output of M.sub.GATE2 can be connected to the input of M.sub.GATE1 and the output of M.sub.INV1. From this topology, the master latch 122 and slave latch 118 can be connected with clocked inverters for isolation.

    [0183] FIG. 51 shows another embodiment of a DFF 120 with its slave latch 122 replaced with an embodiment of the latch topology of FIG. 30 The same topology of the latch in FIG. 30 can be used but with a slave inverter, S.sub.INV, in place of M.sub.1 and M.sub.2. For example, the output of S.sub.INV can be connected to M.sub.3-gate, M.sub.5-gate, M.sub.7-gate, M.sub.11-source, M.sub.12-source, M.sub.3-source, M.sub.9-source, M.sub.10-source, M.sub.5-drain, and M.sub.5b-drain.

    [0184] The master latch 122 can be connected to the slave latch 118 via S.sub.INV. For example, the master latch 122 can have a first master inverter M.sub.INV1, a second master inverter, M.sub.INV2, a third master inverter, M.sub.INV3, and a master transmission gate, M.sub.GATE. The input of M.sub.INV1 can be connected to a data input signal, D. The output of M.sub.INV1 can be connected to the input of M.sub.INV2. The input of M.sub.INV2 can be connected to the output of M.sub.INV1. The output of M.sub.INV2 can be connected to the input of M.sub.INV3 and the input of S.sub.INV. The input of M.sub.INV3 can be connected to the output of M.sub.INV2. The output of M.sub.INV3 can be connected to the input of M.sub.GATE. The input of M.sub.GATE can be connected to the output of M.sub.INV3. The output of M.sub.GATE can be connected to the input of M.sub.INV2 and the output of M.sub.INV1.

    [0185] With reference to FIGS. 49-52, embodiments of the DFF 120 can be configured as a positive-edge-triggered DFF, wherein making the slave latch 118 nonvolatile can simplify clocking during restore, as the slave latch 118 is isolated from the input data when CLK is low (i.e., in hold/restore phase). With the topology of FIG. 49, the structure is simple and has the minimum overhead in terms of number of additional transistors (as compared to the conventional topology of FIG. 52). However, the driving strength of the master latch 122 should be sufficient to make sure a new state could be set up in time for the slave latch 118. Also, the possible bleeding current from D through an input switch would affect the timing behavior. FIG. 50 uses clocked inverters as a buffer to drive the slave latch 118 and to isolate the possible bleeding current between master and slave stages. With the designs in FIGS. 51 and 52, clocked inverters instead of CMOS switches are used to drive the master latch and slave latch to provide better kick-back isolation between the two stages and the driver of D. It is noted, however, that the DFF 120 of FIG. 51 has only 6 more transistors than the conventional CMOS DFF of FIG. 52, with a total of 30 transistors including a local clock driver.

    [0186] The setup and hold time of the DFF 120 with the topology in FIG. 51 will be almost identical to that of the conventional CMOS volatile DFF in FIG. 52. This property can stem from a master latch of the same structure and size being used in both designs that features a clocked inverter to provide isolation.

    [0187] FIG. 53 shows the transient simulation waveforms of an embodiment of the DFF 120. With a steady V.sub.DD, embodiments of the DFF 120 can carry out the positive-edge-triggered sample-and-hold operations. The intrinsic non-volatility of latch topologies disclosed herein is inherited to the DFF 120. As shown in FIG. 53, during power failures, the polarization of the FeFETs 102 maintains stable. When power supply recovers, the restore operations automatically restore the output Q and QN to its previous state before the power failure. In FIG. 53, the backup and restore operations for bit 0 and bit 1 are shown around 4-6 s and 9-11 s, respectively.

    [0188] FIGS. 54-57 compare the backup and restore performance metrics of an embodiment of the DFF with a conventional DFF design based on ferroelectric capacitor and another conventional DFF design based on a NCFET DFF. FIG. 54 shows supply voltage as a function of backup energy for an embodiment of a DFF 120 compared to conventional DFFs. FIG. 55 shows supply voltage as a function of restore energy for an embodiment of a DFF 120 compared to conventional DFFs. FIG. 56 shows supply voltage as a function of backup time for an embodiment of a DFF 120 compared to conventional DFFs. FIG. 57 shows supply voltage as a function of restore time f for an embodiment of a DFF 120 compared to conventional DFFs. Conventional designs used more complex backup and restore circuit schemes, need multiple steps to carry out the operations, may cause static leakage current if the polarization state is positive (low-resistance state). Some conventional DFF designs can causes tens of times higher energy overheads. Conversely, embodiments of the DFF 120 a significant amount of energy could be saved for backup and restore operations, which can be due to the removal of the complex driving and sensing schemes for the ferroelectric capacitor. Thanks to the deeply embedded logic-in-memory operation in the disclosed simple and effective circuit structure, embodiments of the DFF 120 facilitate low-energy operations.

    [0189] It is also noted that embodiments of the DFF 120 has lower backup and restore speed than conventional DFFs. This can be due to the adoption of low-power (high V.sub.TH) CMOS transistors to achieve low leakage current for low-power IoT applications. For example, conventional NCFET based DFFs have around 0.12 W static leakage power when operating at 0.8V supply, while the embodiments of the DF 120 can have less than 0.2 nW at 0.8V. The backup and restore speed of embodiments of the DFF 120 are sufficiently fast for most if not all scenarios, as charging and discharging the supply network on the chip following a power failure and recovery usually takes much longer time than a few nanoseconds. The adoption of high V.sub.TH MOSFETs in the main signal routes can also improve the reliability during backup and restore operations.

    [0190] FIG. 58 compares the energy versus delay between embodiments of the DFF 120 and conventional DFF designs. Embodiments of the DFF 120 have around 35% energy-delay-product overhead. Note that the energy here includes the backup energy consumed after Q/QN settles down. For applications with a higher bit-rate or dynamic frequency scaling (DFS) in which the clock cycle is shorter than the polarization switching time, the energy overhead could be much smaller. More importantly, for many IoT applications in which the processor is normally idle, most energy is consumed by the stand-by leakage. In these scenarios, a moderate energy overhead is fairly acceptable.

    [0191] Additional advantages of embodiments of the DFF 120 over some conventional DFF devices can stem from the fact that the conventional DFF devices may be two-terminal devices, wherein the change of their memory state requires a static current or voltage across them for a certain period of time. Such static current, especially considering the widened time window for write operations due to the impact of device variations, significant amount of energy will be consumed by them. Furthermore, the great scalability, low-voltage operation, high ON-OFF ratio, and the unique external-control-free feature, highlight additional advantage of embodiments of the DFF 120.

    [0192] Given an FEFET 102 structure and the ferroelectric material, the tunable FeFET design parameter is the ferroelectric layer thickness T. During device optimizations, the first concern is the retention time. For FeFET memory devices, it depends on the energy barrier between the two polarization states. Increasing T.sub.FE can helps increasing the coercive voltage that is required to change the polarization. However, it results in a larger minimum required supply voltage, which indicates more energy consumption each time the polarization is switched.

    [0193] It is noted that the restore functionality of the embodiments of the latches 118, 122 and DFFs 120 depends on the difference of the sensed resistance from Q/QN to GND or V.sub.DD, which indicates that the sensitivity of the sensed resistance may be critical for yield. For simplicity, only the sensed resistance to GND, i.e. RQ2GND, was analyzed. For en embodiment of the DFF 120, the sensed resistance can be defined as the sum of the series FeFET drain-source resistance RFeFET and the NMOS drain-source resistance RCMOS. When storing a different latch bit information, the key difference in the initial sensed resistance, without considering process non-idealities, varies in RFeFET. As a result, the ratio of RQ2GND between the two branches in the latch can be:

    [00001] = .Math. R Q .Math. .Math. 2 .Math. .Math. GND , .Math. ' 1 ' / R Q .Math. .Math. 2 .Math. GND .Math. '0' = .Math. ( R NCFET , .Math. '1' + R CMOS , .Math. '1' ) / ( R NCFET , .Math. '0' + R CMOS , '0' ) .Math. R CMOS , .Math. '1' / ( R NCFET , .Math. '0' + R CMOS , '0' ) .

    [0194] A smaller will lead to more stable restore operation and is more noise-resistant. A small RCMOS or a large RFeFET, 0 is thus helpful. Considering the orders of difference in the ON-OFF resistance of RFeFET, the approximation in the equation above is rather safe. For this purpose, T.sub.FE is set to be 8 nm so as to provide large ON-OFF state resistance while enabling low-voltage operation. Since the degradation of F can be easily caused by the variation of the NMOS initial resistance, RCMOS, 0 and RCMOS, 1, analysis should be carried out. This is especially important for designs of the DFF 120, because another parallel branch (see M.sub.5b and M.sub.6b) is affecting F, too. The difference in RCMOS, 0 and RCMOS, 1 mainly comes from device size mismatch and threshold voltage V.sub.TH variation V.sub.TH. By manually adding an opposite in-series gate driving voltage to the gate, as shown in FIG. 59, the impact of V.sub.TH can be quantified through a series of simulations. The results are summarized in FIG. 60, with V.sub.DD ramp-up time equal to 0.8 s to mimic typical real scenarios. The results show that, within the 0.5V to 1.0V supply voltage range, the design is reliable with V.sub.TH no more than 30 mV. Note that this result provides a fairly large margin for design, as all the MOSFETs in FIG. 59 are having an unfavorable direction of V.sub.TH variation if the FeFETs on the left and right branches store a negative and positive polarization state, respectively.

    [0195] It is also interesting to find out, that the variation impact is independent on the supply voltage within the given range of 0.5V to 1.0V. This is because of the relatively long rising time for the supply voltage to recover, and the fact that the initial restore trend is almost equal for scenarios with different V.sub.DD. To provide a small F, the latch is designed in a way that all CMOS transistors have a higher V.sub.TH than the bottom two transistors connecting to FeFETs (e.g., M.sub.7 and M.sub.8). By doing this, the following goals could be achieved: (i) The resistance of M.sub.7 and M.sub.5b, or that of M.sub.8 and M.sub.th, plays a less significant role than that of FeFETs, as M.sub.7 is in series with the FeFET, and M.sub.5b is in parallel with the FeFET. This will help built the correct rising trend of Q and QN when V.sub.DD starts to recover. (ii) Static leakage current of the latch will not increase. This can be guaranteed by a proper FeFET design with a high OFF-state resistance. Given a certain ferroelectric material and transistor structure, this OFF-state resistance could be tuned by varying T.sub.FE and the width of FeFET 102. The large inherent ON-OFF resistance ratio will help to reduce the impact of FeFET variation.

    [0196] Embodiments of the DFF 120 could be strongly complementary to existing power-gating approaches in both low and high-performance systems. In aggressive, high speed systems using fine-grained, low-latency power-gating techniques, the ability to power-gate stateful units up to and including entire processor cores within a handful of cycles would both expand the scope of what can be power-gated and simplify design constraints. While the impact of no need for backup and restore control for power-gating is still not yet fully explored, it is promising to open up new possibilities for further energy savings and architecture optimizations due to the reduced control complexity. On the energy-harvesting end of the spectrum, one apparent benefit is the reduced backup and restore energy consumption and latency, which improves the utilization of harvested energy for the purpose computation. The intrinsic non-volatility ensures no missing backup without the need for backup control, leading to prevention of roll-back operations in the computation progress. While there are already works on nonvolatile processor optimizations, further architecture-level optimizations would be useful to capture the intrinsic non-volatility of FeFET flip-flops. Meanwhile, it has been shown that the recovery time in NVPs after a power emergency are sometimes dominated by the recovery of analog components, such as ensuring PLL stability. While this limits the impact of the rapid recovery time that NC-DFFs have in such systems, their rapid, completely distributed and low energy backup properties may allow power gating of data path and other digital components fast enough to divert energy during shorter or less severe power emergencies in order to preserve analog functionality, using embodiments of the DFF 120F cycle-latency (at NVP frequencies) power gating potential to shave microseconds off recovery times.

    [0197] Embodiments of the NMV device 100 can be configured as a memory cell 124. Embodiments of the memory cell 124 can be configured with a 2-transistor FeFET 102 topology between the Wordline and the Readline (2T-memory cell 124) or a 3-transistor FeFET 102 topology between the Wordline and Readline (3T-memory cell 124). Embodiments of the memory cell 124 can facilitate an improved memory access method.

    [0198] For example, embodiments of the memory cell 124 can include at least one FeFET 102 to provide intrinsic non-volatility, compatibility with commercial CMOS processes, both high ON-state current and low OFF-state current, and/or merged logic-memory functionality, which can facilitate convenient writing and nondestructive reading for the memory cell 124. Embodiments of the memory cell 124 can have high energy-efficiency and high write speed, along with improved performance and energy versus latency tradeoffs for writes. Embodiments of the memory cell 124 can support voltage-mode sensing for read access, which can broaden design space flexibility in support of different application scenarios.

    [0199] As noted herein, nonvolatile memory arrays can be used to reduce or eliminate static leakage power in embedded memories by completely shutting down the power supply while retaining the stored data and computation progress. Conventional nonvolatile devices can be limited by requiring the write operation to depend on the voltage change at the FeFET gate only and not concurrently at the FeFET drain and source. This can require a doubled gate driving voltage range to set the memory state, resulting in multi-supply overheads and loss of energy efficiency. In addition, a voltage-mode read is not supported with conventional topologies for nonvolatile devices, causing high design overheads for read access in some scenarios due to bit-line current sensing and voltage clamping.

    [0200] FIGS. 61-63 show a FeFET 102 in a fin structure, which can be a MOSFET with an extra ferroelectric gate insulator, such as doped hafnium dioxide. FIG. 61 shows a schematic for an N-type FeFET 102, FIG. 62 shows a fin-structured FeFET device, and FIG. 63 shows a typical hysteretic G.sub.DSV.sub.GS extracted form one fin of a fin-structured FeFET device at V.sub.DS=10 mV. FeFET device parameters for the LK equation were: =1.05109 m/F, =1107 m5/F/C2, and =61011 m9/F/C4. The ferroelectric material was adopted in this structure for the purpose of steep switching behavior with a sub-threshold swing (SS) lower than 60 mV/dec so that the transistor could be used to build lower-power logic gates. Making use of the voltage booting function of the negative capacitance of the ferroelectric material can be done to increase the internal MOSFET gate voltage. In addition, as noted herein, increasing the ferroelectric layer thickness (T.sub.FE), when the negative ferroelectric capacitance is smaller than the positive MOSFET gate capacitance, a hysteresis appears and may exhibit distinct ON and OFF states with zero gate-source voltage (V.sub.GS) based on the direction of the ferroelectric material polarization.

    [0201] For conventional logic gates, hysteresis should be strictly controlled or minimized to comply with the logic operation. On the contrary, it is intriguing to use the hysteresis for low-power NVM applications.

    [0202] FIG. 64 shows an exemplary energy landscape plot for an embodiment of a FeFET 102. FIG. 65 shows static internal states with an embodiment of the FeFET 102 biased at V.sub.GS=0. The polarization state of the ferroelectric material is stable at zero V.sub.GS. As the energy landscape plot in FIG. 64 shows, the stable polarization state stays close to the two lowest-energy region. For a zero-V.sub.GS FeFET in the OFF (or ON) state, a stable positive (or negative) voltage across the ferroelectric layer, V.sub.FE, and accordingly a negative (or positive) internal gate-source voltage of the internal MOSFET, V.sub.MOS, lead to different G.sub.DS states.

    [0203] The two nonvolatile G.sub.DS states in FIG. 65 show over four orders of difference in magnitude, leading to low-cost sensing schemes to distinguish the state difference. This is superior to existing nonvolatile devices. The sharp transitioning between different states also helps to maintain a larger noise margin. These advantages come from FeFET 102 features of: (i) the settling-down transition behavior in the energy landscape as a passive amplification for V.sub.MOS, and (ii) the gain of the internal MOSFET from V.sub.MOS to sensed current I.sub.DS. For conventional nonvolatile devices. no MOSFET gain is intrinsically provided and sensing the ferroelectric material is more complex and sensitive to the external bit-line parasitic capacitance.

    [0204] With proper MOSFET work function engineering and ferroelectric material design that matches the MOSFET properties, e.g. the gate capacitance, it is possible to locate the FeFET I-V hysteresis window around zero V.sub.GS with embodiments of the FeFET 102. By tuning T.sub.FE, the hysteresis width could also be optimized to work under a proper supply voltage, as shown in FIG. 63.

    [0205] Embodiments of the FeFET 102 can have integrated the NVM storage and the logic transistor operating as a memory state amplifying reader. Such integration not only provides the opportunity to design a simplified low-power sensing scheme, but also opens up new space for future memory-oriented computing.

    [0206] The polarization switching can be accomplished by applying a positive or negative voltage across the ferroelectric layer 114. Different from the state change in resistive memory devices, no static DC current is consumed for embodiments of the FeFET 102 (biased with V.sub.DS=0V). Furthermore, when considering the resistive memory device variations of required write pulse duration, even more energy could be saved.

    [0207] It should be noted that the ferroelectric material in FeFETs could be the same as that in ferroelectric random access memory (FeRAM) devices, leading to similar memory features of retention time, endurance, etc. Yet, the FeFET memory read operation is non-destructive, which outperforms FeRAM. In addition, FeFET is fundamentally superior to FeRAM with better distinguishability and access interface.

    [0208] Referring to FIG. 66, embodiments of the 2T-memory cell 124 can include a first transistor T.sub.1, a second transistor T.sub.2, a bit line, BL, a first Wordline, WLW, and a second Wordline, WLR. T.sub.1 can be a MOSFET. T.sub.1 can have a T.sub.1-source, a T.sub.1-gate, and a T.sub.1-drain. T.sub.2 can be a FeFET 102. T.sub.2 can have a T.sub.2-source, a T.sub.2-gate, and a T.sub.2-drain. WLW can be configured to receive and/or transmit a write signal for write operations. WLR can be configured to receive and/or transmit a read signal for read operations. T.sub.2-drain can be connected to BL and WLW. T.sub.2-gate can be connected to WLW. T.sub.2-source can be connected to T.sub.1-drain. T.sub.1-gate can be connected to WLR and BL. T.sub.1-source can be connected to GND.

    [0209] Some embodiments can include a plurality of 2T-memory cells 124. For example, a memory cell array 126 can include a first 2T-memory cell 124, a second 2T-memory cell 124, a third 2T-memory cell 124, etc. In at least one embodiment, the memory cell array 126 can include a first 2T-memory cell 124, a second 2T-memory cell 124, a third 2T-memory cell 124, a fourth 2T-memory cell 124, a fifth 2T-memory cell 124, a sixth 2T-memory cell 124, a seventh 2T-memory cell 124, and an eighth 2T-memory cell 124. The memory cell array 126 can have a first BL, BL1, a second BL, BL2, a third BL, BL3, and a fourth BL, BL4. The memory cell array 126 can have a first WLW, WLW1, a second WLW, WLW2, a first WLR, WLR1, and a second WLR, WLR2. Each memory cell 124 can have a T.sub.1 and a T.sub.2, wherein T.sub.1 is a MOSFET and T.sub.2 is a FeEFT 102. For example, the first 2T-memory cell 124 can have a first T.sub.1 and a first T.sub.2. The second 2T-memory cell 124 can have a second T.sub.1 and a second T.sub.2. The third 2T-memory cell 124 can have a third T.sub.1 and a third T.sub.2. The fourth 2T-memory cell 124 can have a fourth T.sub.1 and a fourth T.sub.2. The fifth 2T-memory cell 124 can have a fifth T.sub.1 and a fifth T.sub.2. The sixth 2T-memory cell 124 can have a sixth T.sub.1 and a sixth T.sub.2. The seventh 2T-memory cell 124 can have a seventh T.sub.1 and a seventh T.sub.2. The eighth 2T-memory cell 124 can have an eighth T.sub.1 and a eighth T.sub.2. Each of WLW1 and WLW2 can be configured to receive and/or transmit a write signal for write operations. Each of WLR1 and WLR2 can be configured to receive and/or transmit a read signal for read operations.

    [0210] For the first 2T-memory cell 124, first cell T.sub.2-drain can be connected to BL1 and WLW1. First cell T.sub.2-gate can be connected to WLW1. First cell T.sub.2-source can be connected to first cell T.sub.1-drain. First cell T.sub.1-gate can be connected to WLR1 and BL1. First cell T.sub.1-source can be connected to GND. For the second 2T-memory cell 124, second cell T.sub.2-drain can be connected to BL2 and WLW1. Second cell T.sub.2-gate can be connected to WLW1. Second cell T.sub.2-source can be connected to second cell T.sub.1-drain. Second cell T.sub.1-gate can be connected to WLR1 and BL2. Second cell T.sub.1-source can be connected to GND. For the third 2T-memory cell 124, third cell T.sub.2-drain can be connected to BL3 and WLW1. Third cell T.sub.2-gate can be connected to WLW1. Third cell T.sub.2-source can be connected to third cell T.sub.1-drain. Third cell T.sub.1-gate can be connected to WLR1 and BL3. Third cell T.sub.1-source can be connected to GND. For the fourth 2T-memory cell 124, fourth cell T.sub.2-drain can be connected to BL4 and WLW1. Fourth cell T.sub.2-gate can be connected to WLW1. Fourth cell T.sub.2-source can be connected to fourth cell T.sub.1-drain. Fourth cell T.sub.1-gate can be connected to WLR1 and BL4. Fourth cell T.sub.1-source can be connected to GND. For the fifth 2T-memory cell 124, fifth cell T.sub.2-drain can be connected to BL1 and WLW2. Fifth cell T.sub.2-gate can be connected to WLW2. Fifth cell T.sub.2-source can be connected to fifth cell T.sub.1-drain. Fifth cell T.sub.1-gate can be connected to WLR2 and BL1. Fifth cell T.sub.1-source can be connected to GND. For the sixth 2T-memory cell 124, sixth cell T.sub.2-drain can be connected to BL2 and WLW2. Sixth cell T.sub.2-gate can be connected to WLW2. Sixth cell T.sub.2-source can be connected to sixth cell T.sub.1-drain. Sixth cell T.sub.1-gate can be connected to WLR2 and BL2. Sixth cell T.sub.1-source can be connected to GND. For the seventh 2T-memory cell 124, seventh cell T.sub.2-drain can be connected to BL3 and WLW2. Seventh cell T.sub.2-gate can be connected to WLW2. Seventh cell T.sub.2-source can be connected to seventh cell T.sub.1-drain. Seventh cell T.sub.1-gate can be connected to WLR2 and BL3. Seventh cell T.sub.1-source can be connected to GND. For the eighth 2T-memory cell 124, eighth cell T.sub.2-drain can be connected to BL4 and WLW2. Eighth cell T.sub.2-gate can be connected to WLW2. Eighth cell T.sub.2-source can be connected to eighth cell T.sub.1-drain. Eighth cell T.sub.1-gate can be connected to WLR2 and BL4. Eighth cell T.sub.1-source can be connected to GND.

    [0211] FIG. 67 shows the operating status of the 2T-memory cell 124 of FIG. 66 in terms of G.sub.DS versus VG.sub.S. In the power-off mode, the bit line and word lines are grounded and the FeFETs 102 stay with G.sub.DS being high or low as illustrated in the power-OFF mode. With the power turned on, the cells in rows not being read or written are in the idle mode with WLW voltage set to about V.sub.DD/2 and WLR to GND. Thus, this idle-mode cell does not deliver a DC current or affect the BL sensing result. Note that V.sub.BL could vary from GND to V.sub.DD as BL could be controlled by other active rows being read or written. In this case, the FeFET 102 operating point could be in a consecutive region (as opposed to single pinpoints) in the G.sub.DS versus V.sub.GS curve. To prevent the idle-mode FeFET polarization state being flipped, the stable hysteresis region should safely cover this range through device-circuit co-design methods like tuning T.

    [0212] Embodiments of the memory cell array 126 can operate with a row-wise read. FIG. 68 shows an exemplary read operation with pre-charged BL. V.sub.WLW is set to about V.sub.DD/2 to keep the FeFET polarization unchanged. V.sub.WLR is set to V.sub.DD to turn on T.sub.1. The memory cell array 126 topology supports both voltage-sensing and current-sensing read. In a voltage-sensing read, BL can be pre-charged, to V.sub.DD or some other voltage above GND. When WLR is enabled to turn on T.sub.1, V.sub.BL may remain high if T.sub.2 is in the OFF state, or discharge quickly to GND if T.sub.2 is in the ON state. Such a difference in BL settling behavior could be conveniently sensed with a voltage sense amplifier connecting to BL. In addition, the memory read result may be achieved before BL eventually settles down to GND, as long as the sense amplifier could effectively tell the voltage difference of V.sub.BL between the two memory read scenarios.

    [0213] If current-sensing read is adopted, the bit line voltage V.sub.BL should be fixed, and the current from the bit line to the ground through the cell in the selected row can be sensed by a current sense amplifier, similar to existing resistive memory array sensing schemes. This can help to reduce the sensing latency by avoiding charging and discharging the long bit-line parasitic capacitance for a large-size array. The capability of supporting both sensing modes provides more case-to-case design flexibility.

    [0214] FIG. 69 shows an exemplary write operation setup. V.sub.BL can be set to GND and V.sub.DD to write 0 and 1, respectively. V.sub.WLR can be set to GND to turn off T.sub.1. V.sub.WLW can be set to V.sub.DD in the first phase and then GND in the second phase. As WLW is shared with all bits in the word, such a two-phase write method enables writing different values for different bits in the same word line. To write 0, the FeFET polarization switching to the desired positive state occurs during the first phase with V.sub.WLW=V.sub.DD. Setting V.sub.WLW to be beyond the hysteresis rising edge (with T.sub.2 source voltage at GND) triggers the polarization switching. To write 1, the FeFET polarization switching occurs for the desired negative state. If the polarization state of the T.sub.2 is positive, the internal node X would charge to V.sub.DD by BL through the ON-state of T.sub.2. Then, when V.sub.WLW becomes GND in the second phase, T.sub.2 is biased with V.sub.G=GND, V.sub.S=V.sub.D=V.sub.DD, leading to a polarization switching to be negative. It is noted that, V.sub.WLW could also be set to GND and V.sub.DD in the first and second write phases, respectively.

    [0215] FIG. 70 is a snapshot of a SPICE transient simulation waveform of an embodiment of the memory cell array 126, showing polarization statuses for the FeFET transistors. For the simulation, T.sub.FE is 8 nm. was 0.25 and V.sub.DD was 0.6V. The polarization switching speed in FIG. 70 was based on a relatively large and consequently a slow FeFET. The switching speed could be much faster with a smaller . The read latency in FIG. 70 depends on the bit line parasitic capacitance, which increases as the array size increases.

    [0216] Embodiments of a 3T-memory cell 124 can provide additional design flexibility in certain scenarios. FIG. 71 shows an embodiment of a 3T-memory cell 124, with the 3T-memory cell 124 in a two-bit line topology and a single-bit line topology for a voltage-sensing read mode.

    [0217] The 3T-memory cell 124 having a two-bit line topology can have a first transistor, T.sub.1, a second transistor, T.sub.2, a third transistor T.sub.3, a first bit line, BLW, a second bit line, BLR, a WLW, a WLR, and a Wordline-Readline, WLRL. T.sub.1 and T.sub.3 can be MOSFETs. T.sub.2 can be a FeFET 102. T.sub.1 can have a T.sub.1-source, a T.sub.1-gate, and a T.sub.1-drain. T.sub.2 can have a T.sub.2-source, a T.sub.2-gate, and a T.sub.2-drain. T.sub.3 can have a T.sub.3-source, a T.sub.3-gate, and a T.sub.3-drain. T.sub.1-drain can be connected to T.sub.2-gate. T.sub.1-gate can be connected to WLW. T.sub.1-source can be connected to BLW. T.sub.2-drain can be connected to T.sub.3-source. T.sub.2-gate can be connected to T.sub.1-drain. T.sub.2-source can be connected to WLRW. T.sub.3-drain can be connected to BLR. T.sub.3-gate can be connected to WLR. T.sub.3-source can be connected to T.sub.2-drain. Any one or combination of BLW, WLW, and WLRW can be connected to GND. WLR can be connected to V.sub.DD.

    [0218] The 3T-memory cell 124 can have one write-access N-type MOS transistor T.sub.1 controlled by the write-access word line WLW, one read-access N-type MOS transistor T.sub.3 controlled by the read-access word line WLR, and to storage N-type FeFET T.sub.2 connecting to the wordline WLRW for both read and write. The cell 124 uses two bit lines: BLR for read and BLW for write. In power-OFF and idle modes, all word lines and bit lines could be safely grounded. Both voltage sensing and current sensing could be used to perform read. In the voltage-sensing read, T.sub.3 can be turned ON, and WLRW set to GND. The pre-charged V.sub.BLR will remain almost unchanged with an OFF-state T.sub.2 or drop quickly to GND with an ON-state T.sub.2. A voltage thresholding of V.sub.BLR could provide the sensing result for a voltage-mode sensing scheme. In the current-mode sensing scheme, V.sub.BLR can be fixed and T.sub.3 turned ON. Thus, the current delivered by the cell can be sensed at the bit line, providing another meaningful option for energy-delay optimization in a larger memory array.

    [0219] The 3T-memory cell 124 having a single-bit line topology can have a first transistor, T.sub.1, a second transistor, T.sub.2, a third transistor T.sub.3, a bit line, BL, a WLW, a WLR, and a WLRL. T.sub.1 and T.sub.3 can be MOSFETs. T.sub.2 can be a FeFET 102. T.sub.1 can have a T.sub.1-source, a T.sub.1-gate, and a T.sub.1-drain. T.sub.2 can have a T.sub.2-source, a T.sub.2-gate, and a T.sub.2-drain. T.sub.3 can have a T.sub.3-source, a T.sub.3-gate, and a T.sub.3-drain. T.sub.1-drain can be connected to T.sub.2-gate. T.sub.1-gate can be connected to WLW. T.sub.1-source can be connected to BL. T.sub.2-drain can be connected to T.sub.3-drain. T.sub.2-gate can be connected to T.sub.1-drain. T.sub.2-source can be connected to WLRW. T.sub.3-drain can be connected to T.sub.2-drain. T.sub.3-gate can be connected to WLR. T.sub.3-source can be connected to BL.

    [0220] FIG. 72 shows an embodiment of a 3T-memory cell 124 having a two-bit line topology in write mode using a two-step write method. A row-wise write operation is shown when T.sub.3 is turned OFF, T.sub.1 is turned ON, BLW set to GND, and V.sub.DD to write 1 and write 0. A two-phase voltage setting for WLRW can be adopted, changing from V.sub.DD to GND. Write operation for 1 and 0 occurs in the V.sub.DD phase with V.sub.GS=V.sub.DD and GND phase with V.sub.GS=V.sub.DD, respectively. If the two bit lines are merged into one to form the single-bit line topology, bit line BL would inherit the BLW setting of the two-bit line topology. V.sub.WLRW could be GND in the first phase and V.sub.DD in the second phase for the write.

    [0221] FIG. 73 shows SPICE transient simulation waveforms for an embodiment of the cell 124. For the simulation, T.sub.FE was 10 nm, was 0.1, and V.sub.DD was 0.8V. Voltage-sensing mode read was applied. An optional write pre-charge of write bit line BLW was adopted so that V.sub.BLW was set slightly prior to the setting of word lines. In practice, this would improve the write latency as the polarization switching in the write operation can start as soon as the word line is ready. In the simulations, a 50 fF parasitic capacitor was assumed for each bit, a 10 nm FeFET model was used, based on the LK equation with PZT as the ferroelectric material.

    [0222] For fair comparison, no negative supply was used. For the conventional cell designs, the use of negative supply voltage of V.sub.DD was prevented by equally shifting up all supply and biasing voltages by V.sub.DD, as shown in FIG. 74. Different from embodiments of the memory cell 124 disclosed herein, conventional cell designs have the same and fixed drain and source voltage during writing 0 and 1, resulting in the need of a doubled voltage range, as illustrated in FIG. 74. Note that this supply voltage range is 2V.sub.DD even if the negative supply is kept in the conventional cell design. Embodiments of the memory cell 124 were also evaluated with T.sub.FE=12 nm for a wider FeFET hysteresis window to extend the supply voltage operation range.

    [0223] The write energy is the average energy consumed to write 1 and 0 from a different prior state. The write operation latency covers a different period of time between the embodiments of the memory cell 124 and conventional cell designs. For embodiments of the For the memory cell 124 that adopt two-phase write, it is the sum of latency in writing 0 and 1. For the conventional cell designs, the write operation latency is defined as the maximum latency to write 0 and write 1.

    [0224] FIG. 75 shows the simulated write energy per cell versus the write latency for embodiments of the memory cell, as compared to a conventional memory cell. In addition to low write energy and latency of the disclosed designs, a few observations are manifest: First, a higher supply voltage leads to less latency and more energy consumption. Due to no-DC-current write, no more than 2% of the average write energy is consumed to switch the polarization. Second, the 2T-memory cell 124 with a higher T.sub.FE of 12 nm has higher write latency than that 2T-memory cell 124 with 10.5 nm T.sub.FE, even under the same supply voltage. This is because of a different ferroelectric energy landscape and wider hysteresis width. Third, the 3T-memory cell 124 with 10.5 nm T.sub.FE has the write energy-latency curve that lies in between the two curve segments of the 2T-memory cell 124. At the higher-voltage segment, the 3T-memory cell 124 has lower latency than the 2T-memory cell 124 with T.sub.FE=12 nm, mainly because of an intrinsically faster FeFET. At the lower-voltage segment, the 3T-memory cell 124 has higher write latency than the 2T-memory cell 124 with T.sub.FE=10.5 nm, mainly because of the write mechanism differences: before WLW is effectively triggered, the 2T-memory cell 124 can use a prior read operation and BL preset to set the desired voltage for both drain and source of the FeFET. While the 3T-memory cell 124 has neither the source nor drain of the FeFET preset (after a read operation, the internal node X is desired to be GND but charged to V.sub.DD, and is desired to be V.sub.DD but was discharged to GND). Last, conventional cells have the highest write energy. This is mainly because of the required doubled voltage to charge the bit line. In addition, it also results in higher voltage stress on the write-access transistor, which may induce a stability problem and also a power problem as the drain-body or source-body interface diode may be turned on with a high voltage across it.

    [0225] It should be noted that, the write latency was based on set as 0.1. The energy and latency as a function of are provided in FIG. 76, wherein the left side plot if for a fixed and the right side plot is for a varying at V.sub.DD=07.5V. The write energy is almost constant and unrelated to the polarization switching speed, while the write latency strongly linearly reacts to the kinetic coefficient, as is expected.

    [0226] The current-sensing read performance was not simulated as it strongly depends on the current sense amplifier design. Therefore, only the voltage-sensing read operations were evaluated. The read operation energy is the average energy consumed to read 1 and 0. As reading 1 does not noticeably change the bit line voltage, the read operation latency is actually equal to the latency for the read of 0, which is defined as the delay from the effective word line triggering point (with 50% voltage change) to the point when the read bit line voltage has reduced by 150 mV. Practically, a voltage difference of 150 mV could be sensed with a voltage-mode amplifier that does not require a high gain.

    [0227] FIG. 77 shows the simulated read energy per cell versus read latency for an embodiment of the memory cell 124. Data for a conventional memory cell was is not included as it does not support voltage-mode sensing. Thanks to the ultra-low OFF-state current and high ON-state current, ultra-low read energy and latency are achieved for embodiments of the memory cell 124. In addition, the following conclusions could be reached: First, most read energy is consumed in pre-charging the bit line capacitance. For read, pre-charging the bit line is required for both 0 and 1. In contrast, for write, pre-charging of the bit line is required only for writing 1 in the 2T and 3T topologies. Consequently, more energy is consumed by read than write. Second, the read latency reduces as the supply voltage increases. This is because the read access transistors have lower resistance and discharge the bit line faster. For the 2T topology with different T.sub.FE, the read latency difference is not quite significant at 0.7V and 0.8V because the discharging current is mainly limited by the read access MOSFET and the FeFET is not the bottleneck element. Third, the 2T topology has relatively lower read latency than the 3T topology. This is because (i) the 2T topology is biased at V.sub.DD/2 at the FeFET gate while the 3T topology is biased with GND at the FeFET gate; (ii) the 2Ttoplogy always has V.sub.GS=V.sub.DD for the access NMOS while the 3T topology has V.sub.GS=V.sub.DD only at the beginning point for the read access transistor T.sub.3. It is also feasible to use a lower voltage to pre-charge the bit line for read to reduce the read energy consumption as long as the sensing scheme is not the bottleneck.

    [0228] Table 4 summarizes the benchmarking results, where the comparison of embodiment so of the memory cell's 124 access performance, density, peripheral circuitry requirement is displayed. It is also interesting to consider the OFF-to-Ready energy, which is the energy needed to wake up a cell array 126 from completely OFF state to the idle state ready for read and write. With the 2T topology, considering some idle-state biasing voltage settings are non-zero, the memory controller has to raise its voltage level accordingly and thus consumes extra energy. Embodiments of the 3T topology can operate with the largest supply voltage range, and does not require an extra supply voltage of V.sub.DD/2 or 2V.sub.DD, making it a good fit in scenarios when multi-supply is not available.

    TABLE-US-00004 TABLE 4 Comparison of a Conventional Memory Cell and Embodiments of The Disclosed Memory Cells 124 Specifications Conv. Cell 2T-Topology 3T-Topology Number of transistors 2 2 3 Low voltage operation No Yes Yes Write energy Medium Low Low Write speed.sup.& Medium High High Current-mode read speed.sup.# High High High Current-mode read energy.sup.# Low Low Low Voltage-mode read speed High High Voltage-mode read energy Low Low OFF-to-Ready energy High Medium Low Additional supply voltage 2VDD Approx. VDD Not Needed .sup.&Write speed is compared based on the similar write energy consumption; .sup.#Current-mode read speed and energy are roughly evaluated based on the amount of sensed current in the OFF state and the ON state

    [0229] Embodiments of the NVM device 100 can be configured as a 4T-topology (4T) B&R circuitry 116. For example, the B&R circuitry 116 can include only four transistors. This can be done to reduce area overhead. Some embodiments can include an improved DFF 120 by incorporating an embodiment of the 4T B&R circuitry 116. With embodiments of the 4T B&R circuitry 116, the transistor number of B&R circuitry is lowered, and the backup control can be embedded into the supply voltage modulation with lowered routing cost. The energy-delay product overhead in the normal-mode operation can be below 5%. Embodiments of the DFF 120 with such a 4T B&R circuitry 116 can provide area- and energy-efficient nonvolatile computing for power-gating and energy-harvesting applications.

    [0230] Power gating for idle digital circuits is an effective low-power design approach to reducing the leakage power by shutting down the supply. This can be a useful for both portable and server processors whose design optimizations often get tangled up with the battery life and the thermal limit, respectively. In practice, power-gated DFF states need to be saved in nonvolatile memories.

    [0231] One key optimization for DFF backup and restore operations can be to focus on lowering the consumed energy. Another key optimization for DFFs can be to reduce the area overhead. This can have a significant impact in modern processors where complex pipelining logic and sometimes large register cache files are already adopted based on many flip-flops. Embodiments of the 4T B&R circuitry 116 and/or DFF 120 have a reduced the area overhead. In addition, the backup control is embedded into the supply voltage modulation, which reduces the routing cost since there is no need for an extra backup control signal.

    [0232] While FeFETs can be designed hysteresis-free in I.sub.DV.sub.G to comply with the conventional logic gate switching style, embodiments of the B&R circuitry 116 and/or the DFF 120 can utilize the FeFET 102 characteristics of I.sub.DV.sub.G hysteresis. FIG. 78 shows typical 10 nm n-type FeFET G.sub.DSV.sub.G curves with over 5 orders of magnitudes in the sensed drain-source channel conductions (G.sub.DS) between the bistable ON/OFF nonvolatile states sensed at zero V.sub.G. Applying V.sub.GS beyond the hysteresis edge triggers polarization switching. To ensure a sufficient energy barrier in the hysteresis window for desired noise immunity and retention time, the ferroelectric layer 114 thickness (T.sub.FE) must be carefully tuned. As disclosed herein, this T.sub.FE determines the supply voltage needed in backup operations.

    [0233] FIG. 79 shows an embodiment of the 4T B&R circuitry 116. The 4T B&R circuit 116 can have a first transistor, M.sub.1. M.sub.1 can have an M.sub.1-source, an M.sub.1-gate, and an M.sub.1-drain. The 4T B&R circuit 116 can have a second transistor, M.sub.2. M.sub.2 can have an M.sub.2-source, an M.sub.2-gate, and an M.sub.2-drain. The 4T B&R circuit 116 can have a third transistor, M.sub.3. M.sub.3 can have an M.sub.3-source, an M.sub.3-gate, and an M.sub.3-drain. The 4T B&R circuit 116 can have a fourth transistor, M.sub.4. M.sub.4 can have an M.sub.4-source, an M.sub.4-gate, and an M.sub.4-drain. Any one or combination of the transistors of the 4T B&R circuit 116 can be a metal oxide semiconductor field effect transistor (MOSFET) or a FeFET 102.

    [0234] The 4T B&R circuit 116 can further include a first branch 101 and a second branch 103. The first branch 101 can include M.sub.1, M.sub.3, and GND. The second branch 103 can include M.sub.2, M.sub.4, and GND. Depending on the inputs, either the first branch 101 or the second branch 103 operates as a backup branch or a restore branch. For example, when the first branch 101 operates as a backup branch, the second branch 103 operates as a restore branch. When the first branch 101 operates as a restore branch, the second branch 103 operates as a backup branch. Particular note should be made to the cross-coupled circuit connection between M.sub.3 and the second branch 103 and M.sub.4 and the first branch 101.

    [0235] In some embodiments, the B&R circuit 116 can be connected to a slave latch 118. (See FIG. 80). Can be done to generate a DFF 120. For example, the first branch 101 and the second branch 103 can be connected to a slave latch 118 to form a DFF 120.

    [0236] In at least one embodiment, M.sub.1 and M.sub.2 are MOSFETs. In at least one embodiment, M.sub.3 and M.sub.4 are FeFETs 102. M.sub.1-drain can be connected to M.sub.3-source. M.sub.1-gate can be connected to a restore signal input signal and M.sub.2-gate. M.sub.1-source can be connected to GND. M.sub.2-drain can be connected to M.sub.4-source. M.sub.2-gate can be connected to M.sub.1-gate. M.sub.3-drain can be configured to be connected to a slave latch 118, which can be via the first branch 101. M.sub.3-drain can be connected to M.sub.4-gate, M.sub.4-drain, M.sub.3-gate, and to the second branch 103. M.sub.3-gate can be connected to M.sub.4-gate, M.sub.4-drain, M.sub.3-drain, and to the second branch 103. M.sub.3-source can be connected to M.sub.1-drain. M.sub.4-drain can be configured to be connected to the slave latch 118, which can be via the second branch 103. M.sub.4-drain can be connected to M.sub.3-gate, M.sub.3-drain, M.sub.4-gate, and to the first branch 103. M.sub.4-gate can be connected to M.sub.3-gate, M.sub.3-drain, M.sub.4-drain, and to the first branch 103. M.sub.4-source can be connected to M.sub.2-drain.

    [0237] Referring to FIG. 80, in at least one embodiment, the 4T B&R circuit 116 can be configured as a B&R circuit 116 that may be used to form an embodiment of a DFF 120. In some embodiments an improved DFF 120 can be generated by replacing any one or combination of B&R circuit with an embodiment of the 4T B&R circuit 116 disclosed herein. FIG. 80 shows an embodiment of a DFF 120 having a master latch 122 and a slave latch 118 similar to the ones disclosed in FIG. 6 and a 4T B&R circuit 116.

    [0238] The master latch 122 can have a first master inverter M.sub.INV1, a second master inverter, M.sub.INV2, a third master inverter, M.sub.INV3, and a master transmission gate, M.sub.GATE. The input of M.sub.INV1 can be connected to a data input signal, D. The output of M.sub.INV1 can be connected to the input of M.sub.INV2. The input of M.sub.INV2 can be connected to the output of M.sub.INV1. The output of M.sub.INV2 can be connected to the input of M.sub.INV3. The input of M.sub.INV3 can be connected to the output of M.sub.INV2. The output of M.sub.INV3 can be connected to the input of M.sub.GATE. The input of M.sub.GATE can be connected to the output of M.sub.INV3. The output of M.sub.GATE can be connected to the input of M.sub.INV2 and the output of M.sub.INV1.

    [0239] The slave latch 118 can have a first slave inverter, S.sub.INV1, a second slave inverter, S.sub.INV2, a third slave inverter, S.sub.INV3, and a slave transmission gate, S.sub.GATE. The input of S.sub.INV1 can be connected to the output of M.sub.INV2. The input of S.sub.INV2 can be connected to the output of S.sub.INV1. The output of S.sub.INV2 can be connected to the input of S.sub.INV3 and to a data output Q. The input of S.sub.INV3 can be connected to the output of S.sub.INV2. The output of S.sub.INV3 can be connected to the input of S.sub.GATE. The output of S.sub.GATE can be connected to the input of S.sub.INV2 and the output of S.sub.INV1.

    [0240] A clock driver, CLK can be used to generate an in-phase clock signal, c, and opposite-phase clock signal, cn, for M.sub.INV1, M.sub.GATE, S.sub.INV1, and/or S.sub.GATE. Embodiments of the CLK can include a first clock inverter, CLK.sub.INV1, having an output connected to an input of a second clock inverter, CLK.sub.INV2. CLK.sub.INV1 can be configured to generate cn. CLK.sub.INV2 can be configured to generate c. Each of M.sub.GATE and S.sub.GATE can be a gate circuit for transmitting or blocking the output signal from the master latch 122 or slave latch 118, respectively, in response to the clock signal from CLK.

    [0241] M.sub.3-drain can be connected to the output of S.sub.GATE, the output of S.sub.INV1, and the input of S.sub.INV2. For example, the first branch 101 can be connected to the output of S.sub.GATE, the output of S.sub.INV1, and the input of S.sub.INV2. M.sub.4-drain can be connected to the input of S.sub.INV3, the output of S.sub.INV2, and data output Q. For example, the second branch 103 can be connected to the input of S.sub.INV3, the output of S.sub.INV2, and data output Q.

    [0242] In some embodiments, in the OFF mode, the voltage supply and all inputs can be grounded, and the FeFETs 102 (M.sub.3 and M.sub.4) stay stable with either positive or negative polarization. In the NORMAL mode, the restore can be grounded and the two N-type MOS transistors T.sub.1 and T.sub.2 can be turned OFF, so the DFF 120 operates like a conventional DFF. The normal-mode supply voltage can be adjusted dynamically for the best trade-off between C-to-Q delay and energy. The FeFET device parameters, including T.sub.FE, however, a may not be adjustable for a different hysteresis window width after fabrication. Therefore, in the normal-mode, the supply voltage can be designed to stay safely within the FeFET hysteresis window to avoid unnecessary FeFET polarization switching. In the backup mode, the restore input remains grounded, and the supply voltage is raised beyond the FeFET hysteresis edge, enabling polarization switching if a different DFF state was saved in the FeFETs 102 (M.sub.3 and M.sub.4). FIG. 81 shows an embodiment of the DFF 120 in a backup operation, with the DFF 120 state Q being high in voltage as an example. For M.sub.3, a high gate-source voltage provides sufficient positive voltage across the ferroelectric layer, ensuring that M.sub.3 stays at or switches to the positive polarization state. For M.sub.4, an opposite voltage across the gate and source makes it enter or stay at the negative polarization state. Note that M.sub.1 and M.sub.2 are turned OFF, so the initial charge at nodes X and Y does not affect the final polarization states. After the polarization settles, the DFF state is saved, and the supply could be safely turned off for power saving, or remain high as needed if standby or continuous computation is preferred.

    [0243] FIG. 82 shows an embodiment of the DFF 120 in a restore operation. In the restore mode, the clock input C remains low to isolate the slave latch 118 from the master latch 122, and the restore control signal stays high to turn on both M.sub.1 and M.sub.2 before the supply ramps up. As shown in FIG. 82, the branch with positive FeFET polarization clamps QN to ground tightly but detaches Q from the ground. As the supply recovers, the latching structure in the slave latch 118 further enhances such a trend and finally leads to full settling-down.

    [0244] Once T.sub.FE is fixed, the DFF 120 has the minimum required V.sub.DD to carry out successful polarization switching in the backup mode, and the maximum V.sub.DD to avoid polarization switching in the normal mode. These two V.sub.DD levels are similar in magnitude due to the steep switching hysteresis edges.

    [0245] Conventional DFF devices need four extra transistors to isolate the B&R circuitry and the slave latch, so the supply voltage in the normal mode can be higher, as compared to embodiments of the DFF 120 disclosed herein. For fair comparison, the same FeFETs were used in both an embodiment of the DFF 120 and a conventional DFF to conduct an analysis. Therefore, when the normal-mode supply voltage is lower than that in the backup mode, both the conventional DFF and embodiments of the DFF 120 raise the supply voltage accordingly for backups. As will be shown, embodiments of the DFF 120 can re-use the supply voltage modulation unit without introducing other overheads.

    [0246] FIG. 83 shows an example of transient simulation waveform snapshots, in which all operation modes are shown. FIGS. 84-87 show performance evaluations for embodiments of the DFF 120. FIG. 84 shows V.sub.DD v. backup time for embodiments of the DFF 120. FIG. 85 shows V.sub.DD v. backup energy for embodiments of the DFF 120. FIG. 86 shows V.sub.DD v. restore energy for embodiments of the DFF 120. FIG. 87 shows clock to Q energy v. clock to Q delay for embodiments of the DFF 120. The intrinsic DFF restore time is lower than 100 ps for all design process corners. Thus, the actual DFF restore time is practically almost the same as the supply voltage recovery time due to the relatively large capacitive load in the supply network. The restore energy has very little dependence on T.sub.FE, as almost all energy is consumed to charge the capacitance at each internal node and a restore operation does not trigger polarization switching. For backup performance, scenarios when the polarization state was flipped were considered. Two observations are noted: (i) when a larger T.sub.FE is adopted, the wider ferroelectric hysteresis window and higher energy barrier lead to more switching time and energy for the backup operation; (ii) while reducing the normal-mode supply voltage is widely used for lower C-to-Q sample-and-hold energy in the normal mode, it also leads to more backup time and energy due to more supply voltage increase to reach the backup mode supply voltage level.

    [0247] FIG. 88 summarizes the backup time versus backup energy for the second observation, wherein a comparison of the performance of backup time and energy between an embodiment of the DFF 120 conventional DFF devices is made. While both designs have ultra-fast backup speed in ns and ultra-low backup energy in fJ, some differences are observed. The conventional DFF design with a fixed T.sub.FE has a relatively flat backup time because its backup operation starts with the supply voltage raised to the same level when the dedicated backup control signal is triggered. In comparison, the backup operation is faster in the inventive DFF 120 due to direct contact between the slave latch and the FeFETs without any isolation transistors used in the conventional DFF design.

    [0248] FIG. 89 further provides detailed energy-delay product (EDP) overhead for en embodiment of the DFF 120, in comparison with the conventional DFF devices. While the inventive DFF 120 pays slightly higher EDP for much lower area overhead (50%), this EDP overhead is no more than 5% for both designs. Table 5 summarizes the comparisons of metrics of an embodiment of the DFF120 with conventional DFF devices.

    TABLE-US-00005 TABLE 5 Metric Comparisons of an Embodiment of the DFF 120 with Conventional DFF Devices Conventional Conventional Embodiment of the DFF DFF DFF 120 Number of B&R 2 or 4 8 4 transistors Normal-mode EDP 30%-50% <5% <5% overhead External B&R control Not needed Not needed Needed signals Backup and restore: fj, ns fj, ns fj, ns energy, speed Immunity to variation Medium High High and noise * Restore signal needed; Backup control is embedded into the supply signal.

    [0249] Embodiments of the DFF 120 can reduce the area overhead of DFF by 50%, through harnessing the feature of logic-memory fusion in FeFETs. Embodiments of the DFF 120 consumes only fJ energy to accomplish the nonvolatile backup and restore operations within ns, with an energy-delay performance overhead below 5%.

    [0250] It should be understood that modifications to the embodiments disclosed herein can be made to meet a particular set of design criteria. For instance, the number of or configuration of MOSFETs, FeFETs 102, DFFs 120, slave latches 118, master latches 122, memory cells 124, eyepieces 108, and/or other components or parameters may be used to meet a particular objective. In addition, any of the embodiments of the NVM devices 100 (e.g., B&R circuit 116, 4T B&R circuit 116, clave latch 118, master latch 122, DFF 120, memory cell 124, etc.) disclosed herein can be connected to other embodiments of the NVM devices 100 (e.g., B&R circuit 116, 4T B&R circuit 116, clave latch 118, master latch 122, DFF 120, memory cell 124, etc.) to generate a device.

    [0251] It will be apparent to those skilled in the art that numerous modifications and variations of the described examples and embodiments are possible in light of the above teachings of the disclosure. The disclosed examples and embodiments are presented for purposes of illustration only. Other alternative embodiments may include some or all of the features of the various embodiments disclosed herein. For instance, it is contemplated that a particular feature described, either individually or as part of an embodiment, can be combined with other individually described features, or parts of other embodiments. The elements and acts of the various embodiments described herein can therefore be combined to provide further embodiments.

    [0252] Therefore, it is the intent to cover all such modifications and alternative embodiments as may come within the true scope of this invention, which is to be given the full breadth thereof. Additionally, the disclosure of a range of values is a disclosure of every numerical value within that range, including the end points. Thus, while certain exemplary embodiments of apparatuses and methods of making and using the same have been discussed and illustrated herein, it is to be distinctly understood that the invention is not limited thereto but may be otherwise variously embodied and practiced within the scope of the following claims.

    [0253] It should also be appreciated that some components, features, and/or configurations may be described in connection with only one particular embodiment, but these same components, features, and/or configurations can be applied or used with many other embodiments and should be considered applicable to the other embodiments, unless stated otherwise or unless such a component, feature, and/or configuration is technically impossible to use with the other embodiment. Thus, the components, features, and/or configurations of the various embodiments can be combined together in any manner and such combinations are expressly contemplated and disclosed by this statement. Thus, while certain exemplary embodiments of the NVM devices 100 have been shown and described above, it is to be distinctly understood that the invention is not limited thereto but may be otherwise variously embodied and practiced within the scope of the following claims.