Apparatus for reducing wandering spurs in a fractional-N frequency synthesizer

Abstract

The present invention provides a fractional-N frequency synthesizer comprising a divider controller comprising a multistage noise Shaping (MASH) digital delta-sigma modulator comprising L stages, wherein the Lth stage is configured to receive as an input a high amplitude dither signal.

Claims

1. A fractional-N frequency synthesizer comprising a divider controller comprising a multistage noise shaping (MASH) digital delta-sigma modulator comprising L stages, wherein the Lth stage is configured to receive as an input the sum of the output of the preceding stage and a high amplitude dither signal, wherein the high amplitude dither signal comprises an integer dither signal which is uniformly distributed in the range [0, 1, . . . , M1], wherein M corresponds to the modulus of the MASH digital delta-sigma modulator.

2. The fractional-N frequency synthesizer of claim 1, wherein the MASH digital delta-sigma modulator comprises a MASH digital delta-sigma modulator with additive first-order dither.

3. The fractional-N frequency synthesizer of claim 2, wherein the MASH digital delta-sigma modulator comprises a MASH 1-1-1 architecture.

4. The fractional-N frequency synthesizer of claim 1, wherein each of the L stages comprises a first order error feedback modulator (EFM).

5. A fractional-N frequency synthesizer comprising a divider controller comprising a multistage noise shaping (MASH) digital delta-sigma modulator comprising L stages, wherein the Lth stage is configured to receive as an input the sum of the output of a preceding stage and a high amplitude dither signal, wherein the high amplitude dither signal comprises a dither signal which is uniformly distributed in the range [0, 1, . . . , 2.sup.K1]*M/2.sup.K, wherein M=2.sup.B, and wherein M corresponds to the modulus of the MASH digital delta-sigma modulator, B corresponds to the number of bits, and K comprises an integer between 1 and 6.

6. The fractional-N frequency synthesizer of claim 5, wherein the MASH digital delta-sigma modulator comprises a MASH digital delta-sigma modulator with additive first-order dither.

7. The fractional-N frequency synthesizer of claim 6, wherein the MASH digital delta-sigma modulator comprises a MASH 1-1-1 architecture.

8. The fractional-N frequency synthesizer of claim 5, wherein each of the L stages comprises a first order error feedback modulator (EFM).

9. A fractional-N frequency synthesizer comprising a divider controller comprising a multistage noise shaping (MASH) digital delta-sigma modulator comprising L stages, wherein the Lth stage is configured to receive as an input the sum of the output of a preceding stage and a high amplitude dither signal, wherein the MASH digital delta-sigma modulator comprises a MASH digital delta-sigma modulator with additive first-order dither, wherein the MASH digital delta-sigma modulator comprises a MASH 1-1-1 architecture, wherein the MASH 1-1-1 architecture with additive first-order dither comprises a first stage, a second stage and a third stage, and wherein the third stage of the MASH architecture is configured to receive as an input the sum of the output of the preceding stage and the high amplitude dither signal.

10. The fractional-N frequency synthesizer of claim 9, wherein the high amplitude dither signal is filtered in accordance with the equation:
Y(z)=(1/M)*[X(z)+(1z.sup.1)D.sub.1(z)+(1z.sup.1).sup.2D.sub.2(z)]+(1z.sup.1).sup.3E.sub.q3(z), where Y corresponds to the z transform of an output signal of the MASH 1-1-1 architecture; X corresponds to the z transform of an input signal to the MASH 1-1-1 architecture; D.sub.1 corresponds to the z transform of an additive first order dither signal; D.sub.2 corresponds to the z transform of the high amplitude dither signal; and E.sub.q3 corresponds to the z transform of a quantization error of the third stage of the MASH 1-1-1 architecture.

11. The fractional-N frequency synthesizer of claim 9, wherein the second stage of the MASH architecture is configured to receive as an input a binary dither signal.

12. The fractional-N frequency synthesizer of claim 9, wherein each of the L stages comprises a first order error feedback modulator (EFM).

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The patent or application file contains at least one drawing executed in color. Copies of this patent or patent application publication with color drawing(s) will be provided by the Office upon request and payment of the necessary fee. The present disclosure will be more clearly understood from the following description of an embodiment thereof, given by way of example only, with reference to the accompanying drawings, in which:

(2) FIG. 1 shows a block diagram of a conventional fractional-N frequency synthesizer;

(3) FIG. 2 shows a block diagram of a conventional divider controller based on a Multi stAge noise SHaping (MASH) digital delta-sigma modulator with shaped additive dither;

(4) FIG. 3 shows a block diagram of a conventional additive LSB-dithered MASH 1-1-1 divider controller with first-order shaped additive dither;

(5) FIGS. 4A and 4B shows typical manifestations of wandering spurs in the frequency domain, where FIG. 4A is a VCO spectrogram and FIG. 4B is an output phase noise spectrogram (with logarithmic frequency axis) for a fractional-N frequency synthesizer with a MASH 1-1-1 divider controller architecture;

(6) FIG. 5 shows a spectrogram of the output of the fractional-N synthesizer of FIG. 1 with the conventional dithered MASH 1-1-1 divider controller of FIG. 3 and a linear charge pump;

(7) FIG. 6 shows a spectrogram of the output of a fractional-N synthesizer of FIG. 1 with the conventional dithered MASH 1-1-1 divider controller of FIG. 3 and a mismatched charge pump;

(8) FIG. 7 shows a block diagram of an embodiment of a high amplitude dithered MASH 1-1-1 divider controller in accordance with the present disclosure;

(9) FIG. 8 shows the simulated VCO input signal in the fractional-N frequency synthesizer of FIG. 1 incorporating the conventional MASH 1-1-1 divider controller of FIG. 3;

(10) FIG. 9 shows the simulated VCO input signal in a fractional-N frequency synthesizer of FIG. 1 incorporating the high amplitude dithered MASH 1-1-1 divider controller of FIG. 7;

(11) FIG. 10 shows a spectrogram of the output of a synthesizer comprising the high amplitude dithered divider controller of FIG. 7 and a linear loop; and

(12) FIG. 11 shows a spectrogram of the output of a synthesizer comprising the high amplitude dithered divider controller of FIG. 7 and a nonlinear loop.

DETAILED DESCRIPTION

(13) The present disclosure provides a fractional-N frequency synthesizer which reduces the effect of wandering spurs exhibited by the synthesizer when operating with a higher resolution DDSM-based divider controller. The present disclosure will now be described in conjunction with FIG. 7 onwards.

(14) The inventors of the present disclosure determined that it is the interaction between the signal injected by a DDSM-based divider controller and a synthesizer's phase-locked loop which causes wandering spurs.

(15) In accordance with the present disclosure, the magnitudes of the wandering spurs introduced by a DDSM into a fractional-N frequency synthesizer are reduced by adding a high amplitude random dither signal at the input to the last stage of the DDSM.

(16) FIG. 7 shows one embodiment of the present disclosure where the DDSM incorporated into the synthesizer comprises a modified MASH 1-1-1 divider controller. The MASH 1-1-1 divider controller comprises a cascade of three first-order Error Feedback Modulators (EFM). The MASH 1-1-1 is known to suffer from limit cycles. Therefore a binary dither signal, denoted d.sub.1, is added to the input of the second stage to prevent limit cycle behavior.

(17) The MASH 1-1-1 divider controller is further modified by adding a high-amplitude dither to the last stage of the MASH architecture. This involves adding a full range uniform dither signal to the third stage of the DDSM. This dither signal is second-order high passed filtered when it appears at the output. In the z domain,
Y(z)=(1/M)*[X(z)+(1z.sup.1)D.sub.1(z)+(1z.sup.1).sup.2D.sub.2(z)]+(1z.sup.1).sup.3E.sub.q3(z),
where Y, X, D.sub.1, D.sub.2 and E.sub.q3 are the z transforms of y, x, the dither signals d.sub.1 and d.sub.2, and the quantization error of the third EFM stage in FIG. 3.

(18) In one embodiment, the dither signal d.sub.1 is uniformly distributed in [0, 1] and the high amplitude dither signal d.sub.2 is uniformly distributed in the range [0, 1, . . . , M1].

(19) In another embodiment, the high amplitude dither signal is uniformly distributed in the range [0, 1, . . . , 2.sup.K1]*M/2.sup.K, where M=2.sup.B, B is the number of bits and K is an integer between 1 and 6.

(20) The wandering spur phenomenon is caused by a chirp signal which is produced at the input to the VCO. This chirp has its origin in the DDSM. By adding high amplitude dither to the last stage of the MASH divider controller, it swamps the chirp signal and eliminates the wandering spur. This can be seen by comparing FIG. 8, which shows the VCO signal in a fractional-N frequency synthesizer of FIG. 1 incorporating the conventional MASH 1-1-1 divider controller shown in FIG. 3, with the VCO signal produced in the frequency synthesizer of FIG. 1 which incorporates the high amplitude dithered MASH 1-1-1 divider controller of FIG. 7, as shown in FIG. 9. The chirp signal is evident in FIG. 8 but FIG. 9 is more noiselike.

(21) FIG. 10 shows a spectrogram of the output of a fractional-N frequency synthesizer with an ideal linear loop in which the divider controller comprises the high amplitude dithered MASH 1-1-1 of FIG. 7 (with x=524288, M=2.sup.20). By comparison with FIG. 5, it can be seen that this results in the elimination of wandering spurs from the output of the frequency synthesizer.

(22) FIG. 11 shows a spectrogram of the output of a fractional-N frequency synthesizer in which the divider controller comprises the high amplitude dithered MASH 1-1-1 of FIG. 7 (with x=524288, M=2.sup.20) with an 8% static charge pump current mismatch. As was the case with FIG. 10, no wandering spur is present in the spectrogram, by contrast with FIG. 6.

(23) It can be seen that due to the incorporation of the modified MASH 1-1-1 divider controller into the frequency synthesizer, these spectrograms do not exhibit any wandering spurs. Thus, it will be appreciated that the fractional-N frequency synthesizer of the present disclosure provides a divider controller signal which is less prone to produce wandering spurs than a frequency synthesizer which uses a conventional dithered digital delta-sigma modulator. Through the mitigation of wandering spurs, it enables the frequency synthesizer to generate cleaner carriers for a range of applications including communications, radar and instrumentation.

(24) In the specification the terms comprise, comprises, comprised and comprising or any variation thereof and the terms include, includes, included and including or any variation thereof are considered to be totally interchangeable and they should all be afforded the widest possible interpretation and vice versa.

(25) The present disclosure is not limited to the embodiments hereinbefore described but may be varied in both construction and detail.