Multi-gain transconductance amplifier

Abstract

A multiple-gain transconductance amplifier circuit is presented. It is developed by utilizing programmable gain source-coupling differential pair output stage forming multiple-gain transconductance amplifier outputs. A reconfigurable n.sup.th-order filter based on a multi-gain transconductance amplifier where the multi-gain transconductance amplifier includes a linear voltage-to-current converter and a programmable current-folding output stage was implemented. The filter achieves independent programmability while still using a single active device per pole. Further, the proposed multiple-gain transconductance amplifier can be employed to design poly phase filters and transconductance amplifier cell for an amplifier-based low-dropout regulator.

Claims

1. A multiple-gain independently programmable transconductance amplifier, comprising: a voltage-to-current conversion circuit configured to receive a differential input voltage signal at a first input and provide at an output node a first single-ended current signal that is linearly proportional to the differential input voltage signal; and a multiple-gain current-folding output stage comprising a plurality of differential pairs, wherein each differential pair includes a first transistor and a second transistor, a first gate of the first transistor being directly connected to the output node, and a second gate of the second transistor being directly connected to a bias voltage source, the first transistor and the second transistor of each differential pair being source coupled and in series with one adjustable current mirror supply, at least one of the plurality of differential pairs is configured to program a different gain of the output stage by varying a bias current of a corresponding adjustable current mirror supply.

2. The multiple-gain independently programmable transconductance amplifier of claim 1, wherein the voltage-to-current conversion circuit further comprises: a differential input voltage source; a first differential pair that includes a third transistor and a fourth transistor, gates of the third transistor and the fourth transistor respectively connected to the differential input voltage source, sources of the third transistor and the fourth transistor being connected to a current mirror supply, respective drains of the third transistor and the fourth transistor being connected to a diode-connected load, wherein one of the drains outputs the first single-ended current signal; and a second differential pair that includes a fifth transistor and a sixth transistor, sources of the second differential pair being connected to and biased by a variable voltage source, gates of the second differential pair being connected to respective sources of the first differential pair, and respective drains of the second differential pair being cross-coupled to the drains of the first differential pair.

3. The multiple-gain independently programmable transconductance amplifier of claim 2, wherein programmable currents of the output stages of the multiple-gain independently programmable transconductance amplifier are set based on a first bias current of a first differential pair of the multiple-gain current-folding output stage, a second bias current of a second differential pair of the multiple-gain current-folding output stage, a transconductance of the input stage, a positive input voltage, and a negative input voltage.

4. A reconfigurable high-order integrated circuit filter, comprising: a ground node; a plurality of multi-gain transconductance amplifiers wherein each multi-gain transconductance amplifier having a voltage-to-current conversion circuit configured to receive a differential input voltage signal at a first input and provide at an output node a first single-ended current signal that is linearly proportional to the differential input voltage signal; and a multiple-gain current-folding output stage comprising a plurality of differential pairs, wherein each differential pair includes a first transistor and a second transistor, a first gate of the first transistor being directly connected to the output node, and a second gate of the second transistor being directly connected to a bias voltage source, the first transistor and the second transistor of each differential pair being source coupled and in series with one adjustable current mirror supply, at least one of the plurality of differential pairs is configured to program a different gain of the output stage by varying a bias current of a corresponding adjustable current mirror supply, and the plurality of multi-gain transconductance amplifiers including, a first stage multi-gain transconductance amplifier having a single non-inverting input, a single inverting input coupled to the ground node, and at least three outputs; a final stage multi-gain transconductance amplifier having a single non-inverting input, a single inverting input coupled to the ground node and at least two outputs; and at least one intermediate stage multi-gain transconductance amplifier disposed in the cascade between the first multi-gain transconductance amplifier and the last multi-gain transconductance amplifier having at least one input, and at least three outputs, a first output of the at least three outputs establishing a feedback connection to the non-inverting input of the first multi-gain transconductance amplifier, a second output of the at least three outputs feeding in an output-to-input manner through the cascade, a third output of the at least three outputs establishing a feedforward connection to form an accumulative feedforward signal, a second output of the at least two outputs of the last multi-gain transconductance amplifier of the cascade connected to the feedforward connection adding to the accumulative feedforward signal; and a plurality of capacitors, each capacitor connected between the ground node and a second of the at least three outputs of the intermediate stage multi-gain transconductance amplifier.

5. The reconfigurable high-order integrated circuit filter of claim 4, wherein the voltage-to-current conversion circuit of the multi-gain transconductance amplifier further comprises: a differential input voltage source; a first differential pair that includes a third transistor and a fourth transistor, gates of the third transistor and the fourth transistor respectively connected to the differential input voltage source, sources of the third transistor and the fourth transistor being connected to a current mirror supply, respective drains of the third transistor and the fourth transistor being connected to a diode-connected load, wherein one of the drains outputs the first single-ended current signal; and a second differential pair that includes a fifth transistor and a sixth transistor, sources of the second differential pair being connected to and biased by a variable voltage source, gates of the second differential pair being connected to respective sources of the first differential pair, and respective drains of the second differential pair being cross-coupled to the drains of the first differential pair.

6. The reconfigurable high-order integrated circuit filter of claim 5, wherein programmable currents of the output stages of each multiple-gain transconductance amplifier are set based on a first bias current of a first differential pair of the multiple-gain current-folding output stage, a second bias current of a second differential pair of the multiple-gain current-folding output stage, the transconductance of the input stage, a positive input voltage, and a negative input voltage.

7. The reconfigurable high-order integrated circuit filter of claim 6, wherein the filter is configured to achieve independent programmability by using source-coupling differential pair topology with multiple-gain transconductance amplifier outputs.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) A more complete appreciation of the disclosure and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein:

(2) FIG. 1A shows an exemplary multi-output transconductance amplifier;

(3) FIG. 1B shows an exemplary multi-gain transconductance amplifier;

(4) FIG. 2 is an exemplary circuit schematic of a disclosed multi-gain independently programmable transconductance amplifier;

(5) FIG. 3 is an exemplary circuit schematic of a multi-outputs transconductance amplifiers with dependent gains;

(6) FIG. 4 shows DC responses of the disclosed multi-gain independently programmable transconductance amplifier with independent gain tunings;

(7) FIG. 5 shows AC responses of the disclosed multi-gain independently programmable transconductance amplifier with independent tunings;

(8) FIG. 6 shows a current-mode poly-phase filter according to an aspect of the disclosure;

(9) FIG. 7 shows a poly-phase filter according to an aspect of the disclosure;

(10) FIG. 8 is an embodiment of a filter topology based on multi-gain independently programmable transconductance amplifiers;

(11) FIG. 9 shows low-pass, high-pass and band-pass responses of the fourth-order filter;

(12) FIG. 10 shows Butterworth low-pass responses of the fourth-order filter demonstrating programmable pole frequency; and

(13) FIG. 11 shows Chebyshev low-pass responses of the fourth-order filter.

DETAILED DESCRIPTION

(14) In the drawings, like reference numerals designate identical or corresponding parts throughout the several views. Further, as used herein, the words a, an and the like generally carry a meaning of one or more, unless stated otherwise. The drawings are generally drawn to scale unless specified otherwise or illustrating schematic structures or flowcharts.

(15) Furthermore, the terms approximately, about, and similar terms generally refer to ranges that include the identified value within a margin of 20%, 10%, or 5%, and any values in between.

(16) The following is an assessment of publications and is intended not only as a review of related approach, but also on the inventor's recognition of attributes and limitation of these approaches, which set a baseline for the novel embodiments described herein.

(17) In an example, realizations of transconductance amplifier are available with single output and multi-outputs structures. In an example, the additional outputs are equal in magnitude but may be different in signs as shown in FIG. 1A. For example, the outputs can have same transconductance gain.

(18) Note that the proposed multi-gain transconductance amplifier can have a different gain for each output current, such as g.sub.m1, g.sub.m2, and g.sub.mn shown in FIG. 1B.

(19) A multi-output transconductance amplifier is often converted to a multi-gain transconductance amplifier counterpart through replacing normal output stage current mirrors with tunable current mirrors. Examples include Pankiewicz, B., Wojcikowski, M., Szczepanski, S., and Sun, Y. (A field programmable analog array for CMOS continuous time OTA-C filter applications. IEEE J. Solid-State Circuits, 37(2), 125-136, (February 2002)incorporated herein by reference) and Ramirez-Angulo, J., and Sanchez-Sinencio, E., (Current-mode continuous-time filters: Two design approaches. IEEE Trans. Cir. Syst. II. 39(6), 337-341, (June 1992)incorporated herein by reference). The digitally tunable current mirror cells proposed in Pankiewicz, B., Wojcikowski, M., Szczepanski, S., and Sun, Y., (A field programmable analog array for CMOS continuous time OTA-C filter applications, IEEE J. Solid-State Circuits, 37(2), 125-136, (February 2002)incorporated herein by reference) are power as well as area inefficient as the number of cell increases by 2 for each bit of tuning. For example, the first bit uses 2 output stages, 2.sup.nd bit uses 4 output stages, 3.sup.rd bit uses 8 output stages and so on. Therefore, the 6.sup.th bit uses 64 output stages. Whereas the analog programmability used in Ramirez-Angulo, J., and Sanchez-Sinencio, E., Current-mode continuous-time filters: Two design approaches. IEEE Trans. Cir. Syst. II. 39(6), 337-341, (June 1992)incorporated herein by reference) suffers from limited linearity. Also, that technique is power inefficient because the core transconductance amplifiers is used to employ several current mirrors for providing multi-output currents then each individual output can be applied to a separate programmable current mirror cell.

(20) FIG. 2 shows an exemplary embodiment of a disclosed multi-gain independently programmable transconductance amplifier. In an embodiment, the input stage employs a linear transconductance amplifier circuit whose output current is applied to current folding output stages. Multi-gain current folding output stages are utilized to obtain independently programmable transconductance amplifier outputs. The transistors M1-M8 (the core circuit M1-M6 was presented in S. C. Huang, M. Ismail, Linear Tunable COMFET Transconductor, Electronics Letters, vol. 29, no. 5, pp. 459-461, March 1993incorporated herein by reference), for example, are used to implement a linear tunable transconductor to convert differential input voltages into a single-ended tunable current i.sub.x. Note that the proposed approach can be employed with any other transconductor. A current mirror circuit 202 is implemented by the transistors M7 and M8 to copy the current into M7 to M8, where transistor M7 is a diode connected transistor. A first differential pair 204 is implemented by the transistors M5-M6. A second differential pair 206 is implemented by the transistors M1-M2. The transistors M3 and M4 are diode connected transistor and function as load transistors. The transistors M1-M6 are matched transistors, thus, the transistors M1-M6 have the same length and width. Gates of the first differential pair are connected to a differential input voltage V.sub.p and V.sub.n. The sources of M5 and M6 are connected to the drains of M3 and M4, respectively. The sources of M5 and M6 are further connected to the gates of M1 and M2, respectively. The drains of M5 and M6 are connected to the drains of the M7 and M8, respectively. The drains of M1 and M2 are cross-coupled, and connected to the drain of M6 and M5, respectively. The transistors M1 and M2 are source-coupled, and connected to a tunable voltage V.sub.b.

(21) The differential current of the transconductor is given by
I.sub.1I.sub.2=i.sub.x=K.sub.1(V.sub.bV.sub.ss)(V.sub.pV.sub.n)(1)

(22) wherein I.sub.1 is the current through the drains of the transistors M2 and M5, and I.sub.2 is the current through the drains of the transistors M1 and M6, K.sub.1=0.5.sub.1C.sub.ox1W.sub.1/L.sub.1 (for M1-M6) with .sub.1 as the surface carrier mobility, C.sub.ox1 is the gate oxide capacitance per unit area, and W.sub.1 and L.sub.1 are the width and length of the channel for the matched transistors M1-M6. The voltage Vb is a DC biasing voltage, Vss is the negative supply voltage, Vp is the positive input voltage and Vn is the negative input voltage. The equation shows that the current i.sub.x and the differential input voltage have a linear relation. Therefore, the input stage transconductor amplifier has a linear transconductance (g.sub.m) given by g.sub.m=K.sub.1(V.sub.bV.sub.ss). g.sub.m is the linear transconductance and can be tuned by V.sub.b.

(23) The output stage is implemented by the transistors M9-M22. Another current mirror 208 is implemented by the transistors M14 and M15 to generate a current I.sub.T1, wherein the transistor M14 is a diode connected transistor. The current mirror formed by M9-M11 is used to copy the current of M9 (I.sub.T1) into M10 and M11, wherein the transistor M9 is a diode connected transistor.

(24) A third different pair 210 is implemented by the transistors M12 and M13. The transistors M10-M11 functions as loads for the transistors M12 and M13. The current folding output stage is used to replace the normal current mirroring output stage and hence achieves robust linearity. The linear current i.sub.x, which is generated by the input stage transconductor, is conveyed to the output port Z.sub.n1 by source coupling M12 and M13. Since this coupled pair is biased with a constant tail current I.sub.T1, the drain current changes in M12 and M13 would be equal but with opposite signs, resulting in a negative type current amplifier with unity gain.

(25) Another pair differential pair 214 that consists of M19-M20 is connected parallel with M12-M13 to provide two additional current outputs. Another current mirror 212 is implemented by the transistors M21 and M22 to generate a current I.sub.T2, wherein the transistor M22 is a diode connected transistor. The transistors M16-M17, forming a current mirror, are used to copy the current of M18 (I.sub.T2) into M16 and M17, wherein the transistor M18 is a diode connected transistor. When the differential pair including M19 and M20 is biased with the different tail current I.sub.T2, the large signal current relationship of the output stage is given by:

(26) $\begin{array}{cc}{I}_{\mathrm{Zp}2}=I_{\mathrm{Zn}2}=\sqrt{\frac{I_{T2}}{I_{T1}}}\frac{\sqrt{1-\left(\frac{K_2{V}_d^2}{4I_{T2}}\right)}}{\sqrt{1-\left(\frac{K_2{V}_d^2}{4I_{T1}}\right)}}{I}_x& \left(2\right)\end{array}$
where I.sub.T1 is a first bias current of the differential pair 208 of the multiple-gain current-folding output stage, I.sub.T2 is a second bias current of the differential pair 212 of the multiple-gain current-folding output stage, V.sub.d=V.sub.cV.sub.g12 (i.e. the differential voltage of the two source coupled pairs 210), V.sub.c is a bias DC voltage for the transistors M13 and M19, V.sub.g12 is a gate voltage of the transistor M12, K.sub.2=0.5.sub.2C.sub.ox2 W.sub.2/L.sub.2 for the matched transistor pairs M12-M13 and M19-M20 with .sub.2 as the surface carrier mobility, C.sub.ox2 is the gate oxide capacitance per unit area, and W.sub.2 and L.sub.2 are the width and length of the channel. Thus, for small signals V.sub.d<<2[min. (I.sub.T1,I.sub.T2)/K.sub.2].sup.1/2, the relationship simplifies to:
i.sub.Zp2=i.sub.Zn2=(I.sub.T2/I.sub.T1).sup.1/2i.sub.x(3)
This would result in the overall programmable gains of:

(27) $\begin{array}{cc}{i}_{\mathrm{Zp}2}=i_{\mathrm{Zn}2}={\left(\frac{I_{T2}}{I_{T1}}\right)}^{\frac{1}{2}}{g}_m\left(V_p-V_n\right)& \left(4\right)\end{array}$
wherein g.sub.m is the transconductance of the linear transconductor forming the input stage given before by g.sub.m=K.sub.1(V.sub.bV.sub.ss).

(28) Thus, tail currents, such as I.sub.T1 and I.sub.T2, can be adjusted to program the gain of new outputs. Extra output currents with different gains are obtained by adding more output stages with each stage providing both positive and negative signals. As will be seen below, the original output current i.sub.Zn1=i.sub.x=g.sub.mv.sub.d can be utilized to realize output with gain g.sub.r's while the new outputs can be used to provide independent gains of FIG. 8.

(29) Another advantage of adopting the proposed output stages is that the input stage transconductance amplifiers can be used to provide an output. In such a case a single current mirror i.e. M7-M8 is sufficient to generate the linearized output current (i.sub.x), as shown in FIG. 2. On the other hand, several current mirrors can be used to realize the first output current. Consequently, several other current mirrors would be needed to generate copies of this output current. In order to demonstrate this point, a three-output transconductance amplifier whose core circuit (M1-M6) obtained from one reference, S. C. Huang, M. Ismail, Linear Tunable COMFET Transconductor, Electronics Letters, vol. 29, no. 5, pp. 459-461, March 1993.incorporated herein by reference) is showed in FIG. 3. FIG. 3 is a multi-output transconductance amplifier with dependent gains. It includes an input stage that employs linear transconductance amplifiers circuit whose output current is applied to the normal current mirror output stages. Three current mirrors (M7-M8, M9-M12, and M10-M11) are used to generate the first output current (i.sub.ZP1). Also, more output current copies are obtained by employing additional normal (M13-M14) and/or cross coupled (M15 through M20) current mirrors. The transistors M15-M20 are used to invert the direction of the output current. Hence, a total number of transistors for the proposed design of FIG. 2 is twenty-two, while a total number of transistors for the design in FIG. 3 is twenty. Therefore, the disclosed design achieved a programmability feature at the cost of just two additional transistors unlike the other available solutions.

(30) In an example, the proposed transconductance amplifiers was simulated and optimized for 0.18 m CMOS technology using supply voltages of 0.9V. The independent tuning capability of the circuit shown in FIG. 2 is demonstrated in FIG. 4 by plotting the DC response for output currents I.sub.Zn1 and I.sub.Zn2 for several values of I.sub.T1 and I.sub.T2. FIG. 4 shows the exemplary DC responses of the disclosed multi-gain independently programmable transconductance amplifier with independent gain tunings. For example, it can be seen that when I.sub.T1 and I.sub.T2 are equal the output currents I.sub.zn1 and I.sub.zn2 are equal as well. When I.sub.T2 is decreased by a factor of 4, the output current I.sub.zn2 decreases by a factor of 2.

(31) FIG. 5 shows exemplary AC responses of the disclosed multi-gain independently programmable transconductance amplifier with independent tunings. It can be seen that the 3 dB bandwidth remains constant and above 100 MHz for various gain settings of the tail currents of I.sub.T1 and I.sub.T2.

(32) In order to demonstrate the advantages of the proposed multi-gain g.sub.m, two examples are given. FIG. 6 shows a current-mode polyphase filter based on single ended g.sub.m.

(33) It can be shown that the filter exhibits the following transfer functions.

(34) $\begin{array}{cc}\frac{I_{\mathrm{oI}}}{I_I}=\frac{I_{\mathrm{oQ}}}{I_Q}=\frac{\frac{g_{\mathrm{mg}}}{C}}{s-j\frac{g_{\mathrm{mc}}}{C}+\frac{g_{\mathrm{mo}}}{C}}& \left(5\right)\end{array}$

(35) The corresponding filter based on the proposed multi-gain g.sub.m is shown in FIG. 7. Although the filter uses two gm's, the filter has the same transfer functions given by Eq.(5). The filters center frequency, pole frequency, and gain are given by g.sub.mc/C, g.sub.mo/C, and g.sub.mg/g.sub.mo, respectively.

(36) It is clear that if the filter of FIG. 7 was realized with traditional multi-output g.sub.m's then g.sub.mc, g.sub.mg, and g.sub.mo would be equal. Thus, programmability features would be lost as the filter would have undesired features of a unity gain and equal pole and center frequencies.

(37) The second example focuses on the realization of a reconfigurable nth-order filter (RNOF). A RNOF is a versatile filter that can be flexibly used to realize any nth-order filter function without hardware changes and, hence, serves wide range of applications. Such filters are core parts of systems utilizing field reconfigurable analog arrays (FRAAs), which are described in references such as Pankiewicz, B., Wojcikowski, M., Szczepanski, S., and Sun, Y., (A field programmable analog array for CMOS continuous time OTA-C filter applications. IEEE J. Solid-State Circuits, 37(2), 125-136, (February 2002)incorporated herein by reference).

(38) Power consumption and independent programmability are two main criteria for FRAAs. Therefore, RNOF are expected to both adopt a minimum number of active devices and maintain independent programmability characteristics. RNOFs can be operated at different frequencies, (e.g. accommodating different bandwidths), change the filter type (e.g. low-pass to band-pass), and modify the overall response (e.g. Butterworth to Chebyshev) According to this disclosure, the disclosed programmable multi-gains transconductance amplifier can be efficient in the number of active devices used as well as maintain independent tuning characteristics.

(39) Multi-outputs transconductance amplifiers are usually used to reduce the number of active devices. In some examples, one or more tuning feature is lost. For example, the filter in Sun, Y, and Fidler, K., (Current-mode OTA-C realization of arbitrary filters characteristics. Electron. Lett. 32(13), 1181-1182 (June 1996)incorporated herein by reference) uses n+2 single-output transconductance amplifiers plus n dual-outputs transconductance amplifiers while FIG. 3 adopts n+3 single output transconductance amplifiers plus n dual-outputs transconductance amplifiers. But both filters have dependent coefficients. The filter in Chang, C., Al-Hashimi, B. M., Sun, Y., and Ross, J. N, (New high-order filter structures using only single-ended-input OTAs and grounded capacitors. IEEE Trans. Cir. Syst. I. 51(9), 458-463, (September 2004)incorporated herein by reference) employs n+2 single-output transconductance amplifiers plus n+2 dual-outputs transconductance amplifiers but it exhibits dependent coefficients too. The filter suggested in Chang, C., Hou, C., Chung, W., Horng, J., and Tu, C.: Analytical synthesis of high-order single-ended-input OTA-grounded C all-pass and band-reject filter structures. IEEE Trans. Cir. Syst. I. 53(3), 489-498, (March 2006)incorporated herein by reference) uses two transconductance amplifiers with n outputs but also it exhibits transfer functions with dependent coefficients as well. Similarly, the filter in Feng, J., Wang, C., Zang, M., and Ren, Y., (Realization of current-mode general nth-order filter based on current mirrors. 3rd International Conference on Advanced Computer Control (ICACC 2011). 367-370, (2011)incorporated herein by reference) incorporating n single output transconductance amplifiers plus one transconductance amplifiers with n+1 outputs exhibits dependent coefficients too. The filter in Tsukutani, T., (A general class of current-mode high-order OTA-C filters, International Journal of Electronics. 81(6), 663-669, (1996)incorporated herein by reference) employs n1 transconductance amplifiers with 3 outputs, two transconductance amplifiers with two outputs, and one single-output transconductance amplifiers. The work assumes the various output have different gains. However, the given simulations were based on a transconductance amplifiers macro model and the CMOS realization needed to provide independent programmability was not provided.

(40) Therefore, the most efficient realization is the current-mode topology as it incorporates the minimum possible (n+1) transconductance amplifiers as shown in FIG. 8 (disclosed in U.S. Pat. No. 8,872,580, which is incorporated herein by reference in its entirety). This is achieved as a single transconductance amplifier can be utilized to efficiently develop the integrator such that the feedback factor and output signals can be realized using the same device. The filter of FIG. 8 is functionally similar, but structurally different to its counterpart filter in Tsukutani, T., (A general class of current-mode high-order OTA-C filters, International Journal of Electronics. 81(6), 663-669, (1996)incorporated herein by reference) using one transconductor less. However, transconductance amplifiers having outputs with different gains would be used to promote independent programmability features. The transfer function of the filter of the FIG. 8 is given by equation (6):

(41) $\begin{array}{cc}T\left(s\right)=\frac{I_{\mathrm{out}}}{I_{\mathrm{in}}}=\frac{\begin{array}{c}\frac{g_{a_n{C}_1{C}_2\mathrm{.Math.}{C}_n}}{g_{{}_1}{g}_{{}_2}\mathrm{.Math.}{g}_{{}_n}}{s}^n+\frac{g_{a_{n-1}{C}_1{C}_2\mathrm{.Math.}{C}_{n-1}}}{g_{{}_1}{g}_{{}_2}\mathrm{.Math.}{g}_{{}_{n-1}}}{s}^{n-1}+\mathrm{.Math.}+\\ \frac{g_{a_2{C}_1{C}_2}}{g_{{}_1}{g}_{{}_2}}{s}^2+\frac{g_{a_1{C}_1}}{g_{{}_1}}s+g_{a_o}\end{array}}{\begin{array}{c}\frac{g_R{C}_1{C}_2\mathrm{.Math.}{c}_n}{g_{{}_1}{g}_{{}_2}\mathrm{.Math.}{g}_{{}_n}}{s}^n+\frac{g_{b_{n-1}{C}_1{C}_2\mathrm{.Math.}{C}_{n-1}}}{g_{{}_1}{g}_{{}_2}\mathrm{.Math.}{g}_{{}_{n-1}}}{s}^{n-1}+\mathrm{.Math.}+\\ \frac{g_{b_2{C}_1{C}_2}}{g_{{}_1}{g}_{{}_2}}{s}^2+\frac{g_{b_1{C}_1}}{g_{{}_1}}s+g_{b_o}\end{array}}& \left(6\right)\end{array}$
where s=j, is an operational frequency of the filter, n is an order of the filter.

(42) In FIG. 8, n+1 multi-gain transconductance amplifiers are arranged in cascade to generate a reconfigurable nth-order filter with independent programmability. A first stage multi-gain transconductance amplifier AN includes a single non-inverting input, a single inverting input coupled to the ground node and three transconductance amplifiers outputs. N1 intermediate stage multi-gain transconductance amplifiers (from AN1 to A1) are disposed in the cascade between the first multi-gain transconductance amplifier and the last multi-gain transconductance amplifier A0. Each of the multi-gain transconductance amplifiers (from AN1 to A1) includes a single non-inverting input, one inverting input, and at least three outputs. A first output of each of the multi-gain transconductance amplifiers (AN1 to A1) feedbacks to the non-inverting input of the multi-gain transconductance amplifier AN. A second output of each of multi-gain transconductance amplifiers (AN1 to A1) feeds to the non-inverting input of the next cascade multi-gain transconductance amplifiers (AN2 to A0). A third output of each of the multi-gain transconductance amplifiers (AN1 to A1) establishes a feedforward connection with the third outputs of all the other multi-gain transconductance amplifiers (AN1 to A1) to form an accumulative feedforward signal. A final stage multi-gain transconductance amplifier A0 includes a single non-inverting input, a single inverting input coupled to the ground node and two outputs. A first output of the final stage transconductance amplifier A0 feedbacks to the non-inverting input of the first stage transconductance amplifier AN. A second output of the final stage transconductance amplifier A0 connects with the third outputs of all the other multi-gain transconductance amplifiers (AN to A1). The filter includes N capacitors (Cn to C1). Each capacitor (Cn1 to C1) is connected between the ground node and the second output of the intermediate stage (AN1 to A1). Cn is connected between the ground node and the second output of the final stage (AN).

(43) Combining the transconductance amplifiers circuit of FIG. 2 and the filter structure of FIG. 8 would lead to a RNOF employing n+1 transconductance amplifiers while preserving independent filter coefficients. This filter uses less number of active devices compared to the solutions based on current amplifier (CA) and voltage follower (VF) in references, such as Alzaher, H., Tasadduq, N., and Al-Ees, O., (Digitally programmable high-order current-mode universal filters. Analog Int. Circ. and Signal Processing, 67(2), 179-187, (2010),incorporated herein by reference) and Alzaher, H., Tasadduq, N., and Al-Ees, O., (A class of digitally programmable nth-order filters. Int. J. Circ. Theor. Appl. 40(9), 943-956, (September 2012)incorporated herein by reference) as well as its counterpart based on a second generation current conveyors (CCII) described in Mahmoud, S. A.: Digitally programmable second generation current conveyor-based FPAA. Int. J. Circ. Theor. Appl. Int. J. Circ. Theor. Appl., 41(10), 1074-1084,incorporated herein by reference) and Alzaher, H., Tasadduq, N. and Al-Ees, O., (Implementation of reconfigurable nth-order filter based on CCII. Analog Integrated Circuits and Signal Processing, 75(3), 539-545,incorporated herein by reference). This is because that the filters of Alzaher, H., Tasadduq, N., and Al-Ees, O., (Digitally programmable high-order current-mode universal filters. Analog Int. Circ. and Signal Processing, 67(2), 179-187, (2010),incorporated herein by reference) and Alzaher, H., Tasadduq, N., and Al-Ees, O., (A class of digitally programmable nth-order filters. Int. J. Circ. Theor. Appl. 40(9), 943-956, (September 2012)incorporated herein by reference) use n+3 CAs plus n VFs and n+2 CA plus n+1 VFs, respectively. Whereas the filter of Mahmoud, S. A.: Digitally programmable second generation current conveyor-based FPAA. Int. J. Circ. Theor. Appl. Int. J. Circ. Theor. Appl., 41(10), 1074-1084incorporated herein by reference), employs 3n+3 digitally controlled CCIIs and that of Alzaher, H., Tasadduq, N., and Al-Ees, O., (A class of digitally programmable nth-order filters. Int. J. Circ. Theor. Appl. 40(9), 943-956, (September 2012)incorporated herein by reference) uses n+2 CCII plus 2n+1 CAs.

(44) In an example, certain second-order filters are not suitable for implementing RNOF although they can be connected in cascade to achieve high-order functions. They cannot implement odd-order responses. In addition, biquads based on single active devices do not promote electronics tuning. On the other hand, it can be shown that universal biquads adopting multi-active devices are inefficient when employed to achieve high-order functions. For example, the filter in (New Configuration for OFCC-Based CM SIMO Filter and its Application as Shadow Filter, Arabian Journal for Science and Engineering, 2018, vol. 59.incorporated herein by reference) can use six and nine active devices to realize 4.sup.th and 6.sup.th-order functions while the proposed solution of FIG. 9 uses five and seven, respectively.

(45) The g.sub.m can be incorporated in the design of an amplifier (AMP)-based low-dropout regulator (LDO). The AMP-based LDO is attractive due to its more accurate line/load regulation resulted from its high dc gain. The AMP-based LDO can include the main LDO and a g.sub.m-cell. The auxiliary path formed by the g.sub.m-cell is added in parallel to compensate for low frequency LDO output pole. It is important that the effective transconductance of the g.sub.m-cell to be high in order to generate feed-forward zero inside loop gain bandwidth (GBW).

(46) In an example, a 4.sup.th-order 7 MHz cutoff frequency Butterworth filter obtained from FIG. 8 was fabricated in a 0.18 m CMOS process, using capacitors values of C.sub.1=16.7 pF, C.sub.2=8.3 pF, C.sub.3=4.9 pF, and C.sub.4=2.4 pF.

(47) In an embodiment, a biasing current of each transconductance amplifier is about 1 mA, however, less than 10% of it is used for operating the programmable output stages. The experimental results for the low-pass, bandpass and high-pass outputs are shown in FIG. 9. Operating frequencies of the filter can be tuned by simultaneously changing all the forward path parameters, g.sub.1 to g.sub.4. The experimental results showing the tuning feature for a 4.sup.th order Butterworth low-pass filter is shown in FIG. 10. When the controlling currents are simultaneously changed from 10 A to 100 A giving the tuning of cutoff frequency from 2.2 MHz to 7 MHz. The 4.sup.th order Butterworth low-pass filter coefficients can be changed to realize a Chebyshev 4.sup.th order low-pass filter for 5 MHz cutoff frequency. The experimental results are shown in FIG. 11.

(48) As recognized by the inventor, the canonic filters reported in the literature are not suitable for reconfigurable applications, not only for the lack of programmability features, but also for the demand of matching conditions to realize the high-pass response. On the other hand, universal filter structures are associated with independent filter characteristics but employ more transconductance amplifiers. Adopting multi-outputs transconductance amplifiers leads to optimum solution having minimum number of devices. However, the adopted multi-outputs transconductance amplifiers are associated with different gains in order to maintain independent programmability characteristics. Consequently, a new CMOS programmable multi-gain transconductance amplifier has been developed. The proposed transconductor amplifier employs a transconductance amplifiers circuit at its input stage and current folding output stages whose gains can be controlled via their respective biasing currents. Experimental results obtained from a 4.sup.th-order universal filter demonstrating versatile programmability features are provided and show the independent gain tuning capability by varying the biasing current of the current folding output stages.

(49) Thus, the foregoing discussion discloses and describes merely exemplary embodiments of the present disclosure. As will be understood by those skilled in the art, the present disclosure may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. Accordingly, the disclosure of the present disclosure is intended to be illustrative, but not limiting of the scope of the disclosure, as well as other claims. The disclosure, including any readily discernible variants of the teachings herein, defines, in part, the scope of the foregoing claim terminology such that no inventive subject matter is dedicated to the public.