Phase-change resistive memory

Abstract

A phase change resistive memory includes an upper electrode; a lower electrode; a layer made of an active material, called an active layer; the memory passing from a highly resistive state to a weakly resistive state by application of a voltage or a current between the upper electrode and the lower electrode and wherein the material of the active layer is a ternary composed of germanium Ge, tellurium Te and antimony Sb, the ternary including between 60 and 66% of antimony Sb.

Claims

1. A method for manufacturing a phase-change resistive memory including an upper electrode; a lower electrode; an active layer made of an active material; the memory switching from a high resistivity state to a low resistivity state by applying a voltage between the upper electrode and the lower electrode, the material of the active layer being a ternary composed of germanium Ge, tellurium Te and antimony Sb, the ternary including 10% of germanium Ge, 27% of tellurium Te and 63% of antimony Sb, the material of the active layer being in a polycrystalline phase in the high resistivity state and in a crystalline phase in the low resistivity state, the method comprising the steps performed in the following order: a step of conformably depositing a conducting material layer of the lower electrode onto a substrate; a step of sputtering using two sputtering targets to form the active layer, a target composed of the element of the chemical formula Ge.sub.2Sb.sub.2Te.sub.5 and a target composed of antimony Sb, and a step of conformably depositing a conducting material layer of the upper electrode, wherein the switching from the high resistivity state to the low resistivity state in said memory is obtained by growth of crystals of the polycrystalline phase.

2. The method according to claim 1, wherein the active layer is doped.

3. The method according to claim 1, wherein a current intensity flowing in the active layer of the memory increases linearly as soon as the voltage between the upper electrode and the lower electrode exceeds a first voltage, said first voltage being lower than a threshold voltage for which the material of the active layer switches from an amorphous state to a crystalline state.

Description

BRIEF DESCRIPTION OF THE FIGURES

(1) The figures are shown for indicative and in no way limiting purposes of the invention.

(2) FIG. 1A shows three images obtained by transmission electron microscopy representing respectively the concentration of germanium Ge, antimony Sb and tellurium Te of the active layer of a PCM memory having a composition according to prior art, after one programming cycle.

(3) FIG. 1B shows three images obtained by transmission electron microscopy representing respectively the concentration of germanium Ge, antimony Sb and tellurium Te of the active layer of a PCM memory according to a first aspect of the invention, after one programming cycle.

(4) FIG. 2 shows the block diagram of a manufacturing method according to a second aspect of the invention.

(5) FIG. 3A shows the schematic representation of a first step of the method according to a second aspect of the invention.

(6) FIG. 3B shows the schematic representation of a second step of the method according to a second aspect of the invention.

(7) FIG. 3C shows the schematic representation of a third step of the method according to a second aspect of the invention.

(8) FIG. 4 represents the current intensity flowing in the active layer of a memory according to a first aspect of the invention and in the active layer of a conventional PCM memory, as a function of the voltage applied across their electrodes, the memories being initially in their high resistivity state.

(9) FIG. 5 shows an image obtained by nano beam diffraction analysis on the material of the active layer of a memory according to a first aspect of the invention.

DETAILED DESCRIPTION OF AT LEAST ONE EMBODIMENT OF THE INVENTION

(10) Unless otherwise indicated, a same element appearing in different figures has a single reference.

(11) FIG. 1A has already been described in reference to the state of the art.

(12) A first aspect of the invention relates to a phase-change resistive memory (PCM memory).

(13) [FIG. 3C] shows a schematic representation of the PCM memory 100 according to a first aspect of the invention.

(14) The PCM memory 100 includes: a lower electrode 101; an active layer 102; and an upper electrode 103.

(15) An upper electrode of a device is defined as the electrode located above this device and the lower electrode of a device as the electrode located below this device, the electrodes being located on either side of the device. Of course, the adjective “upper” and “lower” are herein relating to the orientation of the assembly including upper electrode, device and lower electrode such that by turning over this assembly, the electrode previously referred to as the upper electrode becomes the lower electrode and the electrode previously referred to as the lower electrode becomes the upper electrode.

(16) The lower 101 and upper 103 electrodes are each made of a conducting material which can be different or the same for both electrodes 101, 103. Such a conducting material is for example TiN, TaN, W, TiWN, TiSiN or even WN.

(17) The active layer 102 is an active material layer made of a ternary composed of germanium Ge, tellurium Te and antimony Sb. The percentage of antimony Sb contained in the active material is between 60 and 66%, that is the active material consists of 60 to 66% of antimony Sb and 34 to 40% of germanium Ge and tellurium Te.

(18) For example, the 34 to 40% of germanium Ge and tellurium Te are distributed into 7 to 13% germanium Ge and 27 to 33% tellurium Te.

(19) According to a preferred exemplary embodiment, the active material is composed of 10% of germanium Ge, 27% of tellurium Te and 63% of antimony Sb.

(20) According to one embodiment, the active layer 102 is doped. The active layer 102 is for example doped with carbon C or nitrogen N.

(21) [FIG. 1B] shows three images obtained by transmission electron microscopy representing respectively the concentration of germanium Ge, antimony Sb and tellurium Te of the active layer of the PCM memory 100 after one programming cycle. The higher the current intensity at a point of the image, the higher the concentration of the component at this point.

(22) The absence of the half-ring for the three components and thus the absence of the segregation phenomenon are noticed.

(23) This is very surprising given that in the state of the art, the segregation phenomenon intensifies as antimony Sb is added in the composition of the active material.

(24) In addition to the absence of the segregation phenomenon, the composition of the active layer 102 of the PCM memory 100 is characterised by a polycrystalline phase and not by an amorphous phase in the high resistivity state, and by a single crystal phase in the low resistivity state. More particularly, in the high resistivity state, the active layer 102 has crystal nuclei visible in FIG. 5.

(25) [FIG. 5] is an image obtained by nano beam diffraction analysis on the active layer material of the PCM memory 100 showing crystal nuclei represented by light white dots on the image.

(26) Thus, switching from the low resistivity state to the high resistivity state is not characterised by a state, density, and volume change requiring applying a threshold voltage but by a growth/decrease of crystals requiring applying a voltage lower than the threshold voltage.

(27) FIG. 4 represents the current intensity flowing in the active layer of the PCM memory 100 as a function of the voltage applied across its electrodes in addition to the current intensity flowing in the active layer of a conventional PCM memory as described with reference to the state of the art.

(28) It is noticed that the current intensity linearly increases with the voltage across the electrodes as soon as a voltage represented by a solid line, and being lower than the threshold voltage represented as a dotted line is exceeded.

(29) The composition of the active layer 102 of the PCM memory 100 thus enables the electric stress and thermal stress due to switching from a fully amorphous state to a crystalline state to be decreased and the mechanical stress to be decreased because there is less density and volume modification and having crystal nuclei rather than an amorphous phase in the high resistivity state prevents the drift over time to higher resistivity states.

(30) A second aspect of the invention relates to a method for manufacturing the resistive memory 100.

(31) [FIG. 2] shows a block diagram of steps 201 to 203 of the method 200 for manufacturing the resistive memory 100.

(32) [FIG. 3A] illustrates a first step 201 of the method 200 for manufacturing the resistive memory 100.

(33) The first step 201 consists in performing a conformable deposit of a conducting material layer of lower electrode 101 onto a substrate not represented in FIG. 3A.

(34) By “conformable deposit of a material layer onto a substrate”, it is meant that the material is evenly deposited on the whole surface of the substrate.

(35) The substrate can consist of one or more layers: it comprises, for example, a layer with exposed copper lines enabling metal contacts to be made with an upper metal layer and thus comprises the entire logic necessary for allowing connection with the lines of the upper layers.

(36) [FIG. 3B] illustrates a second step 202 of the method 200 for manufacturing the resistive memory 100.

(37) The second step 202 consists in using the sputtering technique to form the active layer 102 of the resistive memory 100.

(38) The sputtering principle is to use the energy of a plasma at the surface of one or more sputtering targets, to withdraw the atoms of the material of the target(s) one by one and to deposit them onto a substrate.

(39) According to a first embodiment, the sputtering step 202 uses a single sputtering target composed of a material having the same composition as the active material of the PCM memory 100 desired to be manufactured. The sputtering step 202 then consists in sputtering the single target.

(40) According to a second embodiment, the sputtering step 202 uses three sputtering targets: a target composed of germanium Ge, a target composed of tellurium Te and a target composed of antimony Sb. The sputtering step 202 then consists in co-sputtering the three targets so as to obtain the desired percentages for each component of the ternary.

(41) According to a third embodiment, the sputtering step 202 uses two sputtering targets: a target composed of the element of the chemical formula Ge.sub.2Sb.sub.2Te.sub.5 and a target composed of antimony Sb. The sputtering step 202 then consists in co-sputtering both targets to obtain the desired percentages for each component of the ternary.

(42) It is also possible to use other sputtering targets made of other materials, the previous examples being not limiting. For example, three sputtering targets can be used: a target composed of the element of the chemical formula GeTe, a target composed of the element of the chemical formula Sb.sub.2Te.sub.3 and a target composed of antimony Sb. Two sputtering targets can for example be used: a target composed of the element of the chemical formula Ge.sub.2Te.sub.5 and a target composed of antimony Sb.

(43) Sputtering or co-sputtering is for example directly made on the conducting material layer of lower electrode 101, as represented in FIG. 3B.

(44) FIG. 3C illustrates a third step 203 of the method 200 for manufacturing the resistive memory 100.

(45) The third step 203 consists in performing a conformable deposit of a conducting material layer of upper electrode 103.

(46) The conformable deposit is for example directly made onto the active layer 102, as represented in FIG. 3C.

(47) The manufacturing method 200 illustrated in FIGS. 3A, 3B and 3C enables a planar-shaped PCM memory 100 to be manufactured but the PCM memory 100 could have a different shape. For example, the conducting material layer of lower electrode 101 includes two branches arranged so as to form an “L” shape, the active layer 102 being in contact with the end of the branch with the greater length. The method for manufacturing such a PCM memory 100 is thereby different from the manufacturing method 200.

(48) The manufacturing method 200 illustrated in FIGS. 3A, 3B and 3C enables only the PCM memory 100 to be manufactured but it could also be manufactured to be co-integrated, for example with a selector device.