Process for producing a micro-electro-mechanical system from a transferred piezoelectric or ferroelectric layer
11705880 · 2023-07-18
Assignee
- Commissariat A L'energie Atomique Et Aux Energies Alternatives (Paris, FR)
- UNIVERSITE DE FRANCHE-COMTE (Besançon, FR)
- ECOLE NATIONALE SUPERIEURE DE MECANIQUE ET DES MICROTECHNIQUES (Besançon, FR)
Inventors
Cpc classification
H03H2003/021
ELECTRICITY
H03H9/02228
ELECTRICITY
H10N30/072
ELECTRICITY
H03H2003/025
ELECTRICITY
International classification
H03H3/02
ELECTRICITY
Abstract
A process for fabricating a micro-electro-mechanical system, includes the following steps: production of a stack on the surface of a temporary substrate so as to produce a first assembly, comprising: at least depositing a piezoelectric material or a ferroelectric material to produce a layer of piezoelectric material or of ferroelectric material; producing a first bonding layer; production of a second assembly comprising at least producing a second bonding layer on the surface of a host substrate; production of at least one acoustic isolation structure in at least one of the two assemblies; production of at least one electrode level containing one or more electrodes in at least one of the two assemblies; bonding the two assemblies via the two bonding layers, before or after the production of the at least one electrode level in at least one of the two assemblies; removing the temporary substrate.
Claims
1. A process for fabricating a micro-electro-mechanical system, comprising the following steps: production of a stack on the surface of a temporary substrate so as to produce a first assembly, comprising: at least depositing a piezoelectric material or a ferroelectric material to produce a layer of piezoelectric material or of ferroelectric material; producing a first bonding layer; production of a second assembly comprising at least producing a second bonding layer on the surface of a host substrate; production of at least one acoustic isolation structure in at least one of the two assemblies; production of at least one electrode level containing one or more electrodes in at least one of the two assemblies; bonding said two assemblies via said two bonding layers such that said acoustic isolation structure is between said host substrate and layer of piezoelectric material or of ferroelectric material, before or after the production of the at least one electrode level in at least one of the two assemblies; removing said temporary substrate, wherein the process comprises: producing a sacrificial layer above a dielectric material; structuring said sacrificial layer so as to define a sacrificial layer structure; depositing a dielectric above said sacrificial layer structure; removing said sacrificial layer structure so as to define said acoustic isolation structure.
2. The process according to claim 1, wherein said piezoelectric material or said ferroelectric material is deposited by epitaxial growth.
3. The process according to claim 1, wherein the micro-electro-mechanical system comprises at least one bulk acoustic wave resonator or at least one surface acoustic wave resonator or at least one Lamb wave resonator.
4. The process according to claim 1, wherein the bonding comprises a step of thermal annealing.
5. The process according to claim 1, wherein the operation of removing the temporary substrate comprises: a step of thinning said temporary substrate; an operation of chemically etching said thinned temporary substrate.
6. The process according to claim 1, wherein the operation of removing said temporary substrate comprises: a step of diffusing elements that cause precipitation or chemical reactions in the material from which said temporary substrate is made, or a step of implanting ions into said temporary substrate.
7. The process according to claim 1, comprising depositing a buffer layer on the surface of said temporary substrate, prior to the deposition of said piezoelectric material or of said ferroelectric material.
8. A micro-electro-mechanical system obtained using the process according to claim 1.
9. The process according to claim 1, wherein the dielectric material is an oxide that may be SiO.sub.2, the sacrificial layer being made of amorphous silicon or of polysilicon.
10. The process according to claim 1, wherein the production of the acoustic isolation structure comprises: producing at least one sacrificial layer in said first assembly; releasing said sacrificial layer structure after bonding said two assemblies.
11. A process for fabricating a micro-electro-mechanical system, comprising the following steps: production of a stack on the surface of a temporary substrate so as to produce a first assembly, comprising: at least depositing a piezoelectric material or a ferroelectric material to produce a layer of piezoelectric material or of ferroelectric material; producing at least one so-called lower electrode on the surface of said layer of piezoelectric material or of ferroelectric material; producing an acoustic isolation structure in said first assembly, wherein the production of the acoustic isolation structure comprises producing a Bragg mirror structure (MR); and producing a first bonding layer; production of a second assembly comprising at least producing a second bonding layer on the surface of a host substrate; bonding said two assemblies via said two bonding layers, after the production of the at least one lower electrode and the acoustic isolation structure; removing said temporary substrate, and after removing said temporary substrate, producing at least one so-called upper electrode on said layer of piezoelectric material or of ferroelectric material by depositing and structuring said upper electrode.
12. The process according to claim 11, comprising the production of structured layers made of metal and of molybdenum, said structured layers being inserted into the dielectric that are SiO.sub.2.
13. The process according to claim 1, comprising: prior to said bonding of the two assemblies, producing at least one so-called lower electrode on the surface of said layer of piezoelectric material or of ferroelectric material and producing an acoustic isolation structure in said first assembly; after removing said temporary substrate, producing at least one so-called upper electrode on said layer of piezoelectric material or of ferroelectric material.
14. The process according to claim 1, comprising, prior to said bonding of said two assemblies: producing electrodes on the surface of said layer of piezoelectric material or of ferroelectric material; producing an acoustic isolation structure in said second assembly.
15. The process according to claim 1, wherein the piezoelectric material is LiNbO.sub.3 or LiTaO.sub.3 or solid solutions thereof, or KNbO.sub.3 or AIN or GaN.
16. The process according to claim 1, wherein the ferroelectric material is: LiNbO.sub.3 or LiTaO.sub.3 or PZT.
17. The process according to claim 1, wherein the temporary substrate is made of MgO or of SrTiO.sub.3 or of LaAlO.sub.3 or of LSAT ((LaAlO.sub.3).sub.0.3(Sr.sub.2TaAlO.sub.6).sub.0.7) or of DyScO.sub.3, or of sapphire (Al.sub.2O.sub.3) or of lithium niobate (LiNbO.sub.3) or of lithium tantalate (LiTaO.sub.3) or of quartz, the piezoelectric material being PZT.
18. The process according to claim 1, wherein the bonding layers are made of oxide or made of polymer.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
(1) The invention will be better understood and other advantages will become apparent on reading the following nonlimiting description, and by virtue of the appended figures, in which:
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DETAILED DESCRIPTION
(42) Thus the process of the present invention comprises the following main steps, in versions according to certain variants and certain options: preparing a temporary substrate that is a suitable growth substrate. This may require the surface of the substrate to be treated and/or layers for matching epitaxial relationships between the layer to be deposited and the growth substrate to be deposited;
(43) depositing the piezoelectric or ferroelectric layer using a suitable technique, in order to make grow a single-crystal or at the very least textured material; producing the lower portion of the component above the deposited layer, or on another substrate (the future host substrate). This lower portion may comprise electrodes or the like, or at least a structure for acoustically isolating the acoustic wave resonator that will be formed: release well that will allow an air cavity to be inserted under the resonator or Bragg mirror;
bonding the growth substrate comprising the epitaxial layer where appropriate and some of the structures of the lower portion of the component to the host substrate, which optionally possesses the rest of this lower portion (possibly a sacrificial layer structure, at least one electrode, etc.);
detaching the temporary substrate, which may be a growth substrate, by means known to those skilled in the art (chemical or physical etching of the substrate or of one of the layers incorporated into the growth substrate);
completing the fabrication of the component by producing the upper portion of the component.
(44) The Applicant describes below a plurality of examples of processes, the steps of which are illustrated by the figures, in which the same references have been employed, which references correspond to the following elements, respectively: 100: a temporary substrate 200: a buffer layer 300: a layer of piezoelectric material or of ferroelectric material 400: at least one lower electrode 500a, 500b, 500c.fwdarw.500: dielectric material, in particular intended for bonding 600: a sacrificial layer structure MR: a Bragg mirror structure 700: a host substrate 800: at least one upper electrode 900: an upper dielectric layer 1000: contact pads
(45) The examples below are described in the context of piezoelectric materials, but may equally well be applied in the context of ferroelectric materials.
(46) Example of a process for fabricating a bulk wave resonator according to the invention comprising a released sacrificial structure:
(47) Step 1.1:
(48) A silicon substrate corresponding to the temporary substrate 100 is prepared via a high-temperature anneal (temperature >1000° C.) in order to obtain a surface that is smooth on the atomic level, as illustrated in
(49) Step 1.2:
(50) A buffer layer 200, for example of ZnO and of a thickness for example of 20 nm, is deposited by molecular beam epitaxy (MBE), as illustrated in
(51) Step 1.3:
(52) A layer of LiNbO.sub.3 for example of 250 nm thickness is deposited by pulsed injection metal-organic chemical vapour deposition (PI-MOCVD). The lattice match between the Si/ZnO/LiNbO.sub.3 for example leads to growth of a layer of c-axis lithium niobate 300, as illustrated in
Step 1.4:
A lower electrode 400, which is for example made of molybdenum of 100 nm thickness, is deposited by sputtering, then structured by photolithography, reactive ion etching and resist removal, as illustrated in
Step 1.5:
A protective dielectric layer made of SiO.sub.2 500a, for example of 100 nm thickness, is deposited for example by plasma-enhanced chemical vapour deposition (PECVD), then a sacrificial layer made of amorphous silicon, for example of 1 μm thickness, is deposited by sputtering. The latter is structured by photolithography, reactive ion etching and resist removal, to obtain a sacrificial layer structure 600 as illustrated in
Step 1.6:
SiO.sub.2 dielectric 500b, for example of 2 μm thickness, for example is deposited by reactive sputtering of Si using an Ar/O.sub.2 plasma and chemical-mechanical polishing (CMP), as illustrated in
Step 1.7:
Moreover, a substrate covered with a layer 500c by thermal oxidation of a silicon host substrate 700, for example such as to achieve a thickness of 500 nm, is prepared as illustrated in
Step 1.8:
The surfaces are activated and the host substrate 700 and the temporary substrate 100, which corresponds to a growth substrate, are then direct bonded, after which an annealing operation is carried out to consolidate the bond achieved via the dielectric 500, as illustrated in
Step 1.9:
An operation for detaching the temporary growth substrate 100 is carried out.
Thinning by mechanical grinding that aims to leave only about ten microns of thickness, then chemical etching of the temporary growth substrate in a tetramethyl ammonium hydroxide (TMAH) solution and chemical etching of the ZnO buffer layer 200 for example with HCl are carried out, as illustrated in
Step 1.10:
The etch intended for electrical contacts down to the lower electrode is carried out by photolithography, ion-beam etching (IBE) of the piezoelectric layer 300, and resist removal, as illustrated in
Step 1.11:
An upper electrode 800 (again made of Mo, for example of 100 nm thickness) is deposited and structured, as illustrated in
Step 1.12:
The upper electrode is then encapsulated with a layer of SiO.sub.2 900 that is for example deposited by PECVD, and for example once again of 100 nm thickness. Next, apertures for electrical contacts are produced in the film by photolithography, reactive ion etching and resist removal, as illustrated in
Step 1.13:
Electrical contacts 1000, which are for example made of aluminium, of 1 μm thickness, are deposited by sputtering, photolithography, chemical etching and resist removal, as illustrated in
Step 1.14:
Release apertures are etched by ion-beam etching of an SiO.sub.2/LiNbO.sub.3/SiO.sub.2 stack as illustrated in
Step 1.15:
The resonator (layer of piezoelectric material between electrodes) is then released by etching the sacrificial layer structure made of amorphous silicon 600 with XeF.sub.2 gas as illustrated in
Step 1.16:
Lastly, a voltage is applied to the terminals of the component and the latter is heated in order to orient the ferroelectric domains in the layer of lithium niobate in a preferred direction.
(53) Example of a process for producing a bulk acoustic wave resonator from epitaxial lithium niobate on a Bragg mirror
(54) A variant of the preceding production process consists in replacing the acoustic confinement provided by the air cavity located under the resonator with acoustic confinement provided by a Bragg mirror consisting of a stack of alternating layers of high and low acoustic impedances. Among the materials possessing a high acoustic impedance, layers of tungsten (W), of molybdenum (Mo), of silicon nitride (SiN) or of aluminium nitride (AlN) are conventionally considered. As regards materials possessing a low acoustic impedance, the literature above all mentions the use of silicon oxide (SiO.sub.2), but also mentions silicon oxycarbide (SiOC). These lists are not limiting.
(55) A process suitable for producing solidly mounted resonators (SMR), name given to bulk wave resonators mounted on Bragg mirrors, is described below:
(56) Step 2.1:
(57) Steps 1.1 to 1.4 of the first process are carried out until lower electrodes have been produced such as illustrated in
Step 2.2:
As illustrated in
Step 2.3:
The subsequent constituent layers of the Bragg mirror MR, here for example an SiO.sub.2/Mo (250 nm)/SiO.sub.2 (250 nm)/Mo (400 nm) mirror, are then deposited. Next photolithography operations and reactive ion etching of the Mo/SiO.sub.2/Mo trilayer are carried out as illustrated in
Step 2.4:
A layer of 2 μm of SiO.sub.2 500b is deposited, for example by PECVD, and the topography caused by the Bragg mirror MR is planarized as illustrated in
Step 2.5:
The surfaces are activated and the host substrate 700+500c (a substrate of silicon oxide) and temporary growth substrate 100 with the Bragg mirror MR are direct bonded. Annealing operations are carried out to consolidate the bond, as illustrated in
Step 2.6:
The temporary growth substrate 100 is detached as in the preceding embodiment, then the steps continue similarly to those of the production process until the electrical contacts have been finalized. Because of the presence of a Bragg mirror MR instead of the well of sacrificial layer, the releasing step is no longer required, as illustrated in
(58) Example of a process for producing a Lamb wave resonator from epitaxial lithium niobate
(59) The processes described above do not apply solely to bulk acoustic wave resonators, but may also be used to produce Lamb acoustic wave resonators, which are also referred to as plate wave resonators. These resonators differ in that the acoustic waves are no longer excited by two unapertured electrodes that sandwich the piezoelectric layer, but by two interdigitated comb-shaped electrodes that are positioned on one of the (top or bottom) faces of the piezoelectric layer. The other face may make contact with an electrode covering the surface of the component (in order to excite Lamb waves from the vertical electric field thus formed) or, in contrast, comprise no electrodes, in order to excite waves from the horizontal electric field formed between the electrodes of the interdigitated comb. More generally, this process may apply to any family of acoustic micro-resonators that would benefit from an epitaxial piezoelectric layer.
(60) Moreover, variant embodiments may be introduced into the preceding processes. In particular, other techniques for detaching the growth substrate are envisionable.
(61) Specifically, step 1.9) of the first examplaric method is based on chemical etching of the growth substrate. In the case where the latter is not made of silicon and is therefore difficult to dissolve chemically, or to save time, it may be advantageous to carry out thinning mechanically by means of grinding and chemical-mechanical polishing techniques. A drawback remains however: the process leads to a consumption of the growth substrate, and therefore to its loss, this resulting in a notable cost. In order to avoid this problem, it may be advantageous to cause a mechanical fracture of the growth substrate, which will then be able to be reused provided that suitable reconditioning steps are carried out. This fracture may be obtained in various ways. Mention may be made of the following:
(62) generation of a fragile interface during the growth of the piezoelectric layer. This may mainly occur when diffusion of an element that causes precipitation or chemical reactions that lead to the volume of one of the encapsulated materials present to increase, and therefore to spontaneous debonding on application of a mechanical stress, is assisted;
another technique consists in forming a fragile interface after the growth of the piezoelectric layer. This interface may be formed by implanting ions in the growth substrate, then carrying out a thermal anneal to cause the material to fracture, using a process similar to the Smart Cut™ process. This is possible when the epitaxial layer and the set of sublayers for accommodating the lattice parameters have a relatively small thickness, so as to be able to be passed through by the flux of ions during the implantation.
(63) Thus, one variant production process intended for example to produce a Lamb acoustic wave resonator is described hereinafter:
(64) Step 3.1:
(65) A layer of lithium niobate 300 is grown epitaxially on silicon, this epitaxial growth including growth of a buffer layer 200 allowing accommodation of the lattice mismatch between the lithium niobate and the temporary substrate made of silicon 100 (steps identical to steps 1.1 to 1.3 described in the first exemplaric process), as illustrated in
Step 3.2:
Helium and hydrogen ions are then implanted through the epitaxial layer, so as to form a fragile interface I inside the silicon substrate, as illustrated in
Step 3.3:
At this stage of the process, it is possible to optionally form electrodes and a passivating layer, and to form release wells 600 made of sacrificial layer, then to bond, via the dielectric 500 the donor substrate to the host substrate 700, in the same way as in steps 1.4 to 1.8 of the process above. In the present case, the resonator has no lower electrode under the piezoelectric layer, as illustrated in
Step 3.4:
The temporary growth substrate 100 is then detached. In this example, an anneal is carried out that allows the growth substrate to be fractured at the interface I weakened by ion implantation. Next, the thin layer of growth substrate remaining attached to the structure and the buffer layer are chemically etched, as illustrated in
Step 3.5:
The fabrication of the component is finalized. To do this, steps 1.10 to 1.16 of the above process are carried out as illustrated in
(66) The above examples of the process relate to the production of components from epitaxial lithium niobite layers.
(67) The present invention may also be used with other materials able to be grown epitaxially. Mention may for example be made of the materials AlN, GaN, LiTaO.sub.3, KNbO.sub.3, etc.
(68) The approach of the invention is however in no way limited to epitaxial layers. It may a priori be applied to any type of deposited layer, provided that the incorporation of the deposition step into the complete integration of the component is complex (for example, very high temperature deposition in the presence of metals and/or on a surface having a topography).
(69) An example of this type of situation is that of the use of thin layers of PZT to producing piezoelectric micro-transformers. This type of component is similar to the Lamb wave resonators described above, but is composed of two interdigitated comb transducers, one corresponding to the primary of the transformer, and the other to the secondary. The Lamb waves then ensure the transfer of power from the primary to the secondary. In order to effectively excite these waves in the PZT, it is necessary to provide a lower electrode. To ensure the electrical isolation of the primary and secondary, it is therefore necessary to produce two separate lower electrodes, and therefore to pattern the lower metal level. However, conventional PZT growth processes (sol-gel process, cathode sputtering or laser ablation, etc.) are generally optimized for growth on a metal film (generally of platinum) covering the entirety of the substrate. In particular, it has been observed that depositing PZT on patterned electrodes causes a certain number of problems: the nature of the surface on which the PZT film is deposited differs depending on whether it is a question of metal surface (textured Pt) or of the surface of another sublayer (amorphous SiO.sub.2 or partially textured TiO.sub.2, etc.); moreover, the coefficients of thermal expansion of the materials present are different. All this leads to the appearance of residual strains that differ between the metallized regions and non-metallized regions. Moreover, the presence of metal may form a barrier to the diffusion of certain elements (Pb in particular). Parasitic phases (polychloride phase deficient in Pb) are therefore observed to appear in the non-metallized regions, this being unacceptable in terms of fabrication and operation of the components. Even though the insertion of suitable sublayers allows this problem to be partially solved, as described in the article M. Bousquet, B. Viala, H. Achard, J. Georges, A. Reinhardt, E. Nolot, G. Le Rhun, E. Defaÿ, Pt-less silicon integration of PZT sol-gel thin films for microelectronics, Electroceramics XIV, 2014, it still remains tricky to obtain an identical material in the metallized and non-metallized regions.
(70) The present invention allows this problem to be solved. Specifically it allows a PZT film to be deposited on a growth substrate covered with an unapertured sheet electrode, then this film to be transferred to a host substrate that incorporates, for its part, a patterned electrode. Moreover, the present invention allows the PZT films to be grown using non-silicon substrates, such as for example substrates of MgO, of SrTiO3, of LaAlO3, of LSAT ((LaAlO3)0.3(Sr2TaAlO6)0.7), of DyScO3, of sapphire (Al2O3) or of lithium niobate (LiNbO3) or of lithium tantalate (LiTaO3). These single-crystal substrates have the advantage of allowing epitaxial growth of the PZT, rather than polycrystalline growth as encountered with most films deposited on silicon. In addition, the choice of the substrate allows the crystal orientation of the deposited film, the structure of the ferroelectric domains (proportion of ferroelectric domains with a/c orientation) and the Curie temperature of the material formed to be modulated.
(71) Example of a Process for Producing a Piezoelectric Transformer Made of PZT
(72) Step 4.1:
(73) An SrTiO.sub.3 substrate 100 is prepared: chemical treatment (H.sub.2O+buffered HF)+high-temperature anneal (temperature >1000° C.) in order to obtain atomic surface steps (TiO.sub.2 surface planes), such as illustrated in
(74) Step 4.2:
(75) A PZT layer 300 is deposited, for example by laser ablation, cathode sputtering or sol-gel processing, and preferably with a thickness of 2 μm, as illustrated in
(76) Step 4.3:
(77) A metal layer, for example one made of ruthenium of 100 nm thickness, is deposited by sputtering, then this layer is structured to define the lower electrodes 400 by photolithography, reactive ion etching and resist removal, as illustrated in
(78) Step 4.4:
(79) A planarizing layer 500a made of SiO.sub.2 is deposited by PECVD and polished, as illustrated in
(80) Step 4.5:
(81) Photolithography operations, then reactive ion etching of a silicon host substrate 700 covered with an oxide layer 500b are also carried out in order to define cavities, for example of 3 μm depth, as illustrated in
(82) Step 4.6:
(83) As illustrated in
(84) Step 4.7:
(85) A new thermal operation is carried out in order to encapsulate the sacrificial structure 600 with 200 nm of oxide 500c, as illustrated in
(86) Step 4.8:
(87) As illustrated in
(88) Step 4.9:
(89) The temporary growth substrate 100 is then removed, by mechanical thinning finalized with chemical etching, as illustrated in
(90) Step 4.10:
(91) The metal from which the upper electrodes are made, for example 100 nm of ruthenium, is then deposited. Photolithography operations and ion etching, then resist removal are carried out in order to structure the electrodes 800 as illustrated in
(92) Step 4.11:
(93) A new photolithography operation, then ion etching of the PZT layer 300 are carried out in order to open holes for contacts to the lower electrodes 400, as illustrated in
(94) Step 4.12:
(95) Oxide 900 is deposited by PECVD, for example with a thickness of 200 nm, then photolithography operations are carried out to open holes for electrical contacts to the lower electrodes 400 and upper electrodes 800, as illustrated in
(96) Step 4.13:
(97) Cr/Au (1 μm) is deposited by sputtering, photolithography and wet etching, in order to form electrical contact pads 1000, as illustrated in
(98) Step 4.14:
(99) Photolithography operations and ionic etching are then carried out once more, but this time of the SiO.sub.2/PZT/SiO.sub.2 assembly, i.e. of 500/300/900, in order to open access to the sacrificial polysilicon structure 600. The polysilicon is then removed by etching with XeF.sub.2 gas, as illustrated in
Step 4.15:
The ferroelectric material is polarized by applying a voltage.
(100) This process also allows integration of PZT layers into substrates incompatible with the deposition temperatures required to obtain a crystallized PZT film to be envisioned. The invention therefore for example allows PZT actuators to be produced on glass.
(101) Lastly, the present invention is not necessarily limited to resonator applications. It may be applied to other micro-systems such as actuators or sensors.