SUPPLY-GLITCH-TOLERANT REGULATOR

Abstract

A supply-glitch-tolerant voltage regulator includes a regulated voltage node and an output transistor having a source terminal, a gate terminal, and a drain terminal. The source terminal is coupled to the regulated voltage node. The supply-glitch-tolerant voltage regulator includes a first current generator coupled between a first node and a first power supply node. The supply-glitch-tolerant voltage regulator includes a second current generator coupled between the first node and a second power supply node. The supply-glitch-tolerant voltage regulator includes a feedback circuit coupled to the first current generator and the second current generator and is configured to adjust a voltage on the first node based on a reference voltage and a voltage level on the regulated voltage node. The supply-glitch-tolerant voltage regulator includes a diode coupled between the drain terminal and the first power supply node and a resistor coupled between the gate terminal and the first node.

Claims

1. A supply-glitch-tolerant voltage regulator comprising: a regulated voltage node; an output transistor having a source terminal, a gate terminal, and a drain terminal, the source terminal being coupled to the regulated voltage node; a first current generator coupled between a first node and a first power supply node; a second current generator coupled between the first node and a second power supply node; a feedback circuit coupled to the first current generator and the second current generator and configured to adjust a voltage on the first node based on a reference voltage and a voltage level on the regulated voltage node; a diode coupled between the drain terminal and the first power supply node; and a resistor coupled between the gate terminal and the first node.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present invention may be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings.

[0007] FIG. 1 illustrates a functional block diagram of an integrated circuit low-dropout regulator in an exemplary integrated circuit system.

[0008] FIG. 2 illustrates a circuit diagram of an exemplary low-dropout regulator and associated current flows in response to an exemplary power supply glitch event.

[0009] FIG. 3 illustrates a circuit diagram of an exemplary supply-glitch-tolerant voltage regulator consistent with at least one embodiment of the invention.

[0010] FIG. 4 illustrates exemplary waveforms for an exemplary power supply glitch event and associated responses of various embodiments of a voltage regulator consistent with at least one embodiment of the invention.

[0011] The use of the same reference symbols in different drawings indicates similar or identical items.

DETAILED DESCRIPTION

[0012] Referring to FIGS. 1 and 2, low-dropout regulator 102 provides a regulated output voltage level on regulated voltage node V.sub.REG, which is used as the power supply voltage for analog and digital circuits. Low-dropout regulator 102 includes a source follower output stage (i.e., common drain amplifier, e.g., output transistor M.sub.PASS, which is n-type in an exemplary embodiment) configured to provide regulated voltage V.sub.REG and associated current (e.g., 1 mA). Compensation capacitor C.sub.COMP is sized to provide a pole in a loop gain of the low-dropout regulator 102. Regulated voltage V.sub.REG on regulated voltage node 203 is based on currents provided by current generator 204 and current generator 206 (e.g., each including a stack of at least one diode-coupled devices) and a control loop that compares regulated voltage V.sub.REG to reference voltage level V.sub.REF.

[0013] During an exemplary power supply glitch event having a duration t.sub.GLITCH (e.g., t.sub.GLITCH=50-100 ns) the voltage level on power supply node 201 falls from VDD to ground. Whenever the drain voltage of output transistor M.sub.PASS falls below regulated voltage V.sub.REG, the parasitic body diode of output transistor M.sub.PASS becomes forward biased and draws reverse current I.sub.REV, which is relatively large, from bypass capacitance C.sub.BYPASS and through a parasitic diode of the source follower output stage to power supply node 201. As the voltage level on power supply node 201 falls from V.sub.DD to ground, compensation capacitor C.sub.COMP, which is coupled to the gate of output transistor M.sub.PASS, also starts discharging via two currents: compensation loop current I.sub.COMP,LOOP, which is a small bias current, and reverse compensation current I.sub.COMP,REV. Reverse compensation current I.sub.COMP,REV flows from compensation capacitor C.sub.COMP through parasitic diodes of current generator 204 to power supply node 201. Compensation loop current I.sub.COMP,LOOP, flows from compensation capacitor C.sub.COMP to ground and bypass capacitance C.sub.BYPASS starts discharging. Reverse compensation current I.sub.COMP,REV is large enough to discharge the gate capacitance completely during a power supply glitch and recharging compensation capacitor C.sub.COMP after the power supply glitch can take a very long time, during which load current I.sub.LOAD continues to discharge bypass capacitance C.sub.BYPASS. Accordingly, regulated voltage V.sub.REG on regulated voltage node 203 falls from a target regulated voltage level to ground and a brownout reset occurs. After the power supply glitch, the voltage level on power supply node 201 returns to V.sub.DD and regulated voltage V.sub.REG on regulated voltage node 203 is restored to the target regulated voltage level. In response, the integrated circuit system coupled to low-dropout regulator 102 reinitiates a startup sequence, analog circuits 104 and digital circuits 106 will be reset, and states of the digital circuits 106 are corrupted.

[0014] Referring to FIG. 3, supply-glitch-tolerant regulator 302 provides regulated voltage V.sub.REG on regulated voltage node 303 that is robust against transient, large-amplitude noise on power supply node 301. Supply-glitch-tolerant regulator 302 includes a source follower output stage (i.e., common drain amplifier, e.g., output transistor M.sub.PASS, which is n-type in an exemplary embodiment) configured to provide regulated voltage V.sub.REG and associated current (e.g., 1 mA). The voltage level on regulated voltage node 303 is based on currents provided by current generator 304 and current generator 306 (e.g., each including a current mirror or cascoded current mirrors) and a control loop including transconductance amplifier 308 that compares regulated voltage V.sub.REG on regulated voltage node 303 to reference voltage level V.sub.REF. Transconductance amplifier 308 causes current generator 304 and current generator 306 to adjust the voltage on node 305 and the voltage on node 307, the gate of output transistor M.sub.PASS, to adjust the level of regulated voltage V.sub.REG according to the comparison. In at least one embodiment, supply-glitch-tolerant regulator 302 includes diode D.sub.GL, which blocks any flow of reverse current IREv from bypass capacitance C.sub.BYPASS to power supply node 301 through a parasitic diode of the source follower output stage. Diode D.sub.GL is coupled in series with the drain of output transistor M.sub.PASS and has, at most, negligible impact on normal operation of supply-glitch-tolerant regulator 302.

[0015] In at least one embodiment, to reduce or eliminate substantial discharge of bypass capacitance C.sub.BYPASS, in addition to diode D.sub.GL, supply-glitch-tolerant regulator 302 includes limiting resistor R.sub.LIM (e.g., R.sub.LIM=60 kΩ) which blocks the flow of reverse compensation current I.sub.COMP,REV from compensation capacitor C.sub.COMP (e.g., C.sub.COMP=10 pF) via node 307 through parasitic diodes of current generator 304 to power supply node 301. Limiting resistor R.sub.LIM is coupled in series with the gate of output transistor M.sub.PASS, separating compensation capacitor C.sub.COMP from the body diodes of the p-type devices in current generator 304. Limiting resistor R.sub.LIM limits the reverse current to a low level that is insufficient to cause a large voltage drop on the gate of output transistor M.sub.PASS during a power supply glitch, but is also small enough that it does not influence the normal operation of supply-glitch-tolerant regulator 302 since limiting resistor R.sub.LIM is coupled in series with two opposing current generators that provide a substantially larger impedance (i.e., R.sub.LIM<<(Z.sub.304∥Z.sub.306)). Limiting resistor R.sub.LIM and compensation capacitor C.sub.COMP have a time constant (i.e., τ=R.sub.LIM×C.sub.COMP, e.g., R.sub.LIM×C.sub.COMP=600 ns) that is greater than a specified power supply glitch tolerance Δt.sub.GLITCH_TOL (e.g., Δt.sub.GLITCH_TOL=100 ns for a regulated voltage lower limit of 3.5 V or 1.9 V) of supply-glitch-tolerant regulator 302.

[0016] In at least one embodiment, since circuits that receive power from regulated voltage node 303 must remain functional, bypass capacitance C.sub.BYPASS is sized so that the voltage drop caused by the net charge loss (e.g., I.sub.LOAD×Δt.sub.GLITCH, where I.sub.LOAD is the useful load current and Δt.sub.GLITCH is the duration of the power supply glitch) is insufficient to decrease regulated voltage V.sub.REG to a level below a specified lower limit. Supply-glitch-tolerant regulator 302 prevents regulated voltage V.sub.REG on regulated voltage node 303 from falling below a target minimum level during a power supply glitch that is shorter than the specified glitch tolerance. Thus, analog circuits and digital circuits powered by regulated voltage V.sub.REG on regulated voltage node 303 do not reset in response to the power supply glitch, and the digital circuits retain their states during and after the power supply glitch, providing seamless operation of the integrated circuit system, even under nonideal circumstances.

[0017] Referring to FIG. 4, a simplified timing-diagram illustrating the voltage level on power supply node V.sub.DD and regulated voltage V.sub.REG on regulated voltage node 303 during an exemplary power supply glitch event. If a voltage regulator includes no protection from a power supply glitch, regulated voltage V.sub.REG falls from the target regulated voltage level to ground immediately in response to the start of the power supply glitch event and a relatively long time elapses before the regulated output voltage level returns to the target regulated voltage level, as illustrated by waveform 402. Waveform 404 corresponds to a voltage regulator including diode D.sub.GL, alone. Diode D.sub.GL reduces the rate of change to regulated voltage V.sub.REG, but regulated voltage V.sub.REG continues to decrease after the power supply glitch ends, which can cause regulated voltage V.sub.REG to fall below a specified voltage limit. In an exemplary embodiment, diode D.sub.GL and limiting resistor R.sub.LIM are included in supply-glitch-tolerant regulator 302, where R.sub.LIM×C.sub.COMP>Δt.sub.GLITCH (e.g., Δt.sub.GLITCH<100 ns). The inclusion of limiting resistor R.sub.LIM in addition to diode DGL prevents the gate capacitor from discharging and regulated voltage V.sub.REG starts recovering to the target regulated voltage level right after the power supply glitch has ended, as illustrated by waveform 406. Thus, by including diode D.sub.GL and limiting resistor R.sub.LIM, with a suitable selection of bypass capacitance C.sub.BYPASS, regulated voltage V.sub.REG on regulated voltage node 303 stays within specified limits.

[0018] Although supply-glitch-tolerant regulator 302 has been described in an embodiment in which output transistor M.sub.PASS is n-type, one of skill in the art will appreciate that the teachings herein can be utilized with a p-type output transistor and circuitry that is complementary to the circuit illustrated in FIG. 3. In addition, teachings herein can be utilized with a target regulated voltage level that is close to V.sub.DD or above V.sub.DD, a target regulated voltage level that is close to ground or below ground, or a target regulated voltage level that is in between V.sub.DD, ground, or other power supply voltage. Furthermore, teachings herein can be utilized with voltage regulators including other feedback control loop circuitry.

[0019] Thus, embodiments of a supply-glitch-tolerant voltage regulator is disclosed. Supply-glitch-tolerant regulator 302 maintains regulated voltage V.sub.REG at a level that is sufficient to maintain the state of digital circuits in the event of a transient (i.e., relatively short) loss of power on power supply node 301 using a small, internal filter capacitor and a small, internal limiting resistor. Supply-glitch-tolerant regulator 302 does not require relatively large external capacitance and achieves regulation under nonideal circumstances without increased current consumption. Embodiments of a supply-glitch-tolerant voltage regulator will maintain sufficient power to analog and digital circuits in the event of a power supply glitch of a specified duration. The embodiments of a supply-glitch-tolerant voltage regulator do not require a large external capacitance and do not increase power consumption, as compared to a conventional voltage regulator.

[0020] The description of the invention set forth herein is illustrative and is not intended to limit the scope of the invention as set forth in the following claims. The terms “first,” “second,” “third,” and so forth, as used in the claims, unless otherwise clear by context, is to distinguish between different items in the claims and does not otherwise indicate or imply any order in time, location or quality. Variations and modifications of the embodiments disclosed herein may be made based on the description set forth herein, without departing from the scope of the invention as set forth in the following claims.