Amplitude Calibrated Oscillator Device

Abstract

An example oscillator device comprises (i) an oscillation circuit arranged for generating and outputting an oscillation signal and comprising an active circuit to ensure oscillation is maintained, (ii) a voltage-to-current conversion replica circuit of the active circuit arranged for receiving the oscillation signal and for outputting a current proportional to the oscillation signal, (iii) biasing means arranged to generate a constant bias current to activate the oscillation circuit, and (iv) subtraction means for subtracting the current proportional to the oscillation signal from the bias current, thereby obtaining a resulting current which can be used for adapting the oscillation signal's amplitude.

Claims

1. An oscillator device comprising: an oscillation circuit arranged for generating and outputting an oscillation signal and comprising an active circuit for maintaining oscillation of the oscillation signal; a voltage-to-current conversion replica circuit of the active circuit arranged for receiving the oscillation signal and for outputting a current proportional to the oscillation signal; biasing means arranged to generate a constant bias current to activate the oscillation circuit; and subtraction means for subtracting the current proportional to the oscillation signal from the bias current, thereby obtaining a resulting current which can be used for adapting an amplitude of the oscillation signal.

2. The oscillator device of claim 1, wherein the oscillation circuit further comprises a resonant tank.

3. The oscillator device of claim 1, wherein the active circuit comprises a differential transconductor.

4. The oscillator device of claim 1, wherein the oscillation circuit further comprises a second biasing means arranged for receiving the resulting current to bias the oscillator circuit.

5. The oscillator device of claim 4, wherein the resulting current is copied to the second biasing means via a first current mirror and a second current mirror.

6. The oscillator device as in claim 1, comprising a process, voltage, and temperature (PVT) read-out circuit arranged for receiving the resulting current and for outputting a biasing signal in accordance with the received resulting current to the oscillation circuit.

7. The oscillator device of claim 6, wherein the read-out circuit is arranged for deriving a digital code representative of the received resulting current and for generating the biasing signal in accordance with the digital code.

8. The oscillator device of claim 7, further comprising storage means for storing the digital code.

9. The oscillator device of claim 6, wherein the PVT read-out circuit comprises at least one of an ADC, a DAC, or a counter.

10. The oscillator device of claim 1, wherein the oscillator device is implemented as a class-C oscillator.

11. A frequency synthesizer circuit or clock and data recovery circuit comprising the oscillator device of claim 1.

12. A method comprising: generating and outputting, by an oscillation circuit, an oscillation signal, wherein the oscillation circuit comprises an active circuit for maintaining oscillation of the oscillation signal; receiving, by a voltage-to-current conversion replica circuit of the active circuit, the oscillation signal; outputting, by the voltage-to-current conversion replica circuit of the active circuit, a current proportional to the oscillation signal generating, by biasing means, a constant bias current to activate the oscillation circuit; and subtracting, by subtraction means, the current proportional to the oscillation signal from the bias current, thereby obtaining a resulting current; and using the resulting current to adapt an amplitude of the oscillation signal.

13. The method of claim 12, wherein the oscillation circuit further comprises a resonant tank, and wherein generating the oscillation signal comprises generating the oscillation signal using the resonant tank.

14. The method of claim 12, wherein the active circuit comprises a differential transconductor, and wherein maintaining oscillation of the oscillation signal comprises using the differential transconductor to maintain oscillation of the oscillation signal.

15. The method of claim 12, wherein the oscillation circuit further comprises a second biasing means, and wherein the method further comprises receiving and using, by the second biasing means, the resulting current to bias the oscillator circuit.

16. The method of claim 15, further comprising copying the resulting current to the second biasing means via a first current mirror and a second current mirror.

17. The method of claim 12, wherein using the resulting current to adapt an amplitude of the oscillation signal comprises: receiving, by a process, voltage, and temperature (PVT) read-out circuit, the resulting current; and outputting, by the PVT read-out circuit, a biasing signal in accordance with the received resulting current to the oscillation circuit.

18. The method of claim 17, further comprising: deriving, by the PVT read-out circuit, a digital code representative of the received resulting current; and generating, by the PVT read-out circuit, the biasing signal in accordance with the digital code.

19. The method of claim 18, further comprising storing the digital code in a data storage.

20. The method of claim 17, wherein the PVT read-out circuit comprises at least one of an ADC, a DAC, or a counter.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The disclosure will now be described further, by way of example, with reference to the accompanying drawings, wherein like reference numerals refer to like elements in the various figures.

[0028] FIG. 1 illustrates a block diagram of an oscillator device, according to an example embodiment.

[0029] FIG. 2 illustrates a practical implementation of the oscillator device, according to an example embodiment.

[0030] FIG. 3 illustrates a block diagram of an oscillator device with PVT readout circuit, according to an example embodiment.

[0031] FIG. 4 illustrates a practical implementation of the oscillator device with a PVT readout circuit, according to an example embodiment.

DETAILED DESCRIPTION

[0032] The present disclosure will be described with respect to particular embodiments and with reference to certain drawings but the disclosure is not limited thereto but only by the claims.

[0033] Furthermore, the terms first, second, and the like in the description and in the claims are used for distinguishing between similar elements and not necessarily for describing a sequence, either temporally, spatially, in ranking, or in any other manner. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the disclosure described herein are capable of operation in other sequences than described or illustrated herein.

[0034] It is to be understood that the term comprising, used in the claims, should not be interpreted as being restricted to the means listed thereafter; it does not exclude other elements or steps. It is thus to be interpreted as specifying the presence of the stated features, integers, steps, or components as referred to, but does not preclude the presence or addition of one or more other features, integers, steps, components, or groups thereof. Thus, the scope of the expression a device comprising components A and B should not be limited to devices consisting only of components A and B. It means that with respect to the present disclosure, the only relevant components of the device are A and B.

[0035] Reference throughout this specification to one embodiment or an embodiment means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, appearances of the phrases in one embodiment or in an embodiment in various places throughout this specification are not necessarily all referring to the same embodiment, but may. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner, as would be apparent to one of ordinary skill in the art from this disclosure, in one or more embodiments.

[0036] Similarly it should be appreciated that in the description of example embodiments of the disclosure, various features of the disclosure are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. This method of disclosure, however, is not to be interpreted as reflecting an intention that the claimed disclosure requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this disclosure.

[0037] Furthermore, while some embodiments described herein include some but not other features included in other embodiments, combinations of features of different embodiments are meant to be within the scope of the disclosure, and form different embodiments, as would be understood by those in the art. For example, in the following claims, any of the claimed embodiments can be used in any combination.

[0038] It should be noted that the use of particular terminology when describing certain features or aspects of the disclosure should not be taken to imply that the terminology is being re-defined herein to be restricted to include any specific characteristics of the features or aspects of the disclosure with which that terminology is associated.

[0039] In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the disclosure may be practiced without these specific details. In other instances, well-known methods, structures, and techniques have not been shown in detail in order not to obscure an understanding of this description.

[0040] An oscillator device comprises an oscillator circuit, which can include a passive resonant tank and an active circuit. The resonant tank resonates at a frequency determined by the time constant of the tank, while the active circuit compensates for the energy loss of the resonant tank so that resonance can be maintained. Once the resonance is excited and maintained, the circuit is oscillating.

[0041] The oscillation amplitude (swing) is determined by the supply voltage, transistor characteristics, oscillator topology, and biasing of the active circuit. Because of process, voltage, and temperature (PVT) variations, the amplitude of oscillation can be difficult to accurately predict. On the other hand, to meet the desired performance and power budget, it is useful to detect and control the oscillation amplitude at a predefined level.

[0042] Oscillator devices exhibit a trade-off between the output amplitude/swing level and phase noise. Indeed, low-phase-noise design can be achieved with either a high quality-factor resonator or a large signal swing. However, even though the latter is power hungry, an optimum phase-noise region can be found within a certain power consumption budget. This consideration has given birth to the class-C operation mode of an oscillator, where the active devices inject an impulse-like current to the resonator, while staying in the saturation (for MOS transistors) operating region and therefore facilitating operation in an improved and/or optimum phase-noise region with lower power consumption. However, such Class-C type oscillators require a start-up circuit to assure the start of the oscillations.

[0043] The present disclosure proposes an oscillator device for which a reference-free PVT calibration loop is implemented based on the oscillator output amplitude, so that the oscillator performance is improved and/or optimized and the PVT variations can be tracked.

[0044] In the ALC scheme applied in the oscillator device, an amplitude reference is built using a replica of the active devices in the oscillator circuit. The trade-off between the swing and phase noise is then naturally maintained in spite of PVT variations. The calibrated PVT information can be, in addition, used as a reference to improve and/or optimize the entire integrated circuit.

[0045] A generic scheme of a device according to this disclosure is shown in FIG. 1. In line with the discussion above, the oscillation device 100 comprises an oscillation circuit 10 with a passive resonant tank 11 and an active circuit 12. A level control scheme is obtained by adding a voltage-to-current conversion replica circuit 21 of the active devices in the oscillation circuit and biasing means 22. The oscillation device 100 operates in current-mode. The replica circuit 21 outputs a rectified current I.sub.sub which is proportional to the oscillation amplitude as explained below. The biasing means 22 in the oscillation device 100 provide a constant main bias current I.sub.ref. This is different from certain prior art schemes where a bias current with constant transconductance gm is considered instead. The current I.sub.sub is zero at start-up. The main bias current I.sub.ref is set high enough to ensure the oscillation starts up in all conditions. As shown in FIG. 1, the rectified current I.sub.sub is subtracted from the main bias current I.sub.ref. The resulting current I.sub.tail is then used to determine the optimum amplitude for a low phase noise output.

[0046] The scheme of FIG. 1 applies a self-biased or clamping-like control mechanism to limit the oscillation amplitude. A built-in reference is used rather than an external reference. The ALC scheme forces the oscillator to operate in the current limited region. As a current-mode design is adopted, the number of AC nodes in the circuit remains the same. Therefore, the stability is not degraded, in contrast to traditional feedback loops.

[0047] FIG. 2 illustrates a possible practical implementation of the generic scheme of the oscillator device 100 as shown in FIG. 1. A cross-coupled LC oscillator is used containing a passive resonance tank 11, which can be a parallel LC tank, and a differential transconductor 12 with a tail current source 13. The LC tank 11 resonates at the desired oscillation frequency, while the transconductor 12 compensates the LC tank loss so that the oscillation can be excited and maintained. The oscillator output signal approaches an ideal sinusoid wave at the resonance frequency. With ideal linear transconductors, the oscillation signal swing theoretically grows exponentially over time without bound, which means the oscillation signal swing will approach infinity as time elapses. In reality, due to non-linearity in transistors of the transconductor 12, the oscillation signal swing is limited by the voltage supply and bias conditions.

[0048] Various topologies can be considered for the transconductor 12: it can, for example, be built with NMOS transistors, PMOS transistors, or N- or P-type bipolar transistors. In FIG. 2 an implementation with NMOS cross-coupled transistors is shown. The current source transistor M3 provides tail current I.sub.tail to the NMOS transistors M1, M2. When oscillation starts, the oscillation amplitude at the output nodes of the oscillator outa, outb increases, and the signal levels on the NMOS transistors also increase, i.e., the gate-source voltage amplitudes on M1 and on M2 increase. Due to the non-linearity of the transistors M1 and M2, the gate-source voltage amplitude increases together with the oscillation amplitude. Therefore, an indication of the high frequency oscillation signal amplitude at the oscillator output is obtained at low frequency from the voltage level of the tail current used for biasing the active transistors.

[0049] FIG. 2 also indicates the biasing means 22, the voltage-to-current conversion replica circuit 21, and a current mirror 24. The oscillator outputs, nodes outa and outb, are connected to voltage-to-current conversion replica circuit 21, which converts the output voltage V.sub.out to a current I.sub.sub with amplitude proportional to the oscillator swing. The voltage at the oscillator output is provided to the source of transistors M1, M2 of the replica circuit 21. As the source voltage of transistors M1, M2 changes with the change of voltage swing at the oscillator output nodes, the current I.sub.sub flowing through them is varied, which thus realizes a voltage-to-current conversion.

[0050] The diode-mounted device M7 in the replica circuit 21 provides a static gate-source voltage V.sub.gs mimicking the one in the active part 12 of oscillator 100, i.e., at transistors M1, M2. The constant reference current source 22 generates a bias current I.sub.ref, which is then subtracted by the current I.sub.sub from the replica circuit 21 to output a resulting current. The subtraction is done at node 23. The resulting current is then copied via the current mirror 25 comprising transistors M5 and M6 and the current mirror 24 comprising transistors M4 and M3 to provide I.sub.tail to bias the oscillator via transistor M3. The resulting current I.sub.tail represents the difference between the main bias current I.sub.ref and the rectified current I.sub.sub (i.e., I.sub.tailI.sub.refI.sub.sub).

[0051] In addition, current mirror 24 comprises transistor M4, which copies the resulting current into the replica circuit 21 so that the replica circuit 21 is biased in the same manner as the oscillation circuit 10. The current I.sub.sub is initially equal to zero, and the reference current I.sub.ref is set so that the initial value of the I.sub.tail current ensures oscillator startup.

[0052] Once started, the oscillator output amplitude reaches its maximum, i.e., V.sub.outa=V.sub.gs+V.sub.amp. V.sub.amp thereby denotes the amplitude of the oscillator signal. The gate source voltage V.sub.gs represents the DC value at the oscillator output node, which through the current mirror 24 is similar to V.sub.gs of M7 (i.e., V.sub.gs,M7). The peak-to-peak voltage of the oscillator signal is proportional to the threshold voltage V.sub.th. For simplicity, V.sub.th is presumed to be the same for both M1 and M2 transistors. The output voltage level V.sub.out reflects the V.sub.th variation across PVT and can be used as a reference voltage for the ALC circuit.

[0053] One can therefore derive the following:

V.sub.outa=V.sub.gs,M2+V.sub.amp

V.sub.outb=V.sub.gs,M1V.sub.amp,

For V.sub.outa, V.sub.gs represents the DC value at the output node outa, which is equivalent to the V.sub.gs of M2. As M7 in the replica circuit 21 replicates M1 (M2) in the oscillator 10, the DC value of the V.sub.gs voltage of M7 is similar to V.sub.gs. The same applies for V.sub.outb, where V.sub.gs represents the DC value at the output node outb, which is equivalent to the V.sub.gs of M1, and hence also equivalent to the DC value of the V.sub.gs voltage of M7. Therefore, the currents I.sub.tail and I.sub.sub can be derived as follows:

I.sub.tail=I.sub.M1+I.sub.M2

I.sub.M1=f(V.sub.outbV.sub.th)=f(V.sub.gs,M1V.sub.thV.sub.amp)

I.sub.M2=f(V.sub.outaV.sub.th)=f(V.sub.gs,M2V.sub.th+V.sub.amp)

I.sub.sub=I.sub.M1+I.sub.M2

I.sub.M1=f(V.sub.gs,M7V.sub.outaV.sub.th)=f(V.sub.gs,M7V.sub.gs,M2V.sub.ampV.sub.th)=f(V.sub.ampV.sub.th)

I.sub.M2=f(V.sub.gs,M7V.sub.outbV.sub.th)=f(V.sub.gs,M7V.sub.gs,M1V.sub.ampV.sub.th)=f(V.sub.ampV.sub.th)

where V.sub.gs,M7 is a replica of V.sub.gs,M1 (and V.sub.gs,M2) and holds a similar value, thus they cancel each other in the above equations. M1 and M2 conduct alternatively and so do M1 and M2. Hence, when M1 and M1 are conducting, one obtains for I.sub.tail and I.sub.sub, respectively:

I.sub.tail=f(V.sub.gsV.sub.thV.sub.amp)

and at the same time

I.sub.sub=f(V.sub.ampV.sub.th).

A higher oscillator amplitude V.sub.amp leads to a lower I.sub.sub, which is subtracted from I.sub.ref. Through the current mirror, I.sub.tail starts to increase, thus increasing the oscillator amplitude V.sub.amp. When M2 and M2 are conducting one gets:

I.sub.tail=f(V.sub.gsV.sub.th+V.sub.amp)

and at the same time

I.sub.sub=f(V.sub.ampV.sub.th).

A higher oscillator amplitude V.sub.amp leads to a higher I.sub.sub, which is subtracted from I.sub.ref. Through the current mirror 24, I.sub.tail starts to reduce, thus reducing the oscillator amplitude V.sub.amp. In this way, a closed loop, reference-free amplitude level control is facilitated.

[0054] The proposed ALC scheme helps assure the amplitude of the oscillation signal is maintained so that an optimum trade-off between low phase noise and power consumption can be achieved. This ALC scheme applies to any class type oscillators. However, it also applies to class-C oscillators. For a class-C oscillator, the DC voltage at output of the oscillator should be lower than the threshold voltage of the active pair in oscillator. The proposed calibration scheme can start with the maximum current (I.sub.sub=0 in the very beginning), which gives a DC voltage at the gate of both M1 and M2 higher than V.sub.th,M1 and V.sub.th,M2. Therefore, the oscillator starts oscillation in a class-A/AB mode. With the help of the ALC scheme, the oscillator is regulated into class-C mode, meaning the DC voltage at the gate of M1 and M2 is lower than V.sub.th,M1 and V.sub.th,M2. This way the start-up of the Class-C oscillator is achieved without an extra start-up circuit.

[0055] FIG. 3 shows an example implementation of the oscillator device 100 of FIG. 1 but now with a PVT read-out circuit 30. The PVT readout block 30 extracts the end results of the amplitude calibration, which represent the optimum biasing current for the oscillator 10 in the form of a digital code (see PVT code). The digital code may be stored in a pre-set biasing block 40 for later use. After calibration, the calibration circuit 20 is shut down, while the oscillator 10 is biased with the stored PVT code converted to a biasing voltage via a DAC. By doing so, the current consumed by the calibration circuit 20 is saved during the normal operation of the oscillator 10, thus lowering the total power consumption of the whole implementation.

[0056] FIG. 4 shows a more detailed scheme of FIG. 3. The same functional blocks as in FIG. 2 can be recognized. The PVT readout circuit 30 comprises an ADC 31, a DAC 32, a counter 33, and switches S1 to S3 to switch on/off to different biasing schemes during different phases, divided into a calibration phase and an operation phase.

[0057] During the calibration phase, switches S1 and S2 are closed and switch S3 is open. The ALC block 20 regulates the oscillator current to the optimum point for phase noise performance and current consumption. The counter 33 works as a low frequency system clock and controls the timing. By the end of the calibration phase, the gate voltage of M3 (representing the optimum biasing voltage for M3) is read out via the ADC 31 and saved in a memory (not shown in FIG. 4) as a digital code (PVT code). At the end of the calibration phase, switches S1 and S2 are opened to switch off the calibration block 20 in order to save power.

[0058] During the operation phase, switch S3 is closed. This allows the saved PVT code to be read out from the memory and fed back via the DAC 32 to bias the oscillator 10.

[0059] The oscillator device of this disclosure employs a reference-free, automated PVT calibration loop, based on amplitude of the oscillator output, to track the PVT variations. The calibration loop is implemented as an amplitude level controller (ALC) for a class-C based oscillator, which is tuned to a current-voltage point optimized in view of the phase noise performance versus current consumption. The PVT corner calibration can so be embraced in the operational mode, before each PLL locking, and the oscillator can be automatically set to its optimal working point. Further, the proposed approach does not need a reference voltage level to calibrate the oscillator amplitude.

[0060] The oscillator device as described above can be used in various applications: frequency synthesizers employed in radio communication systems, clock and data recovery circuits used in wireline transceivers, voltage/digitally controlled oscillators (V/DCO) incorporated into a phase-locked-loop (PLL), etc.

[0061] While the disclosure has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative or exemplary and not restrictive. The foregoing description details certain embodiments of the disclosure. It will be appreciated, however, that no matter how detailed the foregoing appears in text, the disclosure may be practiced in many ways. The disclosure is not limited to the disclosed embodiments.

[0062] Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed disclosure, from a study of the drawings, the disclosure and the appended claims. In the claims, the word comprising does not exclude other elements or steps, and the indefinite article a or an does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage. A computer program may be stored/distributed on a suitable medium, such as an optical storage medium or a solid-state medium supplied together with or as part of other hardware, but may also be distributed in other forms, such as via the Internet or other wired or wireless telecommunication systems. Any reference signs in the claims should not be construed as limiting the scope.