Abstract
A method of incorporating Programmable Gain Amplifier (PGA) function into pipelined ADC for wide input range. The power consumption is saved without adding extra stage to reduce input range. The ADC input range can be adjusted on the fly using resistor bank and capacitor bank to achieve optimal system performance.
Claims
1. A Programmable Gain Amplifier (PGA) embedded pipelined ADC for wide input range, comprising: a configuration of 1PstP stage and 2PndP stage coupled together; a gain stage before the 1PstP stage Flash ADC; sampling capacitors in specific ratio; a shared OPAMP between two stages; and multiple associated switches operating in two clock phases, wherein one OPAMP amplifier is shared by two pipelined stages, the operating phase is determined by internal built-in switches of the amplifier, wherein two differential input pairs couples to one tail current source and one folded cascoded gain stage, each differential pair is enabled at specific clock phase.
2. The PGA embedded pipelined ADC of claim 1, wherein a specific portion of the sampling capacitors are connected to a common-mode voltage and other sampling capacitors are connected to inputs signal.
3. The PGA embedded pipelined ADC of claim 1, wherein the ratio of sampling capacitors can be programmed to adjust the input range for obtaining optimal ADC linearity performance.
4. The PGA embedded pipelined ADC of claim 1, wherein the gain stage before 1PstP stage Flash ADC can be programmed to adjust the input range for obtaining optimal ADC linearity performance.
5. The PGA embedded pipelined ADC of claim 1, wherein the gain stage is implemented using resistor divider, capacitor divider or R/C in parallel divider.
6. The PGA embedded pipelined ADC of claim 1, wherein the gain stage is implemented using adjustable resistor bank or adjustable capacitor bank to fine-tune the pipelined ADC input range on the fly for obtaining optimal system performance.
7. (canceled)
8. (canceled)
9. (canceled)
Description
BRIEF DESCRIPTION OF THE DRAWINGS
[0005] FIG. 1 illustrates a common block diagram of communication system-on-a-chip (SoC) integrated circuit.
[0006] FIG. 2 shows an advantageous feature that ADC operates on a lower power supply in system-on-a-chip integrated circuit.
[0007] FIG. 3 illustrates a gain amplifier is inserted before ADC to reduce input range.
[0008] FIG. 4 illustrates a Sample and Hold (S/H) is inserted before ADC to reduce input range.
[0009] FIG. 5 illustrates an exemplary block diagram of 12-bit pipelined ADC using 1.5b/stage scheme.
[0010] FIG. 6 presents the 1.sup.st and 2.sup.nd stage implementation of Programmable Gain Amplifier (PGA) embedded pipelined ADC using 1.5b/stage scheme.
[0011] FIG. 7 shows the circuit operation of FIG. 6 during clock phase ph1 enabled.
[0012] FIG. 8 shows the circuit operation of FIG. 6 during clock phase ph2 enabled.
[0013] FIG. 9 is the proposed 1.sup.st and 2.sup.nd stage implementation of Programmable Gain Amplifier (PGA) embedded pipelined ADC in a general configuration.
[0014] FIG. 10 illustrates the implementation of the gain stage before Flash ADC.
[0015] FIG. 11 illustrates the gain stage implementation using adjustable R/C banks.
[0016] FIG. 12 shows the built-in switch implementation of shared OPAMP between two pipelined stages.
DETAILED DESCRIPTION
[0017] The present invention will be described with respect to particular embodiments and with reference to certain drawings but the invention is not limited thereto but only by the claims. The drawings described are only schematic and are non-limiting.
[0018] The terms first, second, third and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the invention described herein are capable of operation in other sequences than described or illustrated herein.
[0019] Furthermore, it is to be noticed that the term comprising, used in the claims, should not be interpreted as being restricted to the means listed thereafter; it does not exclude other elements or steps. Thus, the scope of the expression a device comprising means A and B should not be limited to devices consisting only of components A and B. It means that with respect to the present invention, the only relevant components of the device are A and B.
[0020] Similarly, it is to be noticed that the term coupled discloses both direct and indirect coupling and should not be interpreted as being restricted to direct connections only. Thus, the scope of the expression a device A coupled to a device B should not be limited to devices or systems wherein an output of device A is directly connected to an input of device B. It means that there exists a path between an output of A and an input of B which may be a path including other devices or means.
[0021] FIG. 5 shows the common block diagram of 12 bit pipelined ADC using 1.5-bit/stage scheme. There are 11 stages pipelined and each stage generates two bits into digital error correction. Digital error correction combines all the bits together then aligns the timing and finally resolves 12 bit outputs. Odd stages and even stages are operating at different clock phases ph1 and ph2; when odd stages are performing sampling function the even stages are performing amplification then they are alternated on the next clock phase.
[0022] FIG. 6 shows the invented implementation of Programmable Gain Amplifier (PGA) embedded pipelined ADC. It illustrates the detailed circuitry of the first two stages of pipelined ADC using 1.5b/stage scheme. Note that the scheme of 1.5b per stage is depicted here for simplicity reason, however the other schemes such as 3 bit per stage or 4 bit per stage also applies. The first stage on the left consists of flash ADC 601, four sampling capacitors 602-605, and associated switches. The signal inputs are VIP/VIN and reference inputs are REFP/REFN and common-mode voltage VCM, the outputs of 1.sup.st stage are VOP1/VON1. The second stage consists of flash ADC 611, four sampling capacitors 612-615, and associated switches. The outputs of 2.sup.nd stages are VOP2/VON2. The OPAMP in each stage is actually one shared OP1 606. This shared OPAMP OP1 saves power consumption by using one OPAMP for two consecutive stages. There are internal built-in switches inside of OP1 606 to decide which stage is connected and perform amplification function. The differential inputs VIP/VIN, first stage outputs VOP1/VON1 and second stage outputs VOP2/VON2 are connected and coupled through switches. The clock phases ph1 and ph2 indicates the clock phase that the switches are turned on. The reference switches can be connected to REFP or REFN voltage depending on the Flash ADC's output.
[0023] FIG. 7 and FIG. 8 illustrate the operation of these two stages when clock phase ph1 and ph2 are enabled respectively. As shown in FIG. 7, first stage is performing sampling while the second stage is executing amplification when clock phase ph1 is enabled. Capacitor 703 and 705 are sampling the input voltages VIP/VIN. A gain stage 716 reduces the input amplitude by half before feeding inputs into Flash ADC1 701. The upper reference switch 716 and lower reference switch 717 are connected to REFP and REFN respectively given flash ADC2 output result. The internal switches inside of OP1 706 direct the OPAMP connection to the second stage, where the amplification function is executed through capacitor 712, 713, 714, 715 and OP1. The amplification gain is determined by the capacitor ratio of 713 and 712. In this exemplary case as 1.5b/stage scheme, capacitor 712 and 713 has the equal value. The total charge been sampled and stored by 1.sup.st stage capacitor is expressed as:
Q=C1*(VIPVIN)
Q is the total charge stored in the 1.sup.st stage sampling capacitor
(VIPVIN) is the difference voltage of inputs VIP, VIN
And the second stage output voltage is expressed as:
(VOP2VON2)=2*(VOP1VON2)+(REFPREFN)
[0024] The gain of 2 in the equation above arises because the input is sampled by two capacitors 712 and 713 during sample phase but only one capacitor 713 is in the feedback loop of the amplifier during amplification phase.
[0025] FIG. 8 illustrates the circuitry of another phase where clock phase ph2 is enabled. First stage is performing amplification while the second stage is executing sampling function. The internal switches of OP1 806 direct the OPAMP connection to the first stage. The amplification is carried out through capacitors 802, 803, 804, 805 and OP1. The amplification gain is determined by the capacitor ratio of 802 and 803. In this exemplary case of 1.5b/stage scheme, capacitor 802 and 803 has the same value. For the 2.sup.nd stage, both capacitors 812 and 813 samples the first stage output VOP1/VON. The total charge been sampled and stored by the 2.sup.nd stage capacitor is expressed as:
Q=2*(C2)*(VOP1VON1)
Q is the total charge stored in the 2.sup.nd stage sampling capacitor
(VOP1VON1) is the difference voltage of 1st stage outputs
And the first stage output voltage is expressed as:
(VOP1VON1)=1*(VIPVIN)+(REFPREFN)
Note that the differences between the first stage and the second stage are: [0026] (1) There is a 0.5 gain between 1st stage Flash ADC and the inputs. [0027] (2) The capacitor C1 of 1.sup.st stage samples VCM while the capacitor C2 of 2.sup.nd stage samples inputs, where VCM is a common-mode voltage.
These differences leads to the different equations described above for 1.sup.st stage and 2.sup.nd stage with respect to sampling and amplification phase. In particular, the 1.sup.st stage reduces the input range by adding a 0.5 gain 816 in FIG. 6 before the Flash ADC. And the sampling capacitor of 1.sup.st stage is only half of 2.sup.nd stage's sampling capacitor.
[0028] The proposed Programmable Gain Amplifier (PGA) embedded pipelined ADC can be implemented using 1.5b/stage scheme as shown in FIG. 6, which demonstrates that input range is reduced by half. Moreover, this proposed method can be applied to other architectures like 3b/stage, 4b/stage etc. FIG. 9 shows a proposed Programmable Gain Amplifier (PGA) embedded pipelined ADC in a general configuration. Only the first stage and 2.sup.nd stage circuitry are illustrated. It consists of Flash ADC 901, 911, sampling capacitors 902-905, 912-915 and one shared OPAMP OP1 906 and associated switches coupled together. The gain stage 916 comprises a gain value of A1 before sending input signal into Flash ADC 901. The sampling capacitors 902/904 and 903/905 can have different capacitance. The value of A1 and sampling capacitor values can be calculated depending on the how much input range reduction is required. The 1st stage output range is then expressed as:
[00001]
By incorporating a corresponding gain stage before 1.sup.st stage Flash ADC, the intended reduction ratio of the input range can be specified and implemented accordingly.
[0029] FIG. 10 illustrates the implementation of gain stage in FIG. 9. The gain stage can be formed by resistor divider, capacitor divider or RC in parallel divider depending on the input signal characteristic. With increasing complexity of system-on-a-chip (SoC), there are numerous variables or parameters affecting the overall system performance. It is advantageous to have the programmability that can adjust the input range of ADC for obtaining the optimal system performance. FIG. 11 illustrates the gain stage implementation using adjustable resistor banks and adjustable capacitor banks. This enables users to fine-tune the input range of ADC on the fly to achieve favorable system performance.
[0030] FIG. 12 illustrates the exemplary implementation of built-in switch of the shared OPAMP amplifier. The high gain amplifier consists of tail current 121, two differential input pairs 122, 123, folded-cascoded gain stage 124 and two sets of NMOS switches 125, 126. Two differential pairs 122, 123 are connected to 1.sup.st stage and 2.sup.nd stage in FIG. 6 respectively. Switches 125, 126 determine which differential pairs are enabled. The switches 125, 126 are arranged as common-gate configuration and the gates are controlled by different clock phase ph1/ph2. When 1.sup.st stage is performing amplification, ph1 is enabled and differential pair 122 is enabled accordingly. Incorporating the switch on top of the differential pair minimizes the associated net impedance, which enables amplifier to achieve favorable settling behavior.
[0031] By employing a PGA embedded pipelined ADC, ADC can operate at lower power supply and take larger input range. The overall system performance can be optimized by adjusting the ADC input range without power consumption penalty.
