Sigma-delta modulator

Abstract

A Sigma-Delta () modulator for converting an analog input signal having a frequency bandwidth around a variable center frequency f.sub.0 to a digital output signal at a sampling frequency f.sub.s. The modulator comprises a quantizer (420) for generating the digital output signal and a loop filter for shaping the quantization noise. The loop filter comprises at least one subfilter (430, 410) centered around a frequency f.sub.0 and constant noise shaping coefficients (451, 452, 453). The modulator further comprises a tunable delay element (455), a frequency adjuster (480) for adjusting the sampling frequency f.sub.s such that the normalized center frequency f.sub.0/f.sub.s is constant, and a delay adjuster (490) for adjusting the loop delay t.sub.d implemented by the quantizer and the tunable delay element (455), such that the normalized loop delay t.sub.d/T.sub.s falls in a predetermined range [t.sub.min, t.sub.max], where T.sub.s=1/f.sub.s.

Claims

1. A Sigma-Delta () modulator for converting an analog input signal having a frequency bandwidth around a variable center frequency f.sub.0 to a digital output signal at a sampling frequency f.sub.s, the modulator comprising a quantizer for generating the digital output signal, a loop filter for shaping the quantization noise, the loop filter comprising at least one subfilter centered around a frequency f.sub.0, and noise shaping coefficients, the modulator being characterized in that: the noise shaping coefficients are constant and independent of the center frequency f.sub.0; the modulator further comprises a tunable delay element; a frequency adjuster for adjusting the sampling frequency f.sub.s such that the normalized center frequency f.sub.0/f.sub.s is constant; a delay adjuster for adjusting the loop delay t.sub.d implemented by the quantizer and the tunable delay element, such that the normalized loop delay t.sub.d/T.sub.s falls in a predetermined range [t.sub.min, t.sub.max], where T.sub.s=1/f.sub.s.

2. The modulator according to claim 1, wherein the predetermined range [t.sub.min, t.sub.max] is independent on the center frequency f.sub.0 and the loop delay t.sub.d is adjusted to a value that is a function of the center frequency f.sub.0 and the sampling frequency f.sub.s.

3. The modulator according to claim 1, wherein t.sub.min=t.sub.max.

4. The modulator according to claim 1, wherein the tunable delay element comprises a plurality of cascaded latches and the delay adjuster is configured to adjust the loop delay t.sub.d to a number of half of a clock period of a clock signal controlling the plurality of cascaded latches.

5. The modulator according to claim 4, the delay adjuster is configured to send to each latch of the plurality of cascaded latches a clock signal selected from the group comprising the clock signal and the inversed clock signal.

6. The modulator according to claim 1, wherein the tunable delay element is a programmable delay element and delay adjuster is a circuit for programming the programmable delay.

7. A Sigma-Delta Analog-to-Digital converter ( ADC) comprising a Sigma-Delta modulator according to claim 1.

8. A telecommunication device comprising a radio interface for receiving a radio signal and an Analog-to-Digital converter according to claim 7 for converting the radio signal to a digital signal.

9. A method for converting an analog input signal having a frequency bandwidth around a variable center frequency f.sub.0 to a digital output signal at a sampling frequency f.sub.s by a Sigma-Delta () modulator, the modulator comprising a quantizer and a loop filter for shaping the quantization noise, the loop filter comprising at least one subfilter centered around frequency f.sub.0 and noise shaping coefficients, the method comprising, processing by the modulator said analog input signal for generating said digital output signal, the method being characterized in that: the processing is performed using constant noise shaping coefficients which are independent of the center frequency f.sub.0; the modulator further comprises a tunable delay element; and in that the method further comprises: adjusting the sampling frequency f.sub.s such that the normalized center frequency f.sub.0/f.sub.s is constant, adjusting the loop delay t.sub.d implemented by the quantizer and the tunable delay element, such that the normalized loop delay t.sub.d/T.sub.s falls in a predetermined range [t.sub.min, t.sub.max], where T.sub.s=1/f.sub.s.

10. The method according to claim 9, wherein t.sub.min=t.sub.max.

11. The modulator according to claim 2, wherein t.sub.min=t.sub.max.

12. The modulator according to claim 2, wherein the tunable delay element comprises a plurality of cascaded latches and the delay adjuster is configured to adjust the loop delay t.sub.d to a number of half of a clock period of a clock signal controlling the plurality of cascaded latches.

13. The modulator according to claim 3, wherein the tunable delay element comprises a plurality of cascaded latches and the delay adjuster is configured to adjust the loop delay t.sub.d to a number of half of a clock period of a clock signal controlling the plurality of cascaded latches.

14. The modulator according to claim 2, wherein the tunable delay element is a programmable delay element and delay adjuster is a circuit for programming the programmable delay.

15. The modulator according to claim 3, wherein the tunable delay element is a programmable delay element and delay adjuster is a circuit for programming the programmable delay.

16. The modulator according to claim 4, wherein the tunable delay element is a programmable delay element and delay adjuster is a circuit for programming the programmable delay.

17. The modulator according to claim 5, wherein the tunable delay element is a programmable delay element and delay adjuster is a circuit for programming the programmable delay.

18. A Sigma-Delta Analog-to-Digital converter ( ADC) comprising a Sigma-Delta modulator according to claim 2.

19. A Sigma-Delta Analog-to-Digital converter ( ADC) comprising a Sigma-Delta modulator according to claim 3.

20. A Sigma-Delta Analog-to-Digital converter ( ADC) comprising a Sigma-Delta modulator according to claim 4.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Other advantages and characteristics of the disclosed devices and methods will become apparent from reading the description, illustrated by the following figures, in which like reference numerals refer to similar elements:

(2) FIG. 1, already described, is a schematic representation of an embodiment of a highly digitized RF receiver;

(3) FIG. 2, already described, is a schematic representation of an embodiment of a tunable modulator;

(4) FIG. 3A-3C, already described, represent curves of quantization noise at different center frequencies for an embodiment of a tunable modulator according to the prior art;

(5) FIG. 4 is a schematic representation of an embodiment of a tunable modulator according to the present disclosure;

(6) FIG. 5 is a schematic representation of an embodiment of a tunable modulator according to the present disclosure;

(7) FIG. 6 represent curves of quantization noise of a tunable modulator according to the present disclosure;

(8) FIG. 7 is a schematic representation of an embodiment of the quantizer and the tunable delay element;

(9) FIG. 8 is a curve that illustrates the Signal-to-Noise Ratio degradation of a modulator with respect to the normalized loop delay;

(10) FIG. 9 is a schematic representation of an embodiment of a tunable modulator according to the present disclosure;

(11) FIG. 10 is a flowchart of an embodiment of a method according to the present disclosure.

DETAILED DESCRIPTION

(12) Several embodiments of a ADC will be described in detail by reference to the figures.

(13) FIG. 4 is a schematic representation of an embodiment of a ADC 400 according to the present disclosure. The ADC 400 converts an analog input signal 401 having a frequency bandwidth around a variable center frequency f.sub.0 to a digital output signal 422 at a sampling frequency f.sub.s. The ADC 400 is a circuit that comprises a loop including a forward path 460 for generating the digital output signals 421 and 422 from the analog input signal 401 and a feedback path 470 for generating from the delayed digital output signal 422 one or more feedback signals 403, 404, 405 feeding the forward path. The ADC 400 may be used for implementing the ADC 11 of a RF receiver 100 described by reference to FIG. 1.

(14) The loop comprises a loop filter including one or more subfilters 410, a tunable delay element 455 and one or more DACs 451, 452. In the embodiment illustrated by FIG. 4, the forward path 460 comprises a first subfilter 430, a second subfilter 410, an adder 440, a quantizer 420 and a tunable delay element 455. The quantizer 420 comprises a comparator (for example, an edge-triggered D-Flip-Flop) and one or more latches (not represented). The first subfilter 430 generates a signal 431 from the analog input signal 401 and the feedback signal 403. The second subfilter 410 generates a signal 411 from the analog signal 431 and the feedback signal 405. The adder 440 generates a difference signal 441 as the difference between the filtered signal 411 and the feedback signal 404. The quantizer 420 generates from the difference signal 441 a first digital signal 421 at the sampling frequency f.sub.s. The second digital output signal 422 is a delayed version of the digital signal 421.

(15) The loop delay, t.sub.d, is here defined as the sum of the fixed time delay, t.sub.q, introduced by the quantizer 420 and the variable time delay t.sub.var introduced by the tunable delay element 455. The order of the loop filter can be increased by adding more subfilters between the subfilter 410 and the adder 440.

(16) The feedback path further comprises the DACs 451, 452, 453 used to convert the digital output signal 422 to the analog domain before feeding the forward path. The DACs 451, 452, 453 generate the feedback signals 403, 404, 405 respectively. The coefficients of the filters of the DACs 451, 452, 453 are noise-shaping coefficients for shaping the quantification noise. The noise-shaping coefficients are constant. More precisely the noise-shaping coefficients are independent of the center frequency and therefore do not change when the center frequency varies. The transfer function of the loop filter depends on the transfer functions of the subfilter(s) 410, 430, the tunable delay element 455 and the DACs 451, 452, 453.

(17) The ADC 400 further comprises a frequency adjuster 480 for adjusting the sampling frequency f.sub.s of the quantizer 420 as a function of the center frequency f.sub.0. In one or more embodiments, the frequency adjuster 480 is implemented by using a PLL (Phase Locked Loop).

(18) In one or more embodiments, the frequency adjuster 480 is configured to adjust the sampling frequency f.sub.s such that the normalized center frequency f.sub.s/f.sub.0 is constant and equal to a predetermined value. More precisely, for a given ADC, the normalized center frequency f.sub.s/f.sub.0 is fixed to a predetermined value which is independent of the center frequency f.sub.0 and therefore does not change when the center frequency varies. Or, to say it another way, the sampling frequency f.sub.s is a linear function of the center frequency f.sub.0.

(19) In one or more embodiments, the normalized center frequency f.sub.s/f.sub.0 is equal to 4. Using a normalized center frequency equal to 4 enables to reduce the complexity of the digital part of an RF receiver 100 represented on FIG. 1. In fact, when sampling a sinusoidal wave w(t)=sin(2f.sub.0t) of frequency f.sub.0 at a sampling frequency f.sub.s equal to f.sub.s=4f.sub.0 generates 4 samples at t=0, 1/f.sub.s, 2/f.sub.s, 3/f.sub.s corresponding respectively to w(0)=0; w(1/fs)=w(/2)=1; w(2/fs)=w()=0; and w(3/fs)=w(3/2)=1. The 4 samples may thus be coded on a low number of bits, e.g. on 1 bit. The decimation filters 13 and 18 may thus be simplified accordingly.

(20) In one or more embodiments, the center frequencies of the subfilters 410 are tuned to the desired center frequency f.sub.0 of the ADC. These subfilters may comprise active resonators based on operational amplifier(s) or LC-based passive resonators. In one or more embodiments, the normalized center frequency, f.sub.s/f.sub.0, and the normalized loop delay, td/Ts, are kept constant. This is achieved by adjusting the sampling frequency, f.sub.s, using the frequency adjuster 480, and by adjusting the loop delay, td, using the delay adjuster 490. The noise shaping coefficients are constant. In FIG. 4, we show one technique to realize the noise-shaping coefficients using the feedback DACs 451, 452, 453. These DACs are usually realized using a switched current source where the value of the current source determines the value of the noise-shaping coefficient. The noise-shaping coefficients may also be realized using FIRDACs, feedforward coefficients or a combination of all these techniques.

(21) While FIG. 4 illustrates an example of an embodiment of a ADC with the tunable delay element in the forward path, the tunable delay element may be in the forward path and/or in the feedback path.

(22) FIG. 5 is a schematic representation of an embodiment of a ADC 500 according to the present disclosure. The ADC 500 includes elements that are identical or similar to those of the ADC 400 of FIG. 4 and are identified by the same reference numbers: these elements will not be described again. Only additional details or differences will be described. The loop filter of the ADC 500 comprises one or more subfilters 410, 430, a tunable delay element 455 and one or more DACs 451, 452, 453.

(23) The subfilter 430 may include a resonator and an adder for generating a difference signal from the analog input signal 401 and the feedback signal 403. The subfilter 430 generates a filtered signal 431.

(24) The subfilter 410 may include a resonator and an adder for generating a difference signal from the filtered signal 431 and the feedback signal 405. The subfilter 410 generates a filtered signal 411.

(25) The DAC 451 generates the feedback signal 403 for feeding the subfilter 430. In the embodiment represented on FIG. 5, the DAC 451 has one or more noise shaping coefficients m.sub.0 to m.sub.i.

(26) The DAC 453 generates the feedback signal 405 for feeding the subfilter 410. In the embodiment represented on FIG. 5, the DAC 453 has one or more noise shaping coefficients i.sub.0 to i.sub.j.

(27) The DAC 452 generates the feedback signal 404 for the adder 440. In the embodiment represented on FIG. 5, the DAC 452 has one or more noise shaping coefficients c.sub.0 to c.sub.k.

(28) While FIG. 5 shows an example of an embodiment of a ADC with noise shaping coefficients in the feedback path, the noise shaping coefficients may be implemented in the forward path and/or in the feedback path.

(29) FIG. 6 illustrates the shape of power spectral density (PSD) curve of the quantization noise as a function of the input signal frequency. The desired frequency band 600 of the analog input signal 401 is assumed to be centered around the center frequency f.sub.01 equal to f.sub.s/4. Those curves illustrate the fact, that when the normalized center frequency is constant, i.e. fixed to a predetermined value, the shape of the power spectral density (PSD) of the quantization noise is also constant. As a consequence, the noise shaping coefficients of ADC are constant. These noise shaping coefficients are constant whether they are implemented in the feedforward or in the feedback path. These noise shaping coefficients need not to be adjusted when the center frequency f.sub.0 varies. However the center frequencies of the subfilters 430, 410 still need to be adjusted to desired frequency band 600. As an example, referring back to FIG. 5, for a desired center frequency, the center frequencies of the subfilters 430, 410 and the sampling frequency, fs, are adjusted using the frequency adjuster 480, and the loop delay, td, is adjusted using the delay adjuster 490 but the noise shaping coefficients m.sub.0 to m.sub.i, i.sub.0 to i.sub.j, c.sub.0 to c.sub.k, implemented, in this embodiment, by the feedback DACs 451, 453, 452 are constant.

(30) The tunable delay element 455 is an adjustable delay. In one or more embodiments, the ADC 400 further comprises a delay adjuster 490 for adjusting the loop delay t.sub.d of the loop of the ADC 400. The loop delay, t.sub.d, is here defined as the sum of the fixed time delay, t.sub.q, introduced by the quantizer 420 and the variable time delay t.sub.var introduced by the tunable delay element 455.

(31) In one or more embodiment, the loop delay, t.sub.d, is adjusted as a function of the sampling frequency, f.sub.s, such that the normalized loop delay, t.sub.d/T.sub.s, falls in a predetermined range Rd=[t.sub.min, t.sub.max], where T.sub.s=1/f.sub.s. The predetermined range Rd=[t.sub.min, t.sub.max] may be such that t.sub.min=t.sub.max, thus keeping the normalized loop delay, t.sub.d/T.sub.s fixed.

(32) The adjustment of the loop delay, t.sub.d, may be performed in different ways. In one or more embodiments, the tunable delay element 455 is a programmable delay and the delay adjuster is a circuit for programming the programmable delay.

(33) The document entitled A Low Power Tunable Delay Element Suitable for Asynchronous Delays of Burst Information, by Schell et al, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 5, MAY 2008, describes embodiments of a tunable delay element suitable for implementing the tunable delay element 455 of the ADC 400. The technique proposed in this paper is rather complex and requires a large area and power consumption. In the following, we propose a simple technique to adjust the loop delay so that the normalized loop delay falls within a predetermined range where the SNR degradation is insignificant.

(34) In one or more embodiments, the quantizer 420 and the tunable delay element 455 comprises a plurality of cascaded latches.

(35) FIG. 7 illustrates embodiments of the quantizer 420 and the tunable delay element 455 using cascaded latches.

(36) In one or more embodiments, the quantizer 420 comprises a preamplifier 423 followed by a fixed number M of cascaded latches LF.sub.1, LF.sub.2, . . . , LF.sub.M, connected in series, and clocked by a clock signal at frequency f.sub.s. The clock signal clk used for controlling the latches (LF.sub.1-LF.sub.M) is the sampling signal at frequency f.sub.s.

(37) The delay t.sub.q=(M1) (Ts/2) implemented by the quantizer 420 is a fixed multiple of half the sampling period. Cascaded latches (LF.sub.1-LF.sub.M) of the quantizer are successively toggled clocked to the one another. For example, if the quantizer 420 comprises M=3 latches LF.sub.1, LF.sub.2, LF.sub.3, then the latches LF.sub.1 and LF.sub.3 are controlled by the clock signal while the latch LF.sub.2 is controlled by the inversed clock signal.

(38) In one or more embodiments, the tunable delay element 455 comprises a plurality of P cascaded latches LV.sub.1, LV.sub.2, . . . , LV.sub.P, connected in series followed by an inverter 457. The latches (LV.sub.1-LV.sub.P) are clocked by a clock signal at frequency f.sub.s. The clock signal clk used for controlling the latches (LV.sub.1-LV.sub.P) is the sampling signal at frequencyf,

(39) The delay t.sub.var=P (Ts/2) implemented by the tunable delay element 455 is variable multiple of half the sampling period. The cascaded latches (LV.sub.1-LV.sub.P) of the tunable delay element 455 may be either identically clocked or toggled clocked. Two cascaded latches having toggled clock have a half clock cycle (Ts/2) as delay. On the other hand, two cascaded latches having identical clock has theoretically zero delay.

(40) Each latch of the plurality of latches LV.sub.1-LV.sub.P receives a control signal clk which is either the clock signal or the inversed clock signal. By alternating from one latch LV.sub.i to the next one LV.sub.i+1 in the series the selection of the clock signal, the delay t.sub.i implemented by each latch of the tunable delay element 455 is equal to half of the sampling period T.sub.s/2=1/2f.sub.s. The time delay t.sub.var implemented by the tunable delay element 455 is thus equal to P (Ts/2).

(41) On the contrary, by feeding the latches only with the clock signal, the delay t.sub.i implemented by each latch of the tunable delay element 455 is (theoretically) equal to zero. The time delay t.sub.var implemented by the tunable delay element 455 is thus equal 0.

(42) The time delay t.sub.var implemented by the tunable delay element 455 may thus be adjusted between t.sub.var1=0 and t.sub.var2=P (Ts/2) by selectively sending either the clock signal or the inversed clock signal to each latch LV.sub.1, LV.sub.2, . . . , LV.sub.P. For example, if P=4 toggled latches are implemented, the time delay t.sub.var may be adjusted between t.sub.var10 and t.sub.b2=2T.sub.s.

(43) The delay adjuster 490 is configured to send to each latch of the plurality of latches LV.sub.1, LV.sub.2, . . . , LV.sub.P a control signal which is either the clock signal or the inversed clock signal. Unlike the latches of the quantizer 420, the clock signal used for controlling the latches LV.sub.1 to LV.sub.P of the tunable delay element 455 may vary upon time, in particular with the sampling frequency f.sub.s and the center frequency f.sub.0.

(44) In one or more embodiments, the number of toggled latches in the tunable delay element 455 may be adjusted in order to get a ADC 400 usable for other frequencies ranges.

(45) According to the embodiment of FIG. 7, the loop delay t.sub.d of the ADC 400 is implemented by a series of N=M+P toggled latches of the quantizer 420 and the tunable delay element 455. The maximum loop delay t.sub.d is in theory:
t.sub.dmax=(N1)T.sub.s/2.

(46) In practical implementation, the loop delay t.sub.d of ADC 400 is
t.sub.dmax=(N1)T.sub.s/2+t.sub.

(47) where t.sub.=t.sub.reg+t.sub.inverter+t.sub.DAC, where t.sub.reg is the regeneration time of the last latch of the tunable delay element 455, t.sub.inverter is the time delay due to the inverter 457 of the tunable delay element 455 and t.sub.DAC is the time delay of the Digital-to-Analog converters 451, 452, 453 in the feedback path.

(48) The normalized loop delay is thus:
t.sub.d/Ts=(N1)/2+t.sub./Ts

(49) While the first part of the normalized loop delay (N1)/2 is well-defined, independent of the sampling period Ts and independent of process parameters, the other part t.sub./Ts is generally uncontrollable, dependent on the sampling period Ts.

(50) FIG. 8 shows a curve that illustrates the variations of Signal-to-Noise Ratio (SNR) of an ADC 500 as a function of the normalized loop delay t.sub.d/T.sub.s. This curve results from simulations performed for a given architecture and sampling frequency f.sub.s. As can be seen from the shape of this curve, there is no or little SNR degradation when the normalized loop delay t.sub.d/T.sub.s is in the range R.sub.d=[t.sub.min, t.sub.max] around a nominal loop delay t.sub.nom. In one or more embodiment, the range Rd=[t.sub.min, t.sub.max] is equal to [1.2; 1.7] and t.sub.nom=1.5. In order to compensate for the variations of the normalized loop delay, the time delay t.sub.var of the tunable delay element 455 may be adjusted so that the normalized loop delay of the ADC 500 is maintained within the range Rd=[t.sub.min, t.sub.max]=[1.2; 1.7]. Accordingly, the ADC 500 achieves the same SNR when the loop delay t.sub.d varies between 1.2 Ts and 1.7 Ts.

(51) FIG. 9 is a schematic representation of an embodiment of a ADC 900 according to the present disclosure. This embodiment may be performed using CMOS technology. The overall design is optimized for the nominal loop delay t.sub.nom. The reported ADC is optimized and its noise shaping coefficients are calculated for a loop filter with a nominal loop delay t.sub.nom=1.5 Ts. As illustrated by FIG. 9, the number of noise shaping coefficients of the DAC 452 may be reduced to a single feedback coefficient. The ADC 900 may be composed of an LC filter 451, a single bit comparator 420, a tunable delay element 455 and a Non-Return-to-Zero (NRZ) feedback DAC 452. The LC filter 451 may be composed of an input transconductance, Gin and an LC tank. The input transconductance Gin converts the input voltage to current enabling current summation at the feedback node. The LC tank is composed of a differential inductor, two capacitor banks and a negative transconductance, Gmq.

(52) The table below illustrates how the normalized loop delay varies with the sampling frequency f.sub.s depending on the total number N=P+M of latches that is used in the quantizer 420 and in the tunable delay element 455 of the ADC 500. In this table, M=2, P=2 and N=P+M=4. The number of toggled latches varies from M=2 to N=4.

(53) TABLE-US-00001 Sampling Normalized loop delay Frequency (GHz) 2 Latches*** 3 Latches** 4 Latches* 2.0 0.7 1.2 1.7 3.0 0.8 1.3 1.8 4.0 0.9 1.4 1.9 5.0 1.0 1.5 2.0 6.0 1.1 1.5 2.1 7.0 1.2 1.7 2.2 8.0 1.3 1.8 2.3 9.0 1.4 1.9 2.4 10.0 1.5 2.0 2.5 11.0 1.6 2.1 2.6 12.0 1.7 2.2 2.7 *all consecutive latches are toggled **the last 2 latches are not toggled ***the last 3 latches are not toggled

(54) In order to reach high sampling frequencies in the GHz range these latches are implemented using the Source Coupled Logic (SCL) technique. In the case of 2 latches, the normalized loop delay t.sub.d/T.sub.s is within the range Rd=[t.sub.min, t.sub.max]=[1.2; 1.7] when the sampling frequency is between 7 GHz and 12 GHz. In this case, the normalized loop delay t.sub.d/T.sub.s is lower than t.sub.min when the sampling frequency is below 7 GHz. In the case of 3 latches, the normalized loop delay t.sub.d/T.sub.s is within the range Rd=[t.sub.min, t.sub.max]=[1,2; 1,7] when the frequency is between 2 GHz and 7 GHz and higher than t.sub.max when the sampling frequency is above 7 GHz. With 4 latches, the normalized loop delay t.sub.d/T.sub.s is within the range Rd=[t.sub.min, t.sub.max]=[1,2; 1,7] when the frequency is 2 GHz. In this case, the normalized loop delay t.sub.d/T.sub.s is higher than t.sub.max when the sampling frequency is above 2 GHz.

(55) This table illustrates the fact that the adjustment of loop delay may be performed so that the normalized loop delay falls within the appropriate range Rd=[t.sub.min, t.sub.max]=[1.2; 1.7]. The adjustment of the normalized loop delay may be performed by adjusting the time delay t.sub.var of the tunable delay element 455. The adjustment may b performed so that the SNR degradation is below a given threshold.

(56) In one or more embodiments, the delay adjuster 490 is configured to adjust the delay t.sub.var of the tunable delay element 455 to a predetermined number of half of a clock period of the clock signal. The number of latches that is used is dependent on the desired range for sampling frequency f.sub.s. For example, the number of latches is equal to N=4 with M=2 latches in the quantizer 420 and P=2 latches in the tunable delay element 455 so as to cover the range of sampling frequency from 2 GHz to 12 GHz. For a selected number of latches, the normalized loop delay may further be adjusted are described previously.

(57) FIG. 10 shows the steps of an embodiment of a method for converting an analog input signal having a radiofrequency bandwidth around a variable center frequency f.sub.0 to a digital output signal at a sampling frequency f.sub.s. The conversion is implemented by a Sigma-Delta () modulator according to the present disclosure. The modulator comprises a loop with a forward path and a feedback path. The loop comprises a quantizer and a loop filter. The loop filter comprises one or several subfilters centered around frequency f.sub.0, a tunable delay element 455 and noise shaping coefficients that may be in the forward path or in the feedback path. While the various steps in these flowcharts are presented and described sequentially, some or all of the steps may be executed in different orders, may be combined or omitted, and some or all of the steps may be executed in parallel.

(58) In one or more embodiment the method comprises a step 1005 of adjusting the center frequency f.sub.0 of the subfilters. The adjustment is usually performed by a digital control signal.

(59) In one or more embodiment the method comprises a step 1010 of adjusting the sampling frequency f.sub.s such that the normalized center frequency f.sub.0/f.sub.s is constant.

(60) In one or more embodiment the method comprises a step 1020 of adjusting the loop delay t.sub.d implemented by the quantizer (420) and the tunable delay element (455), such that the normalized loop delay t.sub.d/T.sub.s falls within a predetermined range [t.sub.min, t.sub.max], where T.sub.s=1/f.sub.s. The adjustment may be performed according to the embodiments described by reference to FIG. 7 or 9.

(61) The method further comprises a step 1050 of generating by the loop filter the digital output signal from the analog input signal. The noise shaping coefficients of the loop filter are constant and independent of the center frequency f.sub.0. The step 150 may include a step of generating a difference signal from the analog input signal and a feedback signal generated by the feedback path; a step of filtering the difference signal by at least one subfilter and a step of generating the digital output signal by the quantizer.

(62) In one or more embodiment the filtering is performed by at least one subfilter having a transfer function with a tunable center frequency f.sub.0.

(63) Although described by way of a number of detailed example embodiments, the Sigma-Delta modulator according to the present description comprises various variants, modifications and improvements that will be obvious to those skilled in the art. It is understood that these various variants, modifications and improvements fall within the scope of the disclosed devices or methods such as defined by the following claims.