Negative feedback gain transimpedance amplifier (TIA) systems

Abstract

One embodiment describes a transimpedance amplifier (TIA) system. The system includes a transistor arranged between an input node and an output node to set an amplitude of an output voltage at the output node based on an amplitude of an input current signal provided at the input node. The system also includes a negative feedback transformer coupled to the transistor to provide a negative feedback gain with respect to the output voltage to substantially increase transconductance of the transistor.

Claims

1. A transimpedance amplifier (TIA) system comprising: a transistor arranged between an input node and an output node to set an amplitude of an output voltage at the output node based on an amplitude of an input current signal provided at the input node; a negative feedback transformer coupled to the transistor to provide a negative feedback gain with respect to the output voltage to substantially increase transconductance of the transistor; and a resistor coupled between the output node and a high rail voltage; wherein the negative feedback transformer comprises a primary winding that is coupled to the input node and a secondary winding that is coupled between an input of the transistor and a bias voltage such that the transistor is controlled by the bias voltage via the secondary winding; wherein the high rail voltage and the bias voltage are different.

2. The system of claim 1, wherein the transistor is controlled by the bias voltage.

3. The system of claim 1, wherein the transistor is arranged as an N-channel metal-oxide semiconductor field-effect transistor (MOSFET) comprising a source coupled to the input node and a drain coupled to the output node.

4. An optical receiver comprising the TIA system of claim 1.

5. The optical receiver of claim 4, further comprising a photodiode to generate the input current signal as an input current in response to an input optical signal.

6. An integrated circuit (IC) chip comprising the TIA system of claim 1.

7. A transimpedance amplifier (TIA) system comprising: a transistor arranged between an input node and an output node to set an amplitude of an output voltage at the output node based on an amplitude of an input current signal provided at the input node; and a negative feedback transformer comprising a primary winding that is coupled to the input node and a secondary winding that is coupled between an input of the transistor and a bias voltage to provide a negative feedback gain with respect to the output voltage to substantially increase transconductance of the transistor, and such that the transistor is controlled by the bias voltage via the secondary winding; and a resistor coupled between the output node and a high rail voltage; wherein the high rail voltage and the bias voltage are different.

8. The system of claim 7, wherein the transistor is controlled by the bias voltage via the secondary winding.

9. The system of claim 8, wherein the transistor is arranged as an N-channel metal-oxide semiconductor field-effect transistor (MOSFET) comprising a source coupled to the input node and a drain coupled to the output node.

10. An optical receiver comprising the TIA system of claim 7, the optical receiver further comprising a photodiode to generate the input current signal in response to an input optical signal.

11. An optical receiver system comprising a transimpedance amplifier (TIA) system, the TIA system comprising: a photodiode to receive an optical input signal and to generate an input current signal in response to the optical input signal; a transistor arranged between an input node and an output node to set an amplitude of an output voltage at the output node based on an amplitude of the input current signal provided at the input node; a negative feedback transformer comprising a primary winding that is coupled to the input node and a secondary winding that is coupled between an input of the transistor and a bias voltage to provide negative feedback gain with respect to the output voltage to substantially increase transconductance of the transistor, and such that the transistor is controlled by the bias voltage via the secondary winding; and a resistor coupled between the output node and a high rail voltage; wherein the high rail voltage and the bias voltage are different.

12. The system of claim 11, wherein the transistor is arranged as an N-channel metal-oxide semiconductor field-effect transistor (MOSFET) comprising a source coupled to the input node and a drain coupled to the output node.

13. An integrated circuit (IC) chip comprising the TIA system of claim 11.

14. An integrated circuit (IC) chip comprising the TIA system of claim 7.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 illustrates an example of a transimpedance amplifier system.

(2) FIG. 2 illustrates an example of a transimpedance amplifier circuit.

DETAILED DESCRIPTION

(3) A transimpedance amplifier (TIA) system disclosed herein employs a negative feedback transformer that is configured to provide passive negative-feedback gain to enhance the effective transconductance of the input common-gate transistor of the TIA system. As a result, the input resistance of the TIA system can be reduced. In addition, the TIA system can be implemented in an optical receiver system that includes a photodiode configured to generate a current input signal based on an intensity of an optical signal. In this example receiver system, the negative feedback transformer can be further configured to isolate parasitic capacitance associated with the photodiode. The TIA system thus allows for considerable bandwidth extension without significant noise degradation or power consumption, in contrast to traditional transistor-based regulated cascode architectures.

(4) FIG. 1 illustrates an example of a TIA system 10. The TIA system 10 can be implemented in a variety of applications, including an optical receiver system. The TIA system 10 is configured to amplify an input current signal, demonstrated in the example of FIG. 1 as a current I.sub.IN, to generate an output voltage signal V.sub.OUT.

(5) The TIA system 10 includes an input stage 12 and a negative feedback transformer 14. As an example, the input stage 12 can be configured as a common-gate transistor arrangement that is configured to convert the current input signal I.sub.IN that is received at an input node 16 to the output voltage signal V.sub.OUT that is provided at an output node 18. The input current signal I.sub.IN can be generated from a variety of sources, such as a photodiode in an optical receiver system. The input stage 12 can be arranged between a high voltage rail, demonstrated as a voltage V.sub.DD, and a low voltage rail, demonstrated as ground. Therefore, the input stage 12 can convert the amplitude of the input current signal I.sub.IN to a corresponding amplitude of the output voltage signal V.sub.OUT.

(6) The negative feedback transformer 14 can be arranged with respect to the input stage 12 to provide negative feedback gain of the output voltage signal V.sub.OUT to substantially increase a transconductance of the input stage 12. For example, the negative feedback transformer 14 includes a primary winding that can be coupled to the input node 16 and can include a secondary winding that can be coupled to a control terminal of the input stage 12. For example, the control terminal can be a gate of the common-gate transistor, with the gate receiving a predetermined DC bias voltage. Therefore, the secondary winding of the negative feedback transformer 14 can be arranged in series between the bias voltage and the gate of the common-gate transistor of the input stage 12. Accordingly, negative feedback gain is achieved via the mutual magnetic coupling in the negative feedback transformer based on anti-phase operation between the source and gate of the common-gate transistor of the input stage 12. As a result, the transconductance of the common-gate transistor of the input stage 12 is increased.

(7) FIG. 2 illustrates an example of a TIA circuit 50. The TIA circuit 50 can correspond to the TIA system 10 in the example of FIG. 1, as implemented in an optical receiver system. Thus, in the example of FIG. 2, the TIA circuit 50 includes a photodiode 52 that is configured to receive an optical input signal OPT.sub.IN that is arranged between an input node 54 and a high rail voltage, demonstrated in the example of FIG. 2 as a voltage V.sub.DD. As an example, the optical input signal OPT.sub.IN can be an optical communication signal that can be implemented in a variety of different optical communications applications that may require a high sensitivity optical receiver, such as Li-Fi wireless communications. The photodiode 52 thus provides an input current signal I.sub.OPT having an amplitude that corresponds to an intensity of the optical input signal OPT.sub.IN. As an example, TIA circuit 50 can be implemented as or as part of an integrated circuit (IC) chip.

(8) The TIA circuit 50 includes an input capacitor C.sub.IN that is arranged in parallel with the photodiode 52 between the input node 54 and a low voltage rail, demonstrated in the example of FIG. 2 as ground. The TIA circuit 50 also includes an N-channel metal-oxide semiconductor field effect transistor (MOSFET) N.sub.1 arranged as an input stage for the TIA circuit 50. In the example of FIG. 2, the N-channel MOSFET N1 is arranged as having a source coupled to the input node 54 and a drain coupled to an output node 56. A resistor R.sub.1 interconnects the output node 56 and the high rail voltage V.sub.DD, and a current path between the input node 54 and ground includes a second resistor R.sub.2. Therefore, the N-channel MOSFET N.sub.1 is arranged as a common-gate transistor to provide the output voltage V.sub.OUT at the output node 56 based on an amplitude of the input current signal I.sub.OPT.

(9) The TIA circuit 50 also includes a negative feedback transformer 58. The negative feedback transformer 58 includes a primary winding L.sub.P that interconnects the input node 54 and the resistor R.sub.2, and a secondary winding L.sub.S that interconnects a predetermined DC bias voltage V.sub.B and a gate of the N-channel MOSFET N.sub.1. The primary and secondary windings L.sub.P and L.sub.S are thus mutually magnetically coupled to provide anti-phase operation between the gate and the source of the N-channel MOSFET N.sub.1. As a result, the transconductance of the N-channel MOSFET N.sub.1 can be substantially increased. For example, the transconductance g.sub.m of N.sub.1 can be expressed as:
g.sub.m=(1+n*k)*g.sub.mEquation 1 Whereas: n is a turns ratio between the primary and secondary windings L.sub.P and L.sub.S, and can be expressed as n={square root over (L.sub.s/L.sub.p)} k is a coupling coefficient of the negative feedback transformer 58; and g.sub.m is a nominal transconductance of the N-channel MOSFET N.sub.1.

(10) Therefore, as provided in Equation 1, the input impedance of the TIA circuit 50 decreases by a factor of (1+n*k). The input impedance of the TIA circuit 50 can thus be greatly reduced by implementing the negative feedback transformer 58. Because the input impedance of the TIA circuit 50 is inversely proportional to transconductance, decreasing the input impedance of the TIA circuit 50 results in an increase in the transconductance of the N-channel MOSFET N.sub.1. As a result, based on the increase in the transconductance of the N-channel MOSFET N.sub.1 via the negative feedback transformer 58, the bandwidth of the TIA circuit 50 can be extended to a significantly higher frequency relative to a typical TIA circuit. In addition, a typical TIA circuit can experience a more rapid increase in noise at relatively lower frequencies based on a reduced input pole frequency that effectively amplifies input-referred current noise associated with the current source (e.g., a photodiode). However, based on the increased input bandwidth provided by the negative feedback transformer 58, the TIA circuit 50 can achieve a slower increase in the noise current as frequency increases. Furthermore, in contrast to a TIA circuit that includes a cascode-arrangement input stage, the TIA circuit 50 can operate at a substantially reduced power (e.g., lower amplitude of the high voltage rail V.sub.DD) based on a lack of transistor stacking by implementing the negative feedback transformer 58 to achieve negative feedback gain instead of the cascode-arrangement. Accordingly, the TIA circuit 50 can operate more efficiently than typical TIA circuits.

(11) It is to be understood that the TIA circuit 50 is not intended to be limited to the example of FIG. 2. As an example, the TIA circuit 50 can implement a different arrangement for the input stage than the N-channel MOSFET N.sub.1, such as by implementing alternative types of transistors. As another example, it is to be understood that the TIA circuit 50 could be implemented as or as part of an IC chip that includes additional components of an optical receiver system, such as an output buffer and/or an analog-to-digital converter (ADC). Accordingly, the TIA circuit 50 and/or an associated optical receiver system can be implemented in a variety of ways.

(12) What have been described above are examples. It is, of course, not possible to describe every conceivable combination of components or methods, but one of ordinary skill in the art will recognize that many further combinations and permutations are possible. Accordingly, the invention is intended to embrace all such alterations, modifications, and variations that fall within the scope of this application, including the appended claims. Additionally, where the disclosure or claims recite a, an, a first, or another element, or the equivalent thereof, it should be interpreted to include one or more than one such element, neither requiring nor excluding two or more such elements. As used herein, the term includes means includes but not limited to, and the term including means including but not limited to. The term based on means based at least in part on.