Current conveyor circuit, corresponding device, apparatus and method

Abstract

A circuit includes a first transistor having a control terminal and a current path between first and second current path terminals. A second transistor has a control terminal and a current path between first and second current path terminals. The first current path terminal of the first transistor is coupled to the first current path terminal of the second transistor at an intermediate point. A first current buffer has an input and an output. The input of the first current buffer is coupled to the second current path terminal of the first transistor. A second current buffer has an input and an output, the input of the second current buffer being coupled to the second current path terminal of the second transistor. A summation node is coupled to the outputs of the first and second current buffer.

Claims

1. A circuit, comprising: a first transistor having a control terminal and a current path between first and second current path terminals; a second transistor having a control terminal and a current path between first and second current path terminals, the first current path terminal of the first transistor coupled to the first current path terminal of the second transistor at an intermediate point; a first current buffer having an input configured to receive a first input current and an output configured to generate a first output current proportional to the first input current, the input of the first current buffer being coupled to the second current path terminal of the first transistor, wherein the first current buffer comprises a first current buffer transistor having a current path that is operatively coupled between the input of the first current buffer and the output of the first current buffer; a second current buffer having an input configured to receive a second input current and an output configured to generate a second output current proportional to the second input current, the input of the second current buffer being coupled to the second current path terminal of the second transistor, wherein the second current buffer comprises a second current buffer transistor having a current path that is operatively coupled between the input of the second current buffer and the output of the second current buffer; and a summation node coupled to the outputs of the first and second current buffer.

2. The circuit of claim 1, wherein the first transistor has a first polarity and the second transistor has a second polarity that is opposite the first polarity.

3. The circuit of claim 1, further comprising: a third transistor having a control terminal and a current path between first and second current path terminals, the control terminal of the third transistor being coupled to the control terminal of the first transistor; and a fourth transistor having a control terminal and a current path between first and second current path terminals, the first current path terminal of the third transistor coupled to the first current path terminal of the fourth transistor at a second intermediate point and the control terminal of the fourth transistor being coupled to the control terminal of the second transistor.

4. The circuit of claim 3, wherein the first and third transistors have a first polarity and the second and fourth transistors have a second polarity that is opposite the first polarity.

5. The circuit of claim 1, further comprising first and second bias generators active on the current paths of the first and second transistors, wherein the input of the first current buffer is coupled between the first bias generator and the first transistor, and wherein the input of the second current buffer is coupled between the second bias generator and the second transistor.

6. The circuit of claim 1, wherein the first and second current buffer transistors are common gate connected transistors.

7. The circuit of claim 1, wherein the summation node includes a plurality of current mirrors coupled with the outputs of the first and second current buffers.

8. The circuit of claim 7, wherein the current mirrors include diode-connected transistors.

9. A device comprising: a first transistor having a control terminal and a current path between first and second current path terminals; a second transistor having a control terminal and a current path between first and second current path terminals, the first current path terminal of the first transistor coupled to the first current path terminal of the second transistor at an intermediate point; a first current buffer having an input configured to receive a first input current and an output configured to generate a first output current proportional to the first input current, the input of the first current buffer being coupled to the second current path terminal of the first transistor, wherein the first current buffer comprises a first current buffer transistor having a current path that is operatively coupled between the input of the first current buffer and the output of the first current buffer; a second current buffer having an input configured to receive a second input current and an output configured to generate a second output current proportional to the second input current, the input of the second current buffer being coupled to the second current path terminal of the second transistor, wherein the second current buffer comprises a second current buffer transistor having a current path that is operatively coupled between the input of the second current buffer and the output of the second current buffer; a summation node coupled to the outputs of the first and second current buffers; and a sensing capacitor coupled to the intermediate point.

10. The device of claim 9, further comprising a current sense node coupled to an output of the summation node, wherein a current indicative of a value of a charge on the sensing capacitor is available at the current sense node.

11. The device of claim 9, further comprising: a third transistor having a control terminal and a current path between first and second current path terminals, the control terminal of the third transistor being coupled to the control terminal of the first transistor; a fourth transistor having a control terminal and a current path between first and second current path terminals, the first current path terminal of the third transistor coupled to the first current path terminal of the fourth transistor at a second intermediate point and the control terminal of the fourth transistor being coupled to the control terminal of the second transistor; and a second capacitor coupled to the second intermediate point.

12. The device of claim 9, wherein the device is a portion of a touch screen controller.

13. The device of claim 9, further comprising first and second bias generators active on the current paths of the first and second transistors; wherein the input of the first current buffer is coupled between the first bias generator and the first transistor; and wherein the input of the second current buffer is coupled between the second bias generator and the second transistor.

14. The device of claim 9, wherein the first and second current buffer transistors are common gate connected transistors.

15. The device of claim 9, wherein the summation node includes a plurality of current mirrors coupled with the outputs of the first and second current buffers.

16. The device of claim 15, wherein the current mirrors include diode-connected transistors.

17. A method of operating the device of claim 9, the method comprising sensing a value of a charge on the sensing capacitor.

18. A circuit, comprising: a first transistor of a first polarity, the first transistor having a control terminal and a current path between first and second current path terminals; a second transistor of a second polarity opposite the first polarity, the second transistor having a control terminal and a current path between first and second current path terminals, the first current path terminal of the first transistor coupled to the first current path terminal of the second transistor at a first intermediate point; a third transistor of the first polarity, the third transistor having a control terminal and a current path between first and second current path terminals, the control terminal of the third transistor being coupled to the control terminal of the first transistor; a fourth transistor of the second polarity, the fourth transistor having a control terminal and a current path between first and second current path terminals, the first current path terminal of the third transistor coupled to the first current path terminal of the fourth transistor at a second intermediate point and the control terminal of the fourth transistor being coupled to the control terminal of the second transistor; a first current buffer having an input configured to receive a first input current and an output configured to generate a first output current proportional to the first input current, the input of the first current buffer being coupled to the second current path terminal of the first transistor, wherein the first current buffer comprises a first current buffer transistor having a current path that is operatively coupled between the input of the first current buffer and the output of the first current buffer; a second current buffer having an input configured to receive a second input current and an output configured to generate a second output current proportional to the second input current, the input of the second current buffer being coupled to the second current path terminal of the second transistor, wherein the second current buffer comprises a second current buffer transistor having a current path that is operatively coupled between the input of the second current buffer and the output of the second current buffer; a first bias generator having a current path coupled in series with the current paths of the first and second transistors, wherein the input of the first current buffer is coupled between the first bias generator and the first transistor; a second bias generator having a current path coupled in series with the current paths of the first and second transistors, wherein the input of the second current buffer is coupled between the second bias generator and the second transistor; and a summation node coupled to the outputs of the first and second current buffers.

19. The circuit of claim 18, wherein the first and second current buffer transistors are common gate connected transistors.

20. The circuit of claim 18, wherein the summation node includes a plurality of current mirrors coupled with the outputs of the first and second current buffers.

21. The circuit of claim 20, wherein the current mirrors include diode-connected transistors.

22. The circuit of claim 1, wherein the first current buffer transistor comprises a first current path terminal configured to receive the first input current, and a second current path terminal configured to produce the first output current.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) One or more embodiments will now be described, by way of example only, with reference to the annexed figures, wherein:

(2) FIG. 1 is exemplary of possible contexts of use of embodiments;

(3) FIGS. 2 and 3 are general representations of a current conveyor and its mode of operation;

(4) FIGS. 4 and 5 are circuit diagrams of current conveyors;

(5) FIG. 6 is a circuit diagram exemplary of embodiments;

(6) FIGS. 7 to 10 are explanatory diagrams; and

(7) FIGS. 11 and 12 are circuit diagrams exemplary of embodiments.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

(8) In the ensuing description, one or more specific details are illustrated, aimed at providing an in-depth understanding of examples of embodiments of this description. The embodiments may be obtained without one or more of the specific details, or with other methods, components, materials, etc. In other cases, known structures, materials, or operations are not illustrated or described in detail so that certain aspects of embodiments will not be obscured.

(9) Reference to an embodiment or one embodiment in the framework of the present description is intended to indicate that a particular configuration, structure, or characteristic described in relation to the embodiment is comprised in at least one embodiment. Hence, phrases such as in an embodiment or in one embodiment that may be present in one or more points of the present description do not necessarily refer to one and the same embodiment. Moreover, particular conformations, structures, or characteristics may be combined in any adequate way in one or more embodiments.

(10) The references used herein are provided merely for convenience and hence do not define the extent of protection or the scope of the embodiments.

(11) FIG. 1 is exemplary of a possible context of use of embodiments, namely a mobile (for instance, communication) device such as a smartphone, a tablet, and a laptop computerthis list being merely exemplary and not limitativeincluding a touch screen TS with a touch screen controller TSC, providing for instance multi-touch capability, supporting unlimited simultaneous touches.

(12) According to an arrangement known per se (which makes it unnecessary to provide a more detailed description herein) a current conveyor may be included as a building block of such a controller TSC. For instance, a current conveyor may be included in the analog front end of a touch screen controller to provide the capability of reading a set of sensing capacitors.

(13) Of course, reference to this possible context of use is merely exemplary and thus non-limiting of the scope of the embodiments.

(14) As shown in FIG. 2, a current conveyor 10 may be used together with a capacitive sensing element C.sub.S having a variable capacitance value. In FIG. 2, the capacitance C.sub.P is a (large) parasitic capacitor, which for the sake of simplicity will be assumed to be grounded throughout this description.

(15) The arrangement of FIG. 2 may be intended to translate the value of C.sub.S into a corresponding amount of charge and to transfer it as a current I.sub.z at a node z of the current conveyor 10. This result can be achieved by voltage driving the sensing capacitor C.sub.S and by using the current conveyor 10 to read the charge stored on the sensing capacitor C.sub.S and transfer it to the node z.

(16) For that purpose, the current conveyor 10 may be configured to have a low impedance at a first input x and high impedances at a second input y and at the terminal z, with the current sunk or sourced at the terminal x transferred to the z terminal with a magnification factor M.

(17) Operation of the current conveyor may be described in compact form by using a matrix form, namely:

(18) $\left(\begin{array}{c}{I}_y\\ V_x\\ I_z\end{array}\right)=\left(\begin{array}{ccc}0& 0& 0\\ 1& 0& 0\\ 0& M& 0\end{array}\right)\left(\begin{array}{c}{V}_y\\ I_x\\ V_z\end{array}\right)$

(19) A circuit model of a current conveyor described by the previous matrix equation is given in FIG. 3, with the dotted line between terminals x and y representing a virtual short circuit: that is, the voltage drop between the two terminals is zero and no current flows between them. The dotted line between terminal x and ground represents a virtual ground: that is, the current applied at this terminal is sunk by the ground, but the terminal voltage is not zero (indeed, it is equal to that of terminal y).

(20) The current I.sub.z at the output terminal z is provided by an ideal (i.e. infinite shunt resistance) current controlled current generator with a gain factor M with respect to the input current I.sub.x, that is I.sub.z=MI.sub.x

(21) One or more embodiments may relate to possible implementations of such a circuit, with FIGS. 4 and 5 exemplary of conventional approaches for that purpose.

(22) FIG. 4 is exemplary of a current conveyor circuit 10 based on a buffer-connected OTA (Operational Transconductance Amplifier) 12 having a first (for instance inverting) input y coupled to V.sub.y and a second (for instance, non-inverting) coupled to an intermediate point between two transistors M1, M2 (such as MOSFET transistors of complementary polarities, e.g. PMOS and NMOS) having their current paths (source-drain, in the case of a FET such as a MOSFET) arranged in series between a supply line V.sub.DD and ground.

(23) A current I.sub.z from a current source i.sub.t is present at the captioned intermediate point (input x), with two further transistors M3, M4 (again, for instance, MOSFET transistors of complementary polarities, e.g. PMOS and NMOS) having their current paths arranged in series between a supply line V.sub.DD and ground to form with the transistors M1, M2 a 1:M current mirror in order to provide a current I.sub.z at an intermediate point between the transistors M3 and M4 (terminal z).

(24) FIG. 5 is exemplary of a current conveyor circuit 10 based on a push-pull source follower arrangement including a translinear loop configuration, that is a loop applying the translinear principle, namely a closed loop containing an even number of translinear elements (TEs) with an equal number of them arranged clockwise and counter-clockwise, the product of the currents through the clockwise TEs being equal to the product of the currents through the counter-clockwise TEs.

(25) The circuit of FIG. 5 includes a first pair of transistors 14a, 14b (again, these may be MOSFET transistors of complementary polarities, e.g. PMOS and NMOS having their current paths arranged in series between a supply line V.sub.DD and ground) in a diode configuration (gate shorted to drain) with the signal V.sub.y at an intermediate point therebetween (input y), and a second pair 16 of transistors M.sub.In, M.sub.Ip (again, these may be MOSFET transistors of complementary polarities, e.g. PMOS and NMOS) having their gates coupled with the gates of the transistors 14a, 14b of the first pair with the signal I.sub.x from a current source i.sub.t at the intermediate point therebetween (input x).

(26) The current paths (source-drain in the case of field effect transistors such as MOSFETs) of the transistors M.sub.In, M.sub.Ip are arranged in series between a supply line V.sub.DD and ground with the current paths of two further transistors M1 and M3 in a diode configuration (gate shorted to drain).

(27) The gates of these latter transistors are in turn coupled to the gates of two further transistors M2 and M4 to provide (as in the case of the transistors M3 and M4 of FIG. 4) a current mirror with a factor 1:M with a current I.sub.z as discussed previously at an intermediate point (terminal z) between the transistors M3 and M4.

(28) The solution of FIG. 4 implements a current conveyor wherein, thanks to the negative feedback (short circuit between the x terminal and the non-inverting input of the operational amplifier 12) the input terminal x is a low impedance node and is virtually shorted to terminal y. Moreover, if a current i.sub.t is injected into terminal x the feedback loop will react by adjusting the gate-to-source voltage of transistors M1 and M3 or M2 and M4: thus, a magnified replica of current i.sub.t will be sourced or sunk (depending on the sign of current i.sub.t) at the output terminal z.

(29) It was observed that a solution as exemplified in FIG. 4 may give rise to issues related to the stability of the amplifier and the trade-off between stability and current consumption. In fact, with a large capacitance C.sub.P connected to the x terminal and the operational amplifier 12 buffer-connected, the transconductance g.sub.m of transistors M1 and M2 should be large enough to facilitate achieving the stability of the circuit. This means that, in order to avoid that compensation for circuit stability may become difficult, the value of g.sub.m for transistors M1 and M2 cannot be selected arbitrarily small. A large g.sub.m may in turn lead to a larger current noise insofar as a larger output current noise may be generated due to the output branch (transistors M3 and M4) being a magnified replica of the input branch (transistors M1 and M2). Moreover, facilitating circuit stability may involve using large compensation capacitors.

(30) A relationship between the parameters concerned may be expressed as follows:
(g.sub.mout/g.sub.min).Math.(C.sub.C/C.sub.P)=K.sub.
Here:

(31) g.sub.mout and g.sub.min represent the transconductances of the output and input stages, respectively;

(32) C.sub.P is representative of a (parasitic) capacitor connected at the input terminal x;

(33) C.sub.C is the value of the two Miller capacitors which are used in order to compensate the circuit;

(34) K.sub. is a parameter related to the phase margin: for instance, in order to obtain a 60-degree phase margin, K.sub. may be selected to be about 2.2.

(35) The relationship above is representative of the interplay between stability considerations, current consumption and area occupation.

(36) Moreover, the noise introduced by the OTA input stage 12 may contribute appreciably to the total current conveyor noise.

(37) In the arrangement of FIG. 5, which also implements a current conveyor, a current i.sub.t applied at terminal x will be mirrored and made available at the terminal z so that an adequate design of the current mirrors 1:M will provide a desired magnification M. Moreover, the loop TL indicated in the circuit scheme is a translinear loop which facilitates correct biasing of the input terminal x.

(38) It was observed that a disadvantage of the arrangement of FIG. 5 may lie in the input voltage dynamics and the trade-off between input voltage dynamics and noise.

(39) Saturating the transistors M.sub.In and M.sub.Ip facilitates a correct behavior of the circuit and, by considering the input branch of the circuit of FIG. 5, saturation of the transistors in question may occur in compliance with the following relationship:
V.sub.GS3+V.sub.oVPV.sub.XV.sub.DDV.sub.SG1V.sub.oVN
where:

(40) V.sub.GS3 and V.sub.SG1 indicate the gate-source and source-gate voltages of the diode-connected transistors M3 and M1, respectively;

(41) V.sub.DD is the supply voltage of the circuit;

(42) V.sub.oVP and V.sub.oVN indicate the overdrive voltages of the transistors M.sub.Ip and M.sub.In, respectively.

(43) The previous relationship shows that, in the presence of a small supply voltage (V.sub.DD), the input dynamics represents a point deserving attention.

(44) Smaller transistor overdrives make it larger, this suggesting reducing transistor overdrive voltages. This is in contrast with circuit noise requirements, since the noise contribution of the transistors M1 and M3 will be reduced by reducing their g.sub.m, this however resulting in their overdrive voltage being increased.

(45) Another disadvantage of the arrangement of FIG. 5 may lie in the fact that a magnified replica of the input branch current flows in the output branch. Increasing the input current facilitates reducing the input impedance while however producing an increased current consumption.

(46) One or more embodiments may be based on the recognition of the advantage of avoiding, in providing the current sources M1 and M3, the use of diode connected transistor, which contributes to a diminished input voltage dynamics. In fact, their contributions to the input supply dynamics lie in the terms V.sub.GS3 and V.sub.SG1 introduced previously.

(47) It was observed that the following relationships apply:
V.sub.GS3=V.sub.OV3+V.sub.THN
V.sub.SG1=V.sub.OV1+|V.sub.THP|
where:

(48) V.sub.THN and V.sub.THP are the threshold voltages of M3 and M1, respectively

(49) V.sub.OV1 and V.sub.OV3 are the overdrive voltages of M1 and M3, respectively with the real limitation lying in the threshold voltages which reduce the input voltage dynamics (for instance by about 1.3V).

(50) One or more embodiments may thus adopt the layout exemplified in FIG. 6 where parts or elements already discussed in connection with FIG. 5 are indicated with the same references appearing in FIG. 5, thus making it unnecessary to repeat the related description.

(51) In one or more embodiments as exemplified in FIG. 6, the signal i.sub.t in the input branch is, so-to-say, forced to pass through two current buffers 16a, 16b which lead it towards an output summation node 18 at the terminal z.

(52) In one or more embodiments as exemplified in FIG. 6, the two diode-connected transistors M1 and M3 may be replaced by two current generators (the same designation is maintained for immediate reference) which facilitate a correct biasing of the input branch.

(53) In one or more embodiments as exemplified in FIG. 6, the following relationship applies to the dynamics of the input voltage V.sub.X:
V.sub.OV3V.sub.OVPV.sub.XV.sub.DDV.sub.OV1V.sub.OVN
where:

(54) V.sub.oVP and V.sub.oVN indicate the overdrive voltages of M.sub.Ip and M.sub.In, respectively

(55) V.sub.OV3 and V.sub.OV1 indicate the overdrive voltages of M3 and M1, respectively

(56) V.sub.DD is the supply voltage of the circuit

(57) so that the limiting contribution due to the threshold voltages is no longer present.

(58) A better insight into one embodiment may be gathered by noting that a diode-connected transistor may be seen as a current-to-voltage converter so that (as schematically represented in FIGS. 7 and 8) a first diode-connected transistor M.sub.IN converts a current I.sub.IN into a voltage and then a second transistor M.sub.OUT converts the voltage into a current I.sub.OUT. It was observed that such a double conversion is redundant and, involving a diode connected transistor, limits the input voltage dynamics.

(59) One or more embodiments as exemplified in FIG. 6 avoid such a redundancy by routing the signal component i.sub.t of the input current towards the node z by using two current buffers such as 16a and 16b.

(60) As exemplified in FIG. 9, a current buffer includes a circuit with a low (ideally zero) impedance at an input with an input current I.sub.IN and large (ideally infinite) impedance at an output with an output current I.sub.OUT=I.sub.IN. The current-controlled current source amplification parameter equals 1 for a current buffer, but a larger factor can be chosen in order to get some gain, thus obtaining a current amplifier.

(61) A current buffer may be implemented using a common gate connected transistor T (e.g., a MOSFET), as shown in FIG. 10. Here RS represents the equivalent shunt resistance of the current generator providing the input current IIN (ideally RS should approach infinity) and RL is the resistance of a load through which the out current IOUT flows. A correct transistor biasing (voltage VBB) may be facilitated by resorting to suitable circuitry as known to those skilled in the art.

(62) The current gain A.sub.I of a stage as exemplified in FIG. 10 can be expressed as follows:
A.sub.I=[R.sub.s(g.sub.m+g.sub.o)]/[1+R.sub.S(g.sub.m+g.sub.o)+R.sub.Lg.sub.o]
where:

(63) R.sub.s and R.sub.L are the current source shunt resistance and the load resistance, respectively,

(64) g.sub.m and g.sub.o are the transconductance and output conductance of the transistor indicated as T.

(65) The gain AI approaches unity if R.sub.S is large enough, which may reasonably apply in an arrangement as exemplified in FIG. 6, where the circuit facilitates achieving a low input impedance and a large output impedance.

(66) FIGS. 11 and 12 (where parts or elements already discussed in connection with FIGS. 5 and 6 are indicated with the same references, thus making it unnecessary to repeat the related description) exemplify practical implementations of one or more embodiments.

(67) FIG. 11 exemplifies a possible implementation of the current buffers 16a, 16b by resorting to gate connected transistors as discussed previously in connection with in FIG. 10, with biasing voltages V.sub.BBN and V.sub.BBP.

(68) FIG. 12 exemplifies possible embodiments where the summation node 18 may be implemented by using two current mirrors with mirror ratio equal to M:1. It was noted that here the presence of two diode-connected transistors is not a concern since these diode-connected transistors will not affect either the input voltage or the output voltage dynamics.

(69) Specifically, the representations of FIGS. 6 and 11 are translated in the transistor-level representation of FIG. 12 as follows:

(70) transistors 14a, 14b of FIGS. 6 and 11>>>transistors M11, M12 of FIG. 12;

(71) transistors M.sub.In, M.sub.Ip of FIGS. 6 and 11>>>transistors M01, M02 of FIG. 12;

(72) generators M1, M3 of FIGS. 6 and 11>>>transistors M03, M13 and M04, M14 of FIG. 12;

(73) buffers/transistors 16a, 16b of FIGS. 6 and 11>>>transistors M5, M6 of FIG. 12;

(74) summation node 18 of FIGS. 6 and 11>>>current mirrors M7, M8 and M9, M10 of FIG. 12.

(75) In one or more embodiments current consumption may no longer represent a concern because the input and output branches are decoupled: therefore a current consumption-input voltage dynamics trade-off no longer comes into play.

(76) Another advantage of one or more embodiments may lie in that the current flowing in the output branch can be reduced in order to reduce the noise contribution of the output transistors.

(77) While discussed in detail for ease and completeness of understanding of the embodiments, the arrangement of the (second) pair of transistors 14a, 14b providing at their intermediate point a second input terminal y of the circuit as described herein is not mandatory, and other arrangements may be adopted in one or more embodiments.

(78) For instance, this may be the case for certain differential current conveyor arrangements as discussed in a co-pending Italian Patent Application No. 102017000034042, filed on Mar. 28, 2017, by the same Applicants and including:

(79) plural single-ended current conveyors having respective x terminals (e.g. X1, X2, . . . Xn) with respective input transistor pairs MiN, MiP corresponding to the transistor pair M.sub.In, M.sub.Ip discussed herein, and

(80) a common bias circuit including a single pair of transistors corresponding to the transistor pair 14a, 14b discussed herein coupled via reset switches SW1, SW2.

(81) One or more embodiments may concern a circuit (e.g. 10) including:

(82) a pair of transistors (e.g. M.sub.In, M.sub.Ip) arranged with their current paths (e.g. source-drain, in the case of field effect transistors such as MOSFETs) in series and coupled at an intermediate point between the transistors of the pair of transistors, the intermediate point including an input terminal (e.g. x) of the circuit, wherein the circuit includes:

(83) a pair of current buffers (e.g. 16a, 16b) having respective inputs and outputs, the inputs of the current buffers of the pair of current buffers coupled to the current paths of the transistors of the pair of transistors opposite said intermediate point, and

(84) a summation node (e.g., 18) coupled to the outputs of the current buffers of the pair of current buffers, the output of the summation node including an output terminal (e.g., z) of the circuit.

(85) One or more embodiments may include a further pair of transistors (e.g., 14a, 14b) arranged with their current paths in series and coupled at a further intermediate point between the transistors of the further pair of transistors, the further intermediate point including a further input terminal (e.g. y) of the circuit, wherein the transistors of the further pair of transistors have control terminals (e.g. gates, in the case of field effect transistors such as MOSFETs) coupled to the control terminals of the transistors of said pair of transistors (e.g. in a translinear loop).

(86) One or more embodiments may include first and second bias generators (e.g. M1, M3) active on the current paths of the transistors of said pair of transistors, wherein the current buffers of the pair of current buffers have their respective inputs coupled between:

(87) the first bias generator (e.g., M1) and one (e.g., M.sub.In) of the transistors of the pair of transistors,

(88) the second bias generator (e.g., M3) and the other (e.g., M.sub.Ip) of the transistors of the pair of transistors.

(89) In one or more embodiments, the current buffers may include common gate connected transistors.

(90) In one or more embodiments the summation node may include current mirrors (e.g. M7, M8; M9, M10) coupled with the outputs of the current buffers of the pair of current buffers.

(91) In one or more embodiments the current mirrors may include diode-connected transistors.

(92) In one or more embodiments the pair of transistors and/or the further pair of transistors may include paired transistors of opposing polarities (e.g. NMOS and PMOS).

(93) A device (e.g. TSC) according to one or more embodiments may include the circuit (e.g., 10) of one or more embodiments and a sensing capacitor (e.g., C.sub.S) coupled with the first input of the circuit. A current indicative of the value of the sensing capacitor is available at the output terminal of the circuit.

(94) One or more embodiments may include a circuit according to one or more embodiments, with a further capacitor (e.g. a parasitic capacitor C.sub.P) coupled with a further input terminal (e.g. y) of the circuit.

(95) A device according to one or more embodiments may include a touch screen controller (e.g. TSC).

(96) In one or more embodiments, apparatus (e.g. MD) including a device according to one or more embodiments may be sensitive to the value of said sensing capacitor available at the output terminal of said circuit in said device.

(97) In one or more embodiments, a method may include:

(98) providing a device according to one or more embodiments,

(99) sensing the value of said sensing capacitor available at the output terminal of said circuit in said device.

(100) Without prejudice to the underlying principles, the details and embodiments may vary, even significantly, with respect to what has been disclosed by way of example only, without departing from the extent of protection.

(101) The extent of protection is defined by the annexed claims.