DUTY CYCLE CORRECTION CIRCUIT AND APPLICATIONS THEREOF

Abstract

A duty cycle correction circuit comprises a buffer stage which outputs a digital output signal having a duty cycle. At least one buffer of the buffer stage is configured to exhibit a controllable tripping threshold. A control loop circuit comprises a sensing circuit including a switched capacitor that is reset to a reference potential and time-integrates the digital output signal. A comparator is configured to compare the potential at a terminal of the capacitor with the reference potential. A register stores a correction value determined by the comparator to adjust the tripping threshold of the at least one buffer.

Claims

1. A duty cycle correction circuit, comprising: a buffer stage, comprising: an input terminal for a digital input signal having a duty cycle; an output terminal for a digital output signal having a modified duty cycle; and at least one buffer, the buffer configured to exhibit a controllable tripping threshold; a control loop circuit, comprising: a sensing circuit coupled to the output terminal of the buffer stage comprising a switched capacitor and configured to reset the capacitor to a reference potential and to time-integrate the digital output signal in the capacitor; and a comparator coupled to the capacitor and configured to compare the potential at a terminal of the capacitor with the reference potential; and a register to store a correction value determined by the comparator, wherein the tripping threshold of the at least one buffer is controlled in dependence on the correction value.

2. The duty cycle correction circuit according to claim 1, wherein the sensing circuit further comprises a current source connected to a terminal for a supply potential and a current source connected to a terminal for ground potential, the sensing circuit configured to connect the current sources selectively to the capacitor in response to the digital output signal at the output terminal of the buffer stage.

3. The duty cycle correction circuit according to claim 1, wherein the reference potential is a common mode potential and the sensing circuit is configured to reset the capacitor to the common mode potential after a number of consecutive periods of the output signal.

4. The duty cycle correction circuit according to claim 3, wherein the common mode potential is in a range of +/−30% of half of the voltage between the supply potential and ground potential or half of the voltage between the supply potential and ground potential.

5. The duty cycle correction circuit according to claim 1, wherein the sensing circuit further comprises a first current source connected to a terminal for a supply potential and a first switch, a second current source connected to a terminal for ground potential and a second switch, wherein the capacitor is connected to a node disposed between the first and second current sources and to the terminal for ground potential.

6. The duty cycle correction circuit according to claim 1, wherein the sensing circuit further comprises a first current source connected to a terminal for a supply potential and a first switch, a second current source connected to a terminal for ground potential (VSS) and a second switch (424), wherein the capacitor (410) is connected to a node disposed between the first and second current sources and to the terminal for ground potential, a voltage divider connected to the terminal for a supply potential and to the terminal for ground potential (VSS) and connected to the capacitor through a third switch, the first and second switches coupled to the output terminal of the buffer stage and the third switch controlled in response to expiry of a number of clock cycles of the digital output signal at the output terminal of the buffer stage.

7. The duty cycle correction circuit according to claim 5, wherein the first and second current sources are each included in an output path of a corresponding current mirror.

8. The duty cycle correction circuit according to claim 1, wherein the sensing circuit is configured to time-integrate the digital output signal in the capacitor during a plurality of cycles of the digital output signal after a resetting of the capacitor to the reference potential.

9. The duty cycle correction circuit according to claim 1, wherein the comparator comprises a first differential branch and a second differential branch, a first input terminal coupled to the capacitor and a second input terminal coupled to a terminal for the reference potential and an output terminal, wherein the comparator is configured to perform chopping, wherein the first and second input terminals are alternately coupled to the first and second differential branches and the output terminal is alternately coupled to one of the first and second differential branches.

10. The duty cycle correction circuit according to claim 1, wherein the at least one buffer comprises a switchable path connected between a terminal for a supply potential and a terminal for ground potential further comprising another switchable path connected to the terminal for supply potential through a first switch and to the terminal for ground potential through a second switch, wherein input and output terminals of the switchable path and the other switchable path are connected to each other and the first and second switches of the other switchable path are controlled by the correction value stored in the register.

11. The duty cycle correction circuit according to claim 1, wherein the buffer stage comprises a chain of buffers serially connected with each other, wherein the input terminal for a digital input signal is connected to one end of the chain of buffers and the output terminal for a digital output signal is connected to another end of the chain of buffers.

12. The duty cycle correction circuit according to claim 1, wherein the buffer stage comprises a chain of buffers serially connected with each other, wherein the input terminal for a digital input signal is connected to one end of the chain of buffers and the output terminal for a digital output signal is connected to another end of the chain of buffers, wherein the buffer stage further comprises a plurality of other switchable paths, wherein each one of the plurality of other switchable paths is associated with a subset of the buffers of the chain of buffers, wherein input and output terminals of the other switchable paths and the associated one of the buffers are connected with each other.

13. The duty cycle correction circuit according to claim 12, further comprising a shift register, wherein each register of the shift register is connected to at least one or more of the other switchable paths, wherein each one of the other switchable paths is configured to be one of connected and disconnected to a terminal for supply potential and configured to be one of connected and disconnected to a terminal for ground potential in response to the operation of the control loop circuit.

14. The duty cycle correction circuit according to claim 1, wherein the buffer stage comprises: a plurality of inverters serially connected with each other and a plurality of other inverters connected through switches to terminals for supply and ground potentials and having input and output terminals (z1, z2) connected to input and output terminals of at least a subset of the inverters; further comprising: a plurality of registers, wherein each one of the registers is associated with at least one or more of the other inverters configured to control the switches connected to the associated one of the other inverters to adjust a tripping threshold of the associated one of the other inverters in dependence on correction values determined by the comparator.

15. The duty cycle correction circuit according to claim 1, wherein a portion of the control loop circuit including the sensing circuit and the comparator is switched off, when a steady state condition is achieved.

16. A low voltage differential signalling receiver, comprising: an input terminal for a differential digital input signal; an amplification stage having an output terminal for a single ended amplified signal; the duty cycle correction circuit of claim 1, wherein the input terminal of the duty cycle correction circuit is connected to the output terminal of the amplification stage.

17. A medical imaging apparatus, comprising a radiation source to generate radiation for the treatment of a living organism to generate an image of at least a portion of the living organism, further comprising the low voltage differential signalling receiver of claim 16 to process a signal carrying the image.

18. A data processing apparatus, comprising a processor to process data and a display device to display information dependent on data processed by the processor, further comprising the low voltage differential signalling receiver of claim 16 to receive data processed by the processor and to forward the data to the display device.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In the drawings:

[0032] FIG. 1 shows a principle block diagram of a LVDS receiver including a duty cycle correction circuit according to the principles of the present disclosure;

[0033] FIG. 2 shows a detailed circuit diagram of the frequency division and synchronizing block of the circuit of FIG. 1;

[0034] FIG. 3 shows a detailed circuit diagram of the timing and sequencing block of FIG. 1;

[0035] FIG. 4 shows a detailed circuit diagram of the sensing circuit of FIG. 1;

[0036] FIG. 5 shows a common mode voltage generator to be used in the sensing circuit of FIG. 4;

[0037] FIG. 6 shows a detailed circuit diagram of the chopped comparator of FIG. 1;

[0038] FIG. 7 shows a detailed circuit diagram of the storage circuit and the tripping threshold control of the buffer chain of FIG. 1;

[0039] FIG. 8 shows a waveform diagram of signals used in the circuits of FIGS. 1 to 7;

[0040] FIG. 9 shows a simulation of signals used the circuits of FIGS. 1 through 7;

[0041] FIG. 10 shows an example of the digital output signal at the beginning of a duty cycle correction operation;

[0042] FIG. 11 shows an example of the digital output signal after a duty cycle correction;

[0043] FIG. 12 shows a CT apparatus including a LVDS receiver; and

[0044] FIG. 13 shows a data processing apparatus including a LVDS receiver.

DETAILED DESCRIPTION OF EMBODIMENTS

[0045] The present disclosure will now be described more fully hereinafter with reference to the accompanying drawings showing embodiments of the disclosure. The disclosure may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that the disclosure will fully convey the scope of the disclosure to those skilled in the art. The drawings are not necessarily drawn to scale but are configured to clearly illustrate the disclosure.

[0046] FIG. 1 shows a block diagram of a LVDS receiver including a duty cycle correction circuit according to the principles of the present disclosure. The duty cycle correction circuit may also be used in other circuits where duty cycle correction is required. The LVDS receiver 100 may be used as an input port to an integrated circuit chip receiving a differential signal from a transmission line disposed on a printed circuit board. The input terminals of receiver 100 are connected to corresponding wires 151, 152 that carry the positive and negative portions of the differential signal to transmit clock and data from signal sources TX_p and TX_n. The signal is transmitted over the transmission wire line as a current signal I_IN+, I_IN−. The transmission wire line is terminated by a resistance of 100Ω so that the receiver obtains differential input signals V_IN+, V_IN−. Receiver 100 includes a receiver core 110 connected to the receiver inputs to amplify the low voltage differential input signal to a single-ended full swing signal VIN. A buffer stage 120 including a serial connection or chain of buffers 125, 126, 127, 128 is connected downstream the receiver core 110 to generate an output signal VOUT_RX at output terminal 122 of LVDS receiver 100. The receiver core 110 performs amplification of the differential signal in multiple amplification stages, transforming of the differential signal to a single-ended signal, electrostatic discharge protection and failsafe functions which generate a defined signal when the receiver input is floating. The buffer stage 120 includes CMOS inverter buffers such as buffer 125 comprising p- and n-MOS-transistors 1251, 1252 connected between the terminals for supply potential VDD and ground potential VSS, wherein the output of one inverter buffer such as 125 is connected to the input of the downstream connected next buffer such as 126 within the chain. Although only a subset of buffers is shown in FIG. 1 for exemplary reasons, a buffer stage may contain several tens of buffers such as 30 or 40. In principle, even more buffers in a chain may be used as demanded by the application considering power consumption constraints.

[0047] The duty cycle of the received input signal VIN is subject to duty cycle deviation for multiple reasons. For example, the transmission line 151, 152 may have mismatches or may be subject to electromagnetic interference or the transmitters TX_P, TX_N may already generate a signal of non-balanced duty cycle. Furthermore, the LVDS receiver may introduce a duty cycle deviation, for example, by different rise and fall times of its p- and n-MOS circuits which may be due to process, voltage and temperature (PVT) impacts, non-ideal matching of differential interconnects within the layout and others.

[0048] The duty cycle correction circuit is provided to generate an output signal VOUT_RX having a corrected duty cycle from the input signal VIN. The duty cycle correction circuit includes a control loop which repetitively senses the duty cycle deviation of the output signal VOUT_RX and corrects the deviation so as to achieve a balanced, equalized duty cycle which is 50% or close to 50% after a number of repetitive correction cycles. The control loop circuit 130 comprises a sensing circuit 133 that receives the output signal VOUT_RX from output terminal 122. A comparison circuit 134 compares the sensed duty cycle level with a reference level that indicates the wanted target duty cycle level. A storage circuit 135 provides correction values which are obtained from the comparison stage 134. The stored correction values control the buffer stage 120 so that the duty cycle of the output signal VOUT_RX is adjusted and the control loop operation including sensing, comparing and storing recommences and the loop operation is repeated until a steady state condition is achieved.

[0049] The correction values from storage block 135 control the tripping thresholds of the individual buffers 125, . . . , 128 within the buffer chain 120 so that rising and falling edges can be selectively accelerated or decelerated and the duty cycle as the ratio of low and high portions of a signal period is modified and adjusted. The differential input signal to the LVDS receiver V_IN+, V_IN− as well as the input signal to the buffer chain VIN can be a clock signal having high to low and low to high transitions at the operating frequency. The input signal may also be a data signal in which transitions are governed by the transmitted information. The duty cycle correction is performed on the clock signal and the correction values can be stored in storage 135 so that the data signals can be received thereafter using the tripping threshold setting of the buffer stage determined beforehand. The control mechanism in the buffer chain employs adjusting of the tripping thresholds which correct one of the root causes of duty cycle deviations caused by the asymmetry of p- and n-side components and transistors. The control concept of the present disclosure avoids the addition of additional delays which could reduce the resolution since there is a certain design limit that dictates the minimum possible delay.

[0050] Adjustment of the tripping thresholds of buffers 125, . . . , 128 is achieved by switchable paths 720, 730, 740 connected to the input and output terminals of the buffers 125, . . . , 128 of buffer stage 120 such as terminals z1, z2, z3, z4, z5, . . . zx, zx+1. The switching states of the switchable paths 720, 730, 740 are controlled by the storage circuit 135. The details of the switchable paths 720, 730, 740 are explained in more detail hereinbelow. The switchable paths can be connected in parallel to the input and output terminals of every second buffer such as the first, the third, the fifth etc. buffer in the buffer chain as depicted in FIG. 1. Alternatively, the switchable paths can be connected in parallel to the inputs and outputs of the second, the fourth, the sixth etc. buffer in the buffer chain. It is also possible to connect a switchable path in parallel the inputs and outputs of every buffer in the buffer chain.

[0051] When a steady state condition is achieved, for example, after performance of several correction cycles or when it is determined that the duty cycle deviation is below a resolution criterion, most portions of the control loop circuit 130 can be switched off to save power. For example, the sensing and comparison circuits 133, 134 as well as the frequency division and synchronizing circuit 131 and the timing and sequencing circuit 132 can be switched off. This considerably reduces the amount of power consumed. The storage circuit 135 including storage registers is the only circuit that remains active and stores the correction values to control the tripping threshold of the buffers in the buffer stage 120. The power consumption of these registers is negligible, as they do not switch during steady state. The control loop circuit can wake up after expiry of a predetermined amount of time determined by a timer or in response to an external event such as a variation in supply voltage or a change of temperature indicated by a temperature sensor available on system level. Such an event will activate the signal Bal_duty_en to reactivate the circuit blocks of the control loop.

[0052] In the following, several blocks from the high level representation shown in FIG. 1 are explained thereafter in FIGS. 2 through 7 on the basis of detailed circuit representations.

[0053] FIG. 2 shows a detailed circuit diagram of the frequency division and synchronizing block 131. The circuit receives the output signal VOUT_RX of the buffer stage 120 at terminal 122 which is the input signal to the regulation loop. A buffered version VOUT_buf of this signal is frequency-divided by four flip-flops 211, 212, 213, 214 to generate the clock frequency divided by two, the clock frequency divided by four, the clock frequency divided by eight and the clock frequency divided by sixteen. Other clock division circuits are also possible, such as non-overlapping clock generators. Several flip-flops 215 are used to synchronize the divided clock signals with the output clock signal and generate synchronized versions of the divided clock signals f_div2_phi1, . . . , f_div16_phi1. Complementary divided synchronized clock signals f_div2_phi2, . . . , f_div16_phi2 are also provided by the flip-flops 215.

[0054] FIG. 3 shows a circuit representation of the timing and sequencing block 132. Timing and sequencing block 132 generates control signals that are used to control operation of the other blocks 133, 134, 135. The control signals are generated from the divided clock signals and the buffered output clock signal. An enable signal Bal_duty_en_b enables the overall operation of the control loop circuit. This enable signal can be activated, for example, in response to the switching on of the system, a change of an environmental condition, the expiry of a timer and others.

[0055] FIG. 4 shows a detailed circuit diagram of the sensing circuit 133. The sensing circuit 133 comprises a switched capacitor 410 which is used to time-integrate the digital output signal VOUT_RX so that capacitor 410 carries a charge that is representative of the duty cycle deviation. The capacitor 410 is connected to respective current sources 431, 421 which are connected to the terminal for supply potential VDD and the terminal for ground potential VSS, respectively. A corresponding switch 423, 424 is connected between the current sources 431, 421 and a node 425 which is connected to the capacitor 410. Capacitor 410 is connected between node 425 and the terminal for ground potential VSS. The switches 423, 424 are controlled by signals trim_up_b and trim_down from timing and sequencing block 132 which are basically derived from the buffered output signal VOUT_RX. Accordingly, switched capacitor 410 is selectively connected to current sources 431, 421 through switches 423, 424 in response to the output signal so that the potential Vbal at capacitor 410 is representative of the deviation of the duty cycle from a reference level which may be a balanced, equalized duty cycle. The current sources 431, 421 are portions of current mirrors which are fed by a corresponding current Idc which is mirrored through diode-connected transistor 422 of the input branch of a first current mirror into current source 421 and through diode connected transistor 432 of the input branch of a second current mirror controlling the current through current source 431. The current sources 431, 421 are always switched on and conductive while the current path at the drains of the current source transistors 431, 421 is turned on or off by operating the switches 423, 424. In this configuration, no interaction takes place at the gates of the current source transistors 431, 421 and the channel inversion of the current source transistors is maintained. The speed of the circuit is increased and thus the speed of the output clock signal VOUT_RX which is the input signal to the control loop circuit 130.

[0056] Capacitor 410 is reset to a reference potential VREF at terminal 441 through a switch 440 at the beginning of a sensing cycle. Capacitor 442 smoothes the signal VREF and provides sufficient charge to quickly drive the potential Vbal at capacitor 410. The reference potential VREF may be any reference potential in between the voltage supply rails VDD, VSS. In an embodiment, the reference potential VREF is the common mode voltage Vcm which is basically the middle voltage between the voltage supply rails VDD, VSS or approximately in the middle of the voltage supply VDD, VSS. The common mode voltage can be within a margin around the middle of the voltage supply, for example, within a margin of +/−30% of half of the voltage supply, VDD/2+/−30% wherein VSS is ground potential or 0 V. The closer the reference voltage VREF is to half of the supply voltage VDD/2, the better the duty cycle correction is performed.

[0057] The common mode voltage Vcm can be generated by a resistive divider 511, 512 as shown in FIG. 5. Resetting the switched capacitor 410 to the common mode voltage at the beginning of a sensing cycle allows a fast operation so that after a certain number of charging and discharging steps of capacitor 410 in response to the output signal VOUT_RX the capacitor 410 and the potential Vbal carry the information of the duty cycle deviation. The difference between the potential Vbal at capacitor 410 and the resetting common mode voltage Vcm contains the information of the duty cycle deviation from the balanced level. The higher the number of integration cycles, the higher the amplification of the deviation of the duty cycle. The resetting of the circuit 410 after a number of time integrating steps prevents the sensing circuit 153 from going into saturation.

[0058] FIG. 6 shows a detailed circuit diagram of the comparator 134. The comparator comprises first and second differential branches 610, 620 which receive the reference signal which is the common mode signal Vcm in the present example and the potential Vbal at the switched capacitor 410 representative of the deviation of the duty cycle. The comparator is clock controlled by signal clk_comp so that the low side current source 631 can be switched off. Also the high side paths can be switched off through transistor 632, 633. The power consumption is reduced as comparator 134 consumes power only when a comparison operation is performed and is switched off during an idle time period. Furthermore, the comparator 134 is operated in chopped mode so that the input signals Vbal and Vcm can be exchanged between the branches 610, 620 with every decision through a chopping circuit 641. Correspondingly, the output signal v_dom_c at output terminal 643 is exchanged between branches 610, 620 through chopping circuit 642. As any comparator has an inherent offset which may be caused by the mismatch between the branches 610, 620, the maximum offset error is incurred only once in an initial comparison and the chopping operation avoids further offset errors since the function of the branches is exchanged. The comparator determines whether the duty cycle error represented by the capacitor potential Vbal is above or below the common mode potential Vcm and generates a corresponding output signal V_dom_c to correct the tripping threshold of one or more of the buffers of the buffer chain 120.

[0059] FIG. 7 shows a detailed diagram of the storage circuit 135 and the switchable paths 720, 730, 740 for tripping threshold control of the buffer chain 120. The storage circuit 135 is realized by a shift register 710 of which four register stages 711, 712, 713, 714 are shown connected serially. After finalizing an integration and comparison operation in sensing and comparator circuits 133, 134, the output signal V_dom_c from comparator 134 representing a correction value is fed into the shift register 710 and forwarded through the shift register with every next feeding operation. One register stage of the shift register is associated with one instance <n> of every switchable path. Every switchable path includes <n> instances each controlled by a register. For example, register 711 is associated with transistors <n> of switchable paths 720, 730, . . . , 740 so that signal Equalize_P<n> controls p-MOS transistors MP1<n>, MP3<n>, . . . , MPx<n> and signal Equalize_N<n> controls n-MOS transistors MN1<n>, MN3<n>, . . . , MNx<n>. Register 712 is associated with transistors <n−1> of switchable paths 720, 730, . . . , 740, register 713 with transistors <1> of switchable paths 720, 730, . . . , 740 etc.

[0060] When signal Equalize_N<n> is H (High), transistor MN1<n> is conducting so that transistor MN1_bal<n> is enabled adding additional driving strength of n-MOS transistor MN1_bal<n> to the n-MOS-transistor 1252 of buffer 125 increasing the pull down drive capability of transistor 1252. In this case, transistors 1252 and MN1_bal<n> are connected in parallel to each other. At the same time, signal Equalize_P<n> is L (Low) so that the gate of transistor MP1<n> is driven H by BUFX<n> and INVX<n> shutting off transistor MP1<n> not adding any drive capability to the p-MOS side transistor 1251 of inverter 125. When signal Equalize_N<n> is L, transistor MN1<n> is shut off. At the same time, signal Equalize_P<n> is H so that the gate of transistor MP1<n> is driven L by BUFX<n> and INVX<n> enabling transistor MP1<n> adding the additional driving strength of p-MOS transistor MP1_bal<n> to the p-MOS-transistor 1251 of buffer 125 increasing the pull up drive capability of transistor 1251. In this case, transistors 1251 and MP1_bal<n> are connected in parallel to each other. Transistors MN1_bal<n> and MP1_bal<n> are connected as an inverter that has input and output terminals that are connected to terminals z1, z2 of one of the buffers of the buffer stage so that they are controlled by the signal of which the duty cycle is to be corrected. Transistors MN1<n> and MP1<n> are connected between said inverter and the terminals for supply and ground potentials to enable said inverter in dependence on the correction signal Equalize_N<n> and Equalize_P<n>. In the same way, transistors MN3_bal<n> and MP3_bal<n> are connected as an inverter that has input and output terminals that are connected to terminals z3, z4 of another one of the buffers of the buffer stage. Transistors MN3<n> and MP3<n> are connected between said inverter and the terminals for supply and ground potentials to enable said inverter in dependence on the correction signal Equalize_N<n> and Equalize_P<n>. This applies to every instance <n>.

[0061] When transistor MP1<n> of switchable path 720 is enabled, at the same time transistor MP3<n> of switchable path 730 and transistor MPx<n> of switchable path 740 are enabled. In the same way, when transistor MN1<n> of switchable 720 is enabled, at the same time transistor MN3<n> of switchable path 730 and transistor MNx<n> of switchable path 740 are enabled. In summary, each of the storage elements 711, 712, . . . , 713, 714 controls one instance <n> on every switchable path 720, 730, . . . , 740. Each instance <n> comprises one p-MOS transistor and one n-MOS transistor in every switchable path 720, 730, . . . , 740 such as p-MOS transistors MP1<n>, MP3<n>, . . . , MPx<n> and n-MOS transistors MN1<n>, MN3<n>, . . . , MNx<n>.

[0062] FIG. 7 depicts the version shown in FIG. 1, when the switchable paths are connected in parallel to the inputs/outputs of the odd numbered buffers 125, 127, 128. In an alternative version, when the switchable paths are connected in parallel to the inputs/outputs of the even numbered buffers (not shown), the correction signals Equalize_N<n> and Equalize_P<n> must be flipped at switchable path 720 as well as the corresponding signals at switchable paths 730, 740. The indices shown in FIG. 7 may comply with the following rules: [0063] n=1 to N, [0064] x=1 to X, when x is odd numbered, or [0065] x=2 to X, when x is even numbered, wherein [0066] Equilize_P and Equalize N are to be flipped.

[0067] The width to length ratio (W/L) of the transistors MP1_bal<n:0> and MN1_bal<n:0> represents the driving strengths of said transistors so that the W/L ratio determines the resolution and the step size of the control loop operation and thus determines the dynamic range of the regulation.

[0068] FIG. 8 shows a waveform diagram of signals from the circuits shown in FIGS. 1 to 7. The output signal VOUT_RX is a clock signal having transitions with every clock cycle. The divided clock signals f_div2_phi1, . . . , f_div16_phi1 are obtained from the frequency division and synchronizing block 131 and provide divisions of the input clock signal. The signals trim_up_b and trim_down are generated in timing and sequencing block 132 to cause the time-integration of the clock signal by charging and discharging the switched capacitor 410. Charging and discharging is shown with signal Vbal having ramping and falling portions in response to the operation of current sources 431, 421, resp. The resulting deviation 810 between signals Vbal and common mode voltage Vcm is representative of the deviation of the duty cycle from the ideal equalized level represented by common mode reference potential Vcm. The sign of the deviation is determined by comparator 134 in response to signal clk_comp. In response to signal reset_Vbal, the potential Vbal at switched capacitor 410 is returned to the common mode voltage Vcm as shown at 820. FIG. 8 depicts a number of eight charging and discharging operations as an example. In general, more charging and discharging operations can be performed achieving a larger amplification of the duty cycle deviation, however, at the expense of a longer processing time. Only one decision cycle including one sensing cycle and one comparing operation is depicted and multiple cycles can be performed consecutively as indicated with the dots at the right end of the waveform diagram until the output signal VOUT_RX achieves a balanced duty cycle. The balanced duty cycle may be 50% or close to 50% due to the finite regulation resolution.

[0069] FIG. 9 shows a waveform diagram according to a simulation for three measuring and decision cycles. The duty cycle represented by curve 910 is initially around 48.6% and increases close to 49.4% after the third cycle.

[0070] Turning now to FIG. 10, the clock signal VOUT_RX at the beginning of a duty cycle correction process is shown. The clock signal exhibits a highly unbalanced duty cycle in that the low clock cycle period 1010 and the high clock cycle period 1020 have a substantially different duration leading to a duty cycle of 36.5% in region 1030 of the curve representing the duty cycle.

[0071] FIG. 11 shows the situation at the end of a duty cycle correction process. The low period 1110 and the high period 1120 have substantially the same duration so that the duty cycle is at 49%. Although the ideal target duty cycle is at 50%, the steady state may slightly deviate therefrom due to the resolution of the control loop.

[0072] FIG. 12 shows the application of a LVDS receiver according to the principles of the present disclosure of FIG. 1 in a computer tomography (CT) apparatus. X-ray radiation 1211 is generated by an x-ray source 1210 to investigate a human being or an animal that is positioned in area 1212. The x-ray image sensor 1220 receives the x-ray radiation modified by the living organism. The image sensor 1220 may include x-ray photodiodes, analog-to-digital converters and a digital serial interface to transmit the digital image information to a post-processing device 1230. The sensor 1220 covers a relatively large area and the generated and to be transmitted amount of data is relatively high and at the edge of the available technology since there is always a need to increase the size and resolution of the image sensor to improve medical analysis. The environment is contaminated by the x-ray radiation and, although the circuits may be protected from x-ray radiation, the protection may not be perfect so that there is a risk of radiation reaching the transmission lines and the electronic devices. LVDS receiver 1231 receives the serial data from image sensor 1220 and forwards the data to a post processor 1232. It is important to provide duty cycle correction so that the sensing window for the data received in post processor 1230 works at the optimum. Furthermore, duty cycle distortion may occur due to the x-ray environment. The duty cycle correction control loop according to the principles of the present disclosure and explained in connection with the foregoing FIGS. 1 to 11 allows to detect a duty cycle distortion situation due to an x-ray interference event, enable the duty cycle correction control loop and equalize the duty cycle again.

[0073] FIG. 13 shows a data processing apparatus such as a computer, a mobile computing device or a smartphone. Processor 1310 generates information to be displayed on a display screen 1320. The information may be received serially at a LVDS receiver 1321 according to the principles of the present disclosure. The LVDS-RX 1321 may comply with an industry standard of serial data transmission such as the Mobile Industry Processor Interface (MIPI) Alliance Display Serial Interface (DSI).

[0074] The duty cycle control loop according to the principles of the present disclosure enables a high speed serial communication from processor 1310 to display screen 1320 which is very robust against PVT deviations. The serial clock and data stream received at LVDS-RX 1321 is forwarded to display device 1322 to visualize the transmitted information for optical reception by a user.

[0075] It will be apparent to those skilled in the art that various modifications and variations can be made without departing from the spirit or scope of the disclosure as laid down in the appended claims. Since modifications, combinations, sub-combinations and variations of the disclosed embodiments incorporating the spirit and substance of the disclosure may occur to the persons skilled in the art, the disclosure should be construed to include everything within the scope of the appended claims.