AN AMPLIFIER CIRCUIT TO ENABLE ACCURATE MEASUREMENT OF SMALL ELECTRICAL SIGNALS

Abstract

An amplifier circuit includes a resistor divider (R.sub.REF) comprising n resistive elements, two main nodes defined at each end thereof, two readout nodes (d.sub.1, d.sub.2), resistor nodes (q) defined between adjacent resistive elements, and an input current source (I.sub.REF) connected or connectable to the first main node (a). The resistor divider (R.sub.REF) comprises two arrays of addressable switch elements controllable by a feedback signal (s.sub.FB) to be open or closed. The amplifier circuit includes a differential pair of transistors (T.sub.1, T.sub.2), wherein source terminals of each of the transistors (T.sub.1, T.sub.2) are connected to the second node (b), gate terminals of the transistors (T.sub.1, T.sub.2) are connected to input signals (v.sub.1, v.sub.2), drain terminals of the transistors (T.sub.1, T.sub.2) are connected to current sources (I.sub.1, I.sub.2), and bulk terminals of the transistors (T.sub.1, T.sub.2) are connected to the readout nodes (d.sub.1, d.sub.2). The amplifier circuit functions as a difference amplifier, wherein the bulk terminals affect a threshold of the respective transistors (T.sub.1, T.sub.2) so as to add or subtract a differential signal derived from the readout nodes (d.sub.1, d.sub.2) of the resistor divider (R.sub.REF) determined by the feedback signal (s.sub.FB).

Claims

1. An amplifier circuit which includes: a resistor divider (R.sub.REF) comprising n resistive elements (r.sub.n) in series where n>1, wherein: the resistor divider (R.sub.REF) comprises two main nodes defined at each end thereof, namely a first main node (a) and a second main node (b); the resistor divider (R.sub.REF) also comprises two readout nodes (d.sub.1, d.sub.2), namely a first readout node (d.sub.1) and a second readout node (d.sub.2); the resistor divider (R.sub.REF) comprises resistor nodes (q) defined between adjacent resistive elements; an input current source (I.sub.REF) is connected to the first main node (a); the resistor divider (R.sub.REF) comprises two arrays of addressable switch elements, with a first array of switch elements provided between the respective resistive nodes (q) of the resistive elements and the first readout node (d.sub.1) and with a second array of switch elements provided between the respective resistive nodes (q) of the resistive elements and the second readout node (d.sub.2); and a state of the switch elements is controlled by a feedback signal (s.sub.FB) to be open or closed, the resistive elements thus acting as selectable voltage taps with connected the readout nodes (d.sub.1, d.sub.2); a differential pair of transistors (T.sub.1, T.sub.2) comprising a first transistor (T.sub.1) having at least four terminals and a second transistor (T.sub.2) having at least four terminals, wherein: source terminals of each of the transistors (T.sub.1, T.sub.2) are connected to the second main node (b); gate terminals of the transistors (T.sub.1, T.sub.2) are connected to respective input signals (v.sub.1, v.sub.2); drain terminals of the transistors (T.sub.1, T.sub.2) are connected to respective current sources (I.sub.1, I.sub.2), wherein a differential output signal (v.sub.OUT) is created between the drain terminals of the transistors (T.sub.1, T.sub.2); and bulk terminals of the transistors (T.sub.1, T.sub.2) are connected to the respective readout nodes (d.sub.1, d.sub.2); wherein the amplifier circuit is configured to perform a function of a difference amplifier in that the transistors (T.sub.1, T.sub.2) form a differential amplifier with respective input signals (v.sub.1, v.sub.2) on their gate terminals; and wherein the bulk terminals affect a threshold of the respective transistors (T.sub.1, T.sub.2) so as to add or subtract a differential signal derived from the readout nodes (d.sub.1, d.sub.2) of the resistor divider (R.sub.REF) based on voltage signals generated by the operation of the resistor divider (R.sub.REF) determined by the feedback signal (s.sub.FB).

2. The amplifier circuit as claimed in claim 1, in which the input signals (v.sub.1, v.sub.2) are derived from an external source in the form of a sensor.

3. The amplifier circuit as claimed in claim 1, in which the transistors (T.sub.1, T.sub.2) are MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors).

4. The amplifier circuit as claimed in claim 1, in which the readout nodes (d.sub.1, d.sub.2) are differential nodes and the signals at the readout nodes (d.sub.1, d.sub.2) are a differential representation of the feedback signal (s.sub.FB).

5. The amplifier circuit as claimed in claim 1, which is configured to perform a function of an integrator where the differential pair formed by the transistors (T.sub.1, T.sub.2), the current sources (I.sub.1, I.sub.2), nodal parasitic capacitances and resistances present on nodes connected to the drain terminals of the respective transistors (T.sub.1, T.sub.2), and the operation of the amplifier circuit as a differential difference amplifier with respect to differential signals (v.sub.1, v.sub.2) and (d.sub.1, d.sub.2) causes the differential output (V.sub.OUT) to exhibit characteristics of an integrated output.

6. The amplifier circuit as claimed in claim 5, in which capacitors are added to the nodes connected to the drain terminals of the respective transistors (T.sub.1, T.sub.2) to alter integrator action.

7. The amplifier circuit as claimed in claim 6, in which feedback in the form of the feedback signal (s.sub.FB) is applied directly to the transistors (T.sub.1, T.sub.2), effectively creating a differential amplifier for direct application in sigma-delta converters.

8. The amplifier circuit as claimed in claim 1, which is configured to receive the respective input signals (v.sub.1, v.sub.2): differential signals; or a variable input signal and a fixed or ground input signal.

9. The amplifier circuit as claimed in claim 1, which is, or which forms part of, an integrated circuit.

10. A sigma-delta analogue-to-digital converter which includes the amplifier circuit as claimed in claim 1.

11. The sigma-delta analogue-to-digital converter as claimed in claim 10, which includes a summation node and in which the transistors (T.sub.1, T.sub.2) are configured to function as, or forms part of, the summation node.

12. The sigma-delta analogue-to-digital converter as claimed in claim 10, which includes a DAC (Digital-to-Analogue Converter) and in which the resistor divider (R.sub.REF) is configured to function as, or forms part of, the DAC.

13. The sigma-delta analogue-to-digital converter as claimed in claim 10, which includes an integrator and in which the current sources (11, 12), with supporting circuitry, are configured to function as, or forms part of, are integrator.

14. The sigma-delta analogue-to-digital converter as claimed in claim 10, which includes a comparator and in which an input of the comparator is connected to the differential output signal (v.sub.OUT) of the amplifier circuit.

15. The sigma-delta analogue-to-digital converter as claimed in claim 14, which includes ADC (Analogue-to-Digital Converter) logic and in which an input of the ADC logic is connected to an output of the comparator.

16. The sigma-delta analogue-to-digital converter as claimed in claim 15, which includes feedback logic which is connected to an output of the ADC logic and which is configured to generate the feedback signal (s.sub.FB).

17. The sigma-delta analogue-to-digital converter as claimed in claim 10, which is, or which forms part of, an integrated circuit.

18. A method of operating an amplifier circuit, the method including: providing a resistor divider (R.sub.REF) comprising n resistive elements (r.sub.n) in series where n>1, wherein: the resistor divider (R.sub.REF) comprises two main nodes defined at each end thereof, namely a first main node (a) and a second main node (b); the resistor divider (R.sub.REF) also comprises two readout nodes (d.sub.1, d.sub.2), namely a first readout node (d.sub.1) and a second readout node (d.sub.2); the resistor divider (R.sub.REF) comprises resistor nodes (q) defined between adjacent resistive elements; an input current source (I.sub.REF) is connected to the first main node (a); the resistor divider (R.sub.REF) comprises two arrays of addressable switch elements, with a first array of switch elements provided between the respective resistive nodes (q) of the resistive elements (r.sub.n) and the first readout node (d.sub.1) and with a second array of switch elements provided between the respective resistive nodes (q) of the resistive elements (r.sub.n) and the second readout node (d.sub.2); and a state of the switch elements is controlled by a feedback signal (s.sub.FB) to be open or closed, the resistive elements (r.sub.n) thus acting as selectable voltage taps connected to the readout nodes (d.sub.1, d.sub.2); providing a differential pair of transistors (T.sub.1, T.sub.2) comprising a first transistor (T.sub.1) having at least four terminals and a second transistor (T.sub.2) having at least four terminals, wherein: source terminals of each of the transistors (T.sub.1, T.sub.2) are connected to the second main node (b); gate terminals of the transistors (T.sub.1, T.sub.2) are connected to respective input signals (v.sub.1, v.sub.2); drain terminals of the transistors (T.sub.1, T.sub.2) are connected to respective current sources (I.sub.1, I.sub.2), wherein a differential output signal (v.sub.OUT) is created between the drain terminals of the transistors (T.sub.1, T.sub.2); and bulk terminals of the transistors (T.sub.1, T.sub.2) are connected to the respective readout nodes (d.sub.1, d.sub.2); performing, by the amplifier circuit, a function of a difference amplifier in that the transistors (T.sub.1, T.sub.2) form a differential amplifier with respective input signals (v.sub.1, v.sub.2) on their gate terminals; and affecting, by the bulk terminals of the transistors (T.sub.1, T.sub.2), a transconductance of the respective transistors (T.sub.1, T.sub.2) so as to add or subtract a differential signal derived from the readout nodes (d.sub.1, d.sub.2) of the resistor divider (R.sub.REF) based on voltage signals generated by the operation of the resistor divider (R.sub.REF) determined by the feedback signal (s.sub.FB).

Description

BRIEF DESCRIPTION OF DRAWINGS

[0064] The invention will now be further described, by way of example, with reference to the accompanying diagrammatic drawings.

[0065] In the drawings:

[0066] FIG. 1 shows a circuit diagram of an amplifier circuit, in accordance with the invention;

[0067] FIG. 2 shows a circuit diagram of a resistor divider of the amplifier circuit of FIG. 1;

[0068] FIG. 3 shows a circuit diagram of a more detailed version of the amplifier circuit of FIG. 1;

[0069] FIG. 4 shows a schematic diagram of a sigma-delta ADC of which the amplifier circuit of FIG. 1 may form part;

[0070] FIG. 5 shows a circuit and schematic diagram of a first embodiment of a more detailed version of the sigma-delta ADC of FIG. 4;

[0071] FIG. 6 shows a circuit and schematic diagram of a second embodiment of a more detailed version of the sigma-delta ADC of FIG. 4;

[0072] FIGS. 7-9 show circuit diagrams of alternative versions of the resistor divider of FIG. 2.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENT

[0073] FIG. 1 illustrates an amplifier circuit 100 in accordance with the invention. The amplifier circuit 100 includes a resistor divider (R.sub.REF) comprising n resistive elements in series where n>1. This resistor divider (R.sub.REF) is illustrated in more detail in FIGS. 2 and 7-9. The resistor divider (R.sub.REF) comprises two main nodes defined at each end thereof, namely a first main node (a) and a second main node (b). The resistor divider (R.sub.REF) also comprises two readout nodes (d.sub.1, d.sub.2), namely a first readout node (d.sub.1) and a second readout node (d.sub.2). In this example configuration, the readout nodes (d.sub.1, d.sub.2) are differential and thus may be considered differential nodes (d.sub.1, d.sub.2).

[0074] An input current source (I.sub.REF) is connected or connectable to the first main node (a). The input current source (I.sub.REF) is constant, or near constant, and may be considered a biasing current source.

[0075] The resistor divider (R.sub.REF) comprises resistor nodes (referred to by letter (q) in FIGS. 7-9) defined between adjacent resistive elements (r.sub.1 . . . r.sub.n). The resistor divider (R.sub.REF) comprises two arrays of switch elements (S.sub.a1, S.sub.a2) which are addressable, with the first array of switch elements (S.sub.a1) provided between the respective resistive nodes (q) of the resistive elements (r.sub.1 . . . r.sub.n) and the first readout node (d.sub.1) and with a second array of switch elements (S.sub.a2) provided between the respective resistive nodes (q) of the resistive elements (r.sub.1 . . . r.sub.n) and the second readout node (d.sub.2). A state of each of the switch elements (S.sub.a1, S.sub.a2) is individually controllable by a feedback signal (s.sub.FB) to be open or closed, the resistive elements (r.sub.1 . . . r.sub.n) thus acting as selectable voltage taps with reference to the readout nodes (d.sub.1, d.sub.2).

[0076] The amplifier circuit 100 has a differential pair of transistors (T.sub.1, T.sub.2) comprising a first transistor (T.sub.1) and a second transistor (T.sub.2). In this example, the transistors (T.sub.1, T.sub.2) are MOSFETs and each have four terminals as can typically be expected in a modern CMOS process. The amplifier circuit 100 has the terminals of the transistors (T.sub.1, T.sub.2) connected as follows: [0077] first terminals—the source terminals, in this example configuration—of each of the transistors (T.sub.1, T.sub.2) are connected to the second node (b); [0078] second terminals—the gate terminals, in this example configuration—of the transistors (T.sub.1, T.sub.2) are connected to respective input signals (v.sub.1, v.sub.2); [0079] third terminals—the drain terminals, in this example configuration—of the transistors (T.sub.1, T.sub.2) are connected to respective current sources (I.sub.1, I.sub.2); and [0080] fourth terminals—the bulk terminals, in this example configuration—of the transistors (T.sub.1, T.sub.2) are connected to the respective readout nodes (d.sub.1, d.sub.2).

[0081] Accordingly, a differential output signal (v.sub.OUT) is created between the drain terminals of the transistors (T.sub.1, T.sub.2) respectively having voltage levels labelled as V.sub.OUT+ and V.sub.OUT−. The amplifier circuit 100 is configured to perform a function of a difference amplifier in that the transistors (T.sub.1, T.sub.2) form a differential amplifier with respective input signals (v.sub.1, v.sub.2) on their gate terminals. The bulk terminals affect the threshold voltage of the respective transistors (T.sub.1, T.sub.2) so as to add or subtract a differential signal derived from the readout nodes (d.sub.1, d.sub.2) of the resistor divider (R.sub.REF) based on voltage signals generated by the operation of the resistor divider (R.sub.REF) determined by the feedback signal (s.sub.FB).

[0082] The resistor divider (R.sub.REF) is illustrated in further details in FIG. 2 (with variations being illustrated in FIGS. 7-9). The individual resistive elements (r.sub.1 . . . r.sub.n) may be sized equally or unequally. The resistor nodes (q.sub.1 . . . q.sub.n-1) are defined between adjacent resistors (r.sub.1 . . . r.sub.n) with the main nodes a, b at each end. There are 2*n switch elements in this example, provided respectively between (1) the resistor nodes (q.sub.1 . . . q.sub.n-1) and the second main node b and (2) the readout nodes (d.sub.1, d.sub.2). FIG. 7 illustrates an example in which there are 2*(n+1) switch elements. FIG. 8 illustrates an example in which a switch element is connected to the main node a (instead of the main node b) and FIG. 9 illustrates an example in which there are 2*(n−1) switch elements connected only to the resistor nodes (q.sub.1 . . . q.sub.n-1) and not to the main nodes a, b.

[0083] Regardless of the precise configuration, the switch elements function as programmable voltage taps to connect the readout nodes (d.sub.1, d.sub.2) to selected individual resistive elements (r.sub.1 . . . r.sub.n) based on the feedback signal (s.sub.FB). From these voltage taps, two signals at the readout nodes (d.sub.1, d.sub.2) are derived. As current flows through the resistor divider (R.sub.REF) string, voltage division occurs throughout the array of individual resistive elements so that discrete divisions of the entire voltage across the resistor divider (R.sub.REF) is accessible by the two taps through the readout nodes (d.sub.1, d.sub.2) depending on the specific closure of switches as determined by the feedback signal (S.sub.FB).

[0084] The input signals (v.sub.1, v.sub.2) may be derived from a sensor and may be specified as v.sub.IN and v.sub.IP, and are connected to the gate terminals of the transistors (T.sub.1, T.sub.2) respectively. In the case where the sensor provides a differential output signal, the signals will be differential. In the case where the sensor only provides a single-ended output, one of these inputs will be grounded or connected to a fixed potential. The signals v.sub.IN and v.sub.IP may each be positive or negative with relation to a common reference, or one or both may be connected to such reference.

[0085] With reference to FIG. 3, the circuit 200 performs the function of a difference amplifier and integrator, both functions that are required for the operation of a sigma-delta analogue-to-digital converter. An aspect of the present invention relates to the way in which the feedback signal (s.sub.FB) is subtracted from the output signal (v.sub.OUT) to give effect to the required difference function.

[0086] In a PRIOR ART circuit, where the bulk connections are connected to a constant potential, a tail current I.sub.REF will split equally between branch 1 and 2 when v.sub.IN=V.sub.IP. Any imbalance between v.sub.IN and v.sub.IP will cause a change in the transistor transconductances, thereby steering the tail current more to one branch. The transistor output impedance on the drain nodes are finite, as are the impedances associated with the current sources I.sub.1 and I.sub.2, thereby resulting in v.sub.OUT to be an amplified version of the imbalance between the inputs.

[0087] However, in the present invention, use is made of the bulk terminal of each transistor (T.sub.1, T.sub.2) to form a “second gate”, that is, another terminal that affects the transconductance of each transistor (T.sub.1, T.sub.2). The bulk terminal of each transistor (T.sub.1, T.sub.2) is connected such that the bulk terminal of the first transistor (T.sub.1) is connected to the signal from readout node (d.sub.1) and the bulk terminal of the transistor (T.sub.2) is connected to the signal from readout node (d.sub.2).

[0088] Feedback can therefore be applied directly to the differential pair of transistors (T.sub.1, T.sub.2), effectively creating a differential difference amplifier for direct application in sigma-delta converters. Since the feedback signal (s.sub.FB) is typically a digital signal that controls the states of the switch elements as per FIG. 2, a polarity of the feedback signal (s.sub.FB) can easily be controlled. In addition, and depending on the content and format of the feedback signal (s.sub.FB), a correlation can exist between signals of the readout nodes (d.sub.1, d.sub.2) or these signals can be independently controlled. In a typical application, signals of the readout nodes (d.sub.1, d.sub.2) will change in opposite directions as part of the intended operation of the amplifier circuit 100, 200.

[0089] The current sources I.sub.1 and I.sub.2, together with its parasitic resistances and capacitances, provide both gain and an integration function on the drains of the transistors (T.sub.1, T.sub.2). Additional capacitance 210 may be added on the drain terminals to alter and improve the integration function.

[0090] Since an application of the amplifier circuit 100, 200 is use as part of a sigma-delta analogue-to-digital converter, it may be necessary to interpret the individual functions of the circuit in this context. FIG. 4 shows a typical architecture, or functional block diagram, of a single- or multibit sigma-delta ADC 250. It is necessary to have a summation node (40) from which a feedback signal from a DAC is subtracted. The error signal is processed by an integrator (41) and sent to a comparator (42) for decision making. A digital circuit (ADC logic) (43) uses the comparator output signal to create a digital representation of the input signal. This representation is fed back through a digital-to-analogue converter (44) to the summation node to be subtracted from the current input signal. The approach, in general, is well known amongst persons skilled in the art.

[0091] Within this context, the amplifier circuit 100, 200 may combine the functions of the summation node (40), the integrator (41), and the DAC converter (44) in a unique and effective way. The subtraction function in the summation node (40) is performed using the differential pair of transistors (T.sub.1, T.sub.2) using the technique described above. The feedback signal (s.sub.FB) is derived from the ADC output, while the DAC function (44) is performed by applying the feedback signal (s.sub.FB) to the resistor divider (R.sub.REF) and thereby generating the bulk voltages used by the differential pair of transistors (T.sub.1, T.sub.2) as part of the subtraction operation. Integration by the integrator (41) occurs on the drain terminals of the differential pair of transistors (T.sub.1, T.sub.2).

[0092] FIG. 5 illustrates a sigma-delta ADC 300 including the amplifier circuit 200. The differential pair of transistors (T.sub.1, T.sub.2) are PMOS transistors and accepts a differential input signal (v.sub.IN−v.sub.IP) and signals from differential readout nodes (d.sub.1, d.sub.2) generated by the DAC function (54) to thereby subtract feedback from the input through operation by the differential pair (50). The differential output signal (v.sub.OUT) represents an integrated version, by virtue of the nodal characteristics of the integrator (50), of the difference signal and is then passed to a comparator (52) and fed to ADC logic (53) which converts the single bit comparator output signal to a multi-bit signal. The ADC output is encoded by the feedback logic, part of the DAC (54), to generate the appropriate feedback signal (s.sub.FB) to be applied to the resistor divider (R.sub.REF) in selecting the feedback taps, thereby generating signals at the readout nodes (d.sub.1, d.sub.2) and closing the feedback loop.

[0093] In this example shown in FIG. 5, where operation is fully differential, the signals at the readout nodes (d.sub.1, d.sub.2) will move symmetrically in opposite directions. That is, if d.sub.1 increases, d.sub.2 will decrease with the same proportion. If the implementation is a multi-bit implementation, a relationship between the ADC output and the number of elements in the reference resistor will exist as shown in FIG. 6.

[0094] In another version of the measurement device, the circuit may comprise NMOS transistors of opposite polarity forming the differential pair and in which the polarity and position of the current source (I.sub.REF) and reference resistor (R.sub.REF) are adapted accordingly to provide the same function to the circuit. In fact, any field-effect transistor where the bulk or body terminal can act as a second input to control transconductance can be used.

[0095] FIG. 6 illustrates another version of the sigma-delta ADC 400, in which the amplifier circuit 200 may accept a single-ended input where one input is, for example, grounded and the signal is applied to the other input. Either input may be grounded while the other input accepts positive and negative input signals.

[0096] The sigma-delta ADC 300, 400 may be considered a measurement circuit or a measurement device. The amplifier circuit 100, 200 and/or the sigma-delta ADC 300, 400 may be, or may be part of, an integrated circuit.

[0097] This invention as exemplified constitutes an approach to measure a physical parameter, such as temperature, radiation, thermal signature or the like from a signal generated by a sensor that senses such parameter. A novel approach is used to create the difference function between a differential, but possible single-ended, input signal from the sensor and a feedback signal, typically in digital form, that must be subtracted from the input signal as part of the sigma-delta analogue-to-digital converter while adhering to the requirements for such a measurement device as mentioned earlier. The power consumption is minimised as the reference current is also used as the operating current for the differential amplifier.

[0098] The device can be applied generally in a number of applications, but implementation is primarily aimed at integrated semiconductor circuits and devices. The device can be fabricated using cost-effective, industry standard manufacturing processes such as silicon-based CMOS (complementary metal-oxide-semiconductor). The device finds use in sensor applications, for example in read-out circuits of passive infrared (PIR) sensors, thermopiles and other sensors wherever the measurement and discretisation of input signals are required over a relatively wide dynamic range.

[0099] By constructing an amplifier circuit 100, 200 as described, or a measurement device 300, 400 comprising the amplifier circuit 100, 200, some or all of the requirements listed in the BACKGROUND OF INVENTION can be attained. Furthermore, the novel amplifier circuit 100, 200 or measurement device 300, 400 disclosed herein may achieve distinct advantages over the prior art, for example lower noise operation and additional degrees of freedom in controlling the feedback signal.