RECEIVER

Abstract

A range profile digitization circuit for converting a repeating analog input signal into a time series of digital amplitude values, the converter comprising: a signal quantizer arranged to receive the analog input signal and a threshold input and arranged to output a binary value quantized output signal based on a comparison of the input signal with the threshold signal; a plurality of samplers each arranged to sample and hold its input signal upon receipt of a trigger signal; and for each sampler: a plurality of decoders and a demultiplexer arranged to receive an output from the sampler and pass it to a selected one of said decoders based on a selector input. With a plurality of decoders associated with each of the samplers, each sampler can be re-used during the building up of the range profile.

Claims

1-13. (canceled)

14. A range profile digitization circuit for converting a repeating analog input signal into a time series of digital amplitude values, the circuit comprising: a differencer arranged to receive the analog input signal and a threshold input signal and arranged to output a differencer signal being the difference between the analog input signal and the threshold input signal; a plurality of clocked comparators, each clocked comparator being arranged to sample the differencer signal upon receipt of a trigger signal and each clocked comparator being arranged to output and hold a quantized signal; and for each clocked comparator, a decoder which is arranged to decode the quantized signal into a digital value.

15. A range profile digitization circuit as claimed in claim 14, further comprising a continuous time amplifier downstream of the differencer, arranged to amplify the differencer signal.

16. A range profile digitization circuit as claimed in claim 14, comprising a plurality of differencers, one for each clocked comparator and each arranged to receive the analog input signal and the threshold input signal and arranged to output a differencer signal being the difference between the analog input signal and the threshold input signal to its associated clocked comparator.

17. A range profile digitization circuit as claimed in claim 16, wherein the differencer is an integral part of the clocked comparator circuit.

18. A range profile digitization circuit as claimed in claim 14, comprising: for each clocked comparator: a plurality of decoders and a demultiplexer arranged to receive the amplified output from the clocked comparator and pass it to a selected one of said decoders based on a selector input.

19. A range profile digitization circuit as claimed in claim 14, further comprising: a controller arranged to generate trigger signals for the plurality of clocked comparators, the trigger signals being generated at regular time intervals.

20. A range profile digitization circuit as claimed in claim 19, wherein the controller is arranged to generate a continuous stream of trigger signals comprising a plurality of cycles of the plurality of clocked comparators.

21. A range profile digitization circuit as claimed in claim 18, further comprising: a controller arranged to generate selector inputs for the demultiplexers, the controller being arranged to change the selector input of each demultiplexer every time the corresponding clocked comparator is triggered.

22. A range profile digitization circuit as claimed in claim 18, wherein the controller is arranged to generate trigger signals for the plurality of clocked comparators and selector inputs for the demultiplexers; and wherein the controller is arranged to generate trigger signals that cycle through the plurality of clocked comparators a plurality of times; and wherein the controller is arranged to cycle through the demultiplexer selector inputs, changing each demultiplexer's selector input once per cycle of the trigger signals.

23. A range profile digitization circuit as claimed in claim 14, wherein each clocked comparator is formed from a strong-arm latch.

24. A range profile digitization circuit as claimed in claim 14, wherein the clocked comparator is arranged to generate a high or low output based on the polarity of the incoming signal.

25. A method of range profile digitization for converting a repeating analog input signal into a time series of digital amplitude values, the digitization comprising: taking the difference between the received analog input signal and a threshold input signal; providing the difference signal to a plurality of clocked comparators; each clocked comparator sampling the difference signal upon receipt of a trigger signal and outputting a quantized signal; and for each clocked comparator, decoding the quantized signal to produce a digital value.

26. A method as claimed in claim 25, further comprising amplifying the differencer signal in continuous time.

27. A method as claimed in claim 25, comprising: for each clocked comparator: receiving the amplified output from the clocked comparator and passing it to a selected one of a plurality of decoders via a demultiplexer, based on a selector input.

28. A method as claimed in claim 25, further comprising: generating trigger signals for the plurality of clocked comparators at regular time intervals.

29. A method as claimed in claim 28, comprising generating a continuous stream of trigger signals comprising a plurality of cycles of the plurality of clocked comparators.

30. A method as claimed in claim 27, further comprising: generating selector inputs for the demultiplexers, and changing the selector input of each demultiplexer every time the corresponding clocked comparator is triggered.

31. A method as claimed in claim 25, comprising: generating trigger signals for the plurality of clocked comparators and generating selector inputs for the demultiplexers; and wherein the trigger signals cycle through the plurality of clocked comparators a plurality of times; and cycling through the demultiplexer selector inputs, changing each demultiplexer's selector input once per cycle of the trigger signals.

Description

[0043] Preferred embodiments of the invention will now be described, by way of example only, and with reference to the accompanying drawings in which:

[0044] FIG. 1a shows the basic structure of a swept-threshold receiver;

[0045] FIG. 1b shows waveforms for a swept-threshold receiver operation;

[0046] FIG. 1c shows a portion of an example digitized range profile;

[0047] FIG. 2 illustrates an example of a swept-threshold receiver architecture;

[0048] FIG. 3 shows a receiver architecture according to an embodiment of the invention;

[0049] FIG. 4 shows waveforms associated with use of the architecture shown in FIG. 3; and

[0050] FIG. 5 shows a receiver architecture according to another embodiment of the invention.

[0051] FIGS. 1a, 1b, 1c and 2 were described in detail earlier in this document and are therefore not further described here.

[0052] FIG. 3 shows an impulse radar receiver architecture that operates on the swept threshold principle described and illustrated in relation to FIGS. 1a, 1b, 1c and 2. The received signal (including reflections of the transmitted signal) 12 and a threshold signal 14 are provided as inputs to a quantizer 10 that outputs a quantized signal 11 that is either high or low (voltage rails) depending on the comparison of the received signal 12 with the threshold signal 14. The quantized signal 11 is still a continuous-time (non-clocked) signal, with a binary value (high or low). This quantized signal 11 is then fanned out to a plurality of samplers 30 which operate in parallel.

[0053] Whereas in FIG. 2 the counters 16 were triggered by the taps of a non-clocked delay line, in this embodiment (FIG. 3) the samplers 30 are triggered by the phase outputs <n> from a multiphase frequency generator (multiphase clock) 40. The outputs <0> to <n1> of multiphase clock 40 are shown in the upper half of FIG. 4, all having the same frequency F=F.sub.s/n, but each being offset by a different amount. The outputs <0> to <n1> are equally spaced from one another and <n1> is also equally spaced from the <0> of the next F.sub.s/n clock cycle. The top row of FIG. 4 illustrates the overall effective sampling rate F.sub.s with time period t.sub.s, although it will be appreciated that this is not a real signal appearing anywhere in the circuit of FIG. 3.

[0054] As each sampler 30 is triggered by its corresponding clock phase signal <0> to <n1>, it samples its continuous-time, binary value input 11 and holds that value for the duration of its clock phase until it is next required to sample the input again. The plurality of samplers 30 each receive a different clock phase <0> to <n1> such that they sample the quantized signal 11 at different times and thus sample different range points in the received signal (different range points in the range profile). Each sampler 30 may be a D-type flip-flop.

[0055] The output of each sampler 30 is passed to the input of a demultiplexer 32. Each demultiplexer 32 can direct its input to one of several different outputs, depending on the selector input 34 which is provided by controller 50. The different outputs of the demultiplexer 32 are each provided to a different counter 36 (being a form of decoder) each of which is arranged to increase its count by one upon receipt of a high signal and not to increase its count when its input is low.

[0056] Once per clock phase cycle (i.e. at a frequency Fs/n), the controller 50 changes the selector input 34 to select the next counter in the series, i.e. to move the demultiplexer output on to the next counter. Thus for example the demultiplexer 34 attached to the sampler 30 that is driven by clock phase <0> initially directs its output to counter.sub.0,0. In the next cycle of clock phase <0>, the next sample from sampler 30 is directed to counter.sub.1,0 and the next sample is directed to counter.sub.2,0, etc. up to the final counter.sub.m,0. Similarly the demultiplexer 34 attached to the sampler 30 that is driven by clock phase <1> initially directs its output to counter.sub.0,1. In the next cycle of clock phase <1>, the next sample from sampler 30 is directed to counter.sub.1,1 and the next sample is directed to counter.sub.2,1, etc. up to the final counter.sub.m1,1. In this way, each counter 36 represents a different range point in the range profile in the sequence counter.sub.0,0, counter.sub.0,1, counter.sub.0,2, . . . , counter.sub.0,n1, counter.sub.1,0, counter.sub.1,1, counter.sub.1,2, . . . , counter.sub.1,tn1, . . . , counter.sub.m1,0, counter.sub.m1,1, counter.sub.m1,2, . . . , counter.sub.m1,n1. The counting of the various counters 36 is illustrated in the lower half of FIG. 4, each counter being represented by a pair of lines and a crossing of those lines indicating a change of state (i.e. an increase in counter value).

[0057] The use of the multiphase clock 40 allows multiple adjacent samples to be taken at closely spaced time points without requiring a single fast clock and sampler (i.e. the sampler is distributed). The provision of multiple counters 36 per sampler 30 reduces the number of parallel samplers 30 that are required to provide a full range profile (i.e. the samplers are re-used). The counters 36 are isolated from the quantizer 10 and thus reduce the capacitive load that is seen by the quantizer 10 and thus producing less impact on the rise and fall times of the quantized signal 11.

[0058] FIG. 5 shows a second embodiment of an impulse radar receiver architecture that operates on the swept threshold principle described and illustrated in relation to FIGS. 1a, 1b, 1c and 2. The received signal (including reflections of the transmitted signal) 12 and a threshold signal 14 are provided as inputs to a difference 60 that outputs the difference between the received signal 12 and the threshold signal 14. This difference signal is input into low gain linear amplifier (buffer) 62 that amplifies the signal, but does not quantize it like the quantizer 10 of FIGS. 2 and 3. Instead, the output of amplifier 62 is continuous in time and continuous in value (whereas the output of quantizer 10 of FIGS. 2 and 3 was continuous time, binary value). As the signal is not pushed to the voltage rails at this point in the signal processing chain, the switching noise is reduced.

[0059] The output 63 of amplifier 62 is fanned out to a plurality of parallel samplers 64 in a similar way to the circuit of FIG. 3. Each sampler 64 also performs the quantization necessary to generate a binary value CMOS signal to trigger the counters 36. However, in this embodiment the quantization takes place after the sampling of the amplifier output 63. The important difference here is that the quantization does not need to be performed in continuous time, i.e. the signal does not need to be pushed to one of the voltage rails on such a short timescale (which generates high frequency switching noise). Instead, the amplifier output 63 only needs to be pushed to a voltage rail fast enough to trigger the associated counter 36 before the next sampling event on the associated sampler 64. This can be a much longer time period and allows a slower regenerative amplifier to perform the quantization. Further, this takes place after the sampling and thus any associated switching noise does not affect the sampling, nor does it affect any of the other parallel sampling branches.

[0060] The sampler 64 may comprise separate individual circuits for sampling and then amplifying the sampled value. However, in preferred arrangements a combined circuit is used, most preferably a strong-arm latch circuit is used as this conveniently performs sampling and regenerative amplification in a single efficient circuit.

[0061] As shown in FIG. 5, the samplers 64 are triggered by the phases <0> to <n1> from multiphase clock 40 shown in FIG. 4 such that each sampler 64 samples a different time point (and hence range point) in the received signal 12.

[0062] FIG. 5 shows each sampler 64 having only a single counter 36 and is thus an architecture which is analogous to that of FIG. 2 where all range points are sampled by their own individual sampler 64. However, the principles shown in FIG. 4 may also be applied such that each sampler 64 is provided with a demultiplexer 32 and a plurality of counters 36, with the demultiplexers 32 controlled by a controller 50 in the same way as is described above in relation to FIG. 4.

[0063] In the circuits of both FIGS. 4 and 5, the threshold signal 14 is changed over time so as to sweep through a predefined range of voltages. For each threshold voltage level the full range profile is compared and each counter incremented (or not) appropriately. Over the full predefined range of threshold voltages, the counters will gradually build up a value corresponding to the signal level by counting the number of times that the signal 12 was above the threshold 14.

[0064] It will be appreciated that while the circuits shown in FIGS. 4 and 5 are single-ended implementations, a differential implementation can also be used. Differential circuits may be preferred for better rejection of coupled noise (such as switching noise). In such implementations a differential signal is conveyed as a positive signal (pos) and an identical but opposite polarity signal (neg), with the signal of interest being the difference between the two, i.e. pos-neg.