METHOD OF PRODUCING AN ELECTRONIC DEVICE PRECURSOR

Abstract

There is provided a method 100 of producing an electronic device precursor 200, the method 100 comprising: (i) providing 105 a plasma-etchable layer structure 210 on a plasma-resistant substrate 205, wherein the layer structure 210 has an exposed upper surface; (ii) patterning 110 a plasma-resistant dielectric 215 onto the exposed upper surface to form an intermediate having at least one covered region and at least one uncovered region of the layer structure 210; (iii) subjecting the intermediate to plasma etching 115, whereby the at least one uncovered region of the layer structure 210 is etched away to form at least one covered region of the layer structure 210 having an exposed edge surface; (iv) forming 120 an ohmic contact 220a, 220b in direct contact with a portion of the exposed edge surface; wherein the plasma-etchable layer structure 210 comprises one or more graphene layers which extend across the covered regions of the layer structure 210 to the exposed edge surface.

Claims

1. A method of producing an electronic device precursor, the method comprising: (i) providing a plasma-etchable layer structure on a plasma-resistant substrate, wherein the layer structure has an exposed upper surface; (ii) patterning a plasma-resistant dielectric by physical vapour deposition onto the exposed upper surface to form an intermediate having at least one covered region and at least one uncovered region of the layer structure; (iii) subjecting the intermediate to plasma etching, whereby the at least one uncovered region of the layer structure is etched away to form at least one covered region of the layer structure having an exposed edge surface; (iv) forming an ohmic contact in direct contact with a portion of the exposed edge surface; wherein the plasma-etchable layer structure comprises one or more graphene layers which extend across the covered regions of the layer structure to the exposed edge surface; and wherein, either before or after step (iv), the method further comprises (v) forming a coating layer to provide the covered region of the layer structure with a continuous air-resistant coating.

2. The method according to claim 1, wherein the plasma-resistant substrate is sapphire, silicon, silicon dioxide, silicon nitride, silicon carbide, germanium, or a III-V semiconductor.

3. The method according to claim 1, wherein the plasma-resistant dielectric and/or the coating layer are each an inorganic oxide, nitride, carbide, fluoride or sulphide.

4. The method according to claim 1, wherein the plasma etching comprises oxygen plasma etching.

5. The method according to claim 1, wherein the plasma-etchable layer structure consists of one or more 2D-material layers.

6. The method according to claim 5, wherein the plasma-etchable layer structure consists of one or more graphene layers and, optionally, one or more layers of silicene, germanene, h-BN, borophene and/or a TMDC.

7. The method according to claim 6, wherein the one or more graphene layers and, where present, the one or more layers of silicene, germanene, h-BN, borophene and/or a TMDC, are each formed by CVD or MOCVD.

8. The method according to claim 1, wherein step (ii) comprises forming: (a) one or more rectangular-shaped regions of the plasma-resistant dielectric and wherein the electronic device precursor is for forming a transistor; or (b) one or more cross-shaped regions of the plasma-resistant dielectric and wherein the electronic device precursor is for forming a Hall-sensor.

9. The method according to claim 1, wherein step (ii) comprises patterning a plasma-resistant dielectric by e-beam evaporation.

10. The method according to claim 1, wherein the method comprises forming an array of covered regions, each corresponding to an electronic device precursor.

11. (canceled)

12. (canceled)

13. (canceled)

14. The method according to claim 1, wherein: step (v) is performed after step (iv) and the ohmic contact is formed on the plasma-resistant substrate; and wherein the coating layer is formed by ALD across the plasma-resistant substrate to provide the at least one covered region of the layer structure, the ohmic contact, and remaining exposed edge surface with a continuous air-resistant coating.

15. The method according to claim 14, wherein the method further comprises wire bonding the ohmic contact of the device precursor through the coating layer.

16. The method according to claim 1, wherein: step (v) is performed after step (iv) and the ohmic contact is formed on the plasma-resistant substrate; and wherein the coating layer is formed by patterning a coating layer onto the plasma-resistant substrate to provide the at least one covered region of the layer structure and remaining exposed edge surface with a continuous air-resistant coating.

17. The method according to claim 16, wherein the coating layer is formed by e-beam evaporation.

18. The method according to claim 1, wherein: step (v) is performed before step (iv) and comprises selectively etching away one or more portions of the coating layer to expose corresponding portions of the edge surface, and step (iv) comprises forming an ohmic contact in direct contact with each exposed portion of the edge surface.

19. The method according to claim 18, wherein the selective etching is performed by laser etching or reactive ion etching.

20. The method according to claim 16, wherein the method further comprises depositing a solder bump on the ohmic contact or wire bonding the ohmic contact.

21. An electronic device precursor comprising: a substrate having a layer structure thereon, the layer structure comprising: a lower layer on a first region of the substrate, wherein the lower layer comprises one or more graphene layers which extend across the lower layer, and an upper layer on the lower layer and formed of a dielectric material, wherein the lower and upper layers share a continuous outer edge surface, an ohmic contact provided on a further region of the substrate and in direct contact with the one or more graphene layers via the continuous outer edge surface, and a continuous air-resistant coating layer either (a) across the substrate, the layer structure, and the at least one ohmic contact or (b) enclosing the layer structure.

22. (canceled)

23. (canceled)

24. (canceled)

25. The electronic device precursor according to claim 21, wherein the lower layer further comprises one or more layers of silicene, germanene, h-BN, borophene and/or a TMDC which extend across the lower layer.

26. The electronic device precursor according to claim 21, wherein the electronic device precursor is for forming a Hall-sensor, and wherein the charge carrier density of the one or more graphene layers is less than 810.sup.11 cm.sup.2.

Description

FIGURES

[0158] The present invention will now be described further with reference to the following non-limiting Figures, in which:

[0159] FIG. 1 is a flowchart illustrating the method of the present invention.

[0160] FIG. 2 is a cross-sectional view of an electronic device precursor in accordance with an embodiment of the present invention.

[0161] FIG. 3 is a cross-sectional view of another electronic device precursor in accordance with an embodiment of the present invention.

[0162] FIG. 4 is a plan view of another electronic device precursor in accordance with an embodiment of the present invention.

[0163] FIG. 5 is a plan view of another electronic device precursor in accordance with an embodiment of the present invention.

[0164] FIG. 6 is a perspective view of an array of electronic device precursors in accordance with an embodiment of the present invention.

[0165] FIG. 1 is a flow chart illustrating the method of the present invention 100. The method 100 comprises a number of essential steps (105, 110, 115 and 120) and may further comprise one of three optional steps (125a, 125b and 125c) representing three alternatively preferred specific embodiments of method 100.

[0166] The method 100 is for forming an electronic device precursor suitable for a Hall-sensor and comprises a first step 105 of providing a plasma-etchable layer structure on a plasma-resistant substrate. In exemplary method 100, the plasma-etchable layer structure consists of a graphene monolayer provided by MOCVD directly on a sapphire substrate.

[0167] Next, a further step 110 involves patterning an array cross-shaped regions of alumina by e-beam evaporation, onto the exposed upper surface of the graphene monolayer to form an array of intermediates. The method will be further described with reference to one intermediate though it will be appreciated that all of the intermediates of the array are treated simultaneously. Step 115 involves subjecting the intermediate to oxygen plasma etching to thereby etch the exposed graphene monolayer and form an array of cross-shaped regions of graphene covered with alumina, the alumina covered graphene having a continuous exposed edge surface.

[0168] Method 100 further comprises a step 120 of forming a metal ohmic contact in direct contact with a portion of the exposed edge surface of the etched graphene monolayer. In particular, four metal contacts are formed at the end of each of the arms of the cross-shape.

[0169] In a first specific embodiment of method 100, the method 100 further comprises a step 125a, performed after step 120, which comprises forming a coating layer of alumina by ALD across the sapphire substrate thereby coating the alumina coated graphene, the ohmic contacts and the exposed substrate with a continuous air-resistant coating.

[0170] In a second specific embodiment, the method 100 further comprises a step 125b, performed after step 120, which comprises patterning an alumina coating layer by e-beam evaporation onto the substrate thereby coating the alumina coated graphene with a continuous air-resistance coating. The alumina coating provided by step 125b therefore coats and protects the exposed edge(s) which are not in contact with the ohmic contact from atmospheric contamination and the pattern of the coating is the same geometric cross-shape, but geometrically larger. For example, the maximum width and/or maximum height of the shape may be 10% larger, or even 20% larger that than of the patterned alumina of step 110. The patterning step also leaves a portion of each metal contact exposed for connection to an electronic circuit.

[0171] In a third specific embodiment, the method 100 further comprises a step 125c of forming a coating layer before step 120. Step 125c involves forming a coating layer, to provide the alumina coated graphene monolayer with a continuous air-resistant coating of alumina (i.e. such that the exposed edge surface is coated). In this embodiment, step 120 further involves a step of selectively laser etching four portions of the coating layer at the end of each of the arms of the underlying cross-shape to expose the corresponding portions of the edge surface of the graphene. As required by method 100, step 120 then involve forming the metal ohmic contacts in direct contact with the exposed edge surface in each of the selectively etch portions.

[0172] FIG. 2 is a cross-sectional view of an electronic device precursor 200. The precursor 200 is obtainable by the method described herein which involves forming a coating layer by ALD after forming the ohmic contacts.

[0173] The electronic device precursor 200 is formed of a sapphire substrate 205 upon which there is a plasma-etchable 2D-material layer 210 comprising a graphene layer structure. The 2D-material layer 210 has a shape defined by the alumina layer 215 formed thereon. Accordingly, the 2D-material layer and the alumina share a continuous edge surface wherein the graphene layer structure extends to this edge.

[0174] The precursor 200 further comprises two ohmic contacts 220a and 220b, each in direct contact with said edge of the 2D-material layer 210 and therefore of the graphene layer structure. No contact material is on the surface of the 2D-material layer 210 since the alumina and 2D-material share a continuous edge surface and are of the same shape. Advantageously, the contact does not result in any appreciable doping of the 2D-material as that which may be observed when contacts are provided on the planar surface of a 2D-material. Further, edge contact provides improved charge injection relative to surface charge injection improving overall efficiency (for example by reducing any electrical losses as heat).

[0175] A continuous air-resistant coating layer of silica is formed on the alumina coating 215, the contacts 220a and 220b and the substrate 205. The coating 225 provides excellent protection from atmospheric contamination by prevent the ingress of, for example, oxygen gas and water vapour. The precursor 200 further comprises wires 230a and 230b which have been wire bonded to the ohmic contacts 220a and 220b, respectively. The wires 230a and 230b provide a means for electrical connectivity to the ohmic contacts and therefore protrude out of the coating layer.

[0176] The inventors have found that the electronic device precursor 200 provides an electronic device with excellent stability. In particular, the inventors have found that a device formed from precursor 200 exhibits a rate of degradation of less than 0.01%/day (as measured with respect to the initial carrier concentration, and therefore sensitivity, of the device and the point of manufacture).

[0177] By way of comparison, a device formed from a precursor wherein the coating layer (e.g. coating layer 215) is not provided and instead a ceramic lid, is used to seal the components (as is well-known in the art and which may also be used in combination with the present invention), the sensitivity of such a device was found to degrade at a rate in excess of 0.5%/day. Likewise, the inventors found that the absence of a coating layer or ceramic lid was significantly greater still.

[0178] By way of further comparison, the inventors found that devices formed using an organic, PMMA, coating layer provided greater protection against degradation over known ceramic lids, such devices having a rate of degradation of between 0.03%/day and 0.1%/day.

[0179] The inventors have also found that when metal contacts are deposited on graphene before the patterning of a dielectric layer, the metal results in heavy doping of the graphene of greater than 12 cm.sup.2 and even greater than 10.sup.13 cm.sup.2 thereby significantly reducing sensitivity. FIG. 3 is a cross-sectional view of an electronic device precursor 300. The precursor 300 is obtainable by the method described herein which involves forming a coating layer before the step of forming the ohmic contacts.

[0180] The electronic device precursor 300 comprises a sapphire substrate 305 upon which there is a plasma-etchable 2D-material layer 310. In this embodiment, the 2D-material layer consists of bi-layer graphene (i.e. a graphene monolayer having 2 layers of graphene). Formed thereon is a patterned layer of silica 315 which shares a continuous edge surface with the bi-layer graphene 310. Deposited on the surface of the patterned silica layer 315 is a continuous air-resistant coating 325. The coating 325 is also deposited on an adjacent portion of the surface of the substrate 305. FIG. 3 is a cross-section view of precursor 300, the cross-section bisects two ohmic contacts 320 deposited on the substrate 305. It will be appreciated that in alternative cross-sections, the coating layer the coating layer 325 will be continuous.

[0181] The contacts 320 are in direct contact with an edge surface of the bi-layer graphene, as well as the silica and alumina coatings thereon. The precursor 300 may be obtained by the method described herein which comprises selectively etching a coating layer formed before forming the ohmic contacts.

[0182] Accordingly, the contacts extend from the surface of the substrate 305 which is exposed during the etching process to the surface of the coating layer 325. In this embodiment, solder balls (or solder bumps) 330 are provided on the exposed portion of the ohmic contact such that precursor 300 may be described as being a flip-chip.

[0183] FIG. 4 is a plan view of an electronic device precursor 400. Precursor 400 is suitable for a Hall-sensor and is formed of a 2D-material layer beneath an identically shaped/patterned alumina layer 415, specifically a cross-shape, all of which is formed on a silicon substrate 405. The ends of each of the four arms of the cross-shaped layer structure (i.e. the distal portion) of the 2D-material and patterned alumina 415 are in direct contact with each of the four titanium contacts (420a, 420b, 420c and 420d). A continuous air-resistant alumina coating 425 is provided over the layer structure and a portion of each of the contacts in a manner sufficient to encapsulate the edges of the underlying 2D-material layer and leave a portion of each of the titanium contacts exposed. Coating layer 425 may be provided by e-beam evaporation. In FIG. 4, coating layer 425 is illustrated as semi-transparent so as to illustrate the presence of the underlying patterned alumina 415. As will be appreciated, the 2D-material layer has the same shape as alumina layer 415. Precursor 400 is an individual component obtainable by dicing a substrate formed of an array of equivalent precursors sharing the common substrate. Precursor 400 is advantageous in the respect since dicing does not involve cutting through the coating layer 425 since the coating layer does not extend into the so-called streets or the portions of the substrate between the array of components being manufactured.

[0184] The present inventors have used Raman spectra obtained at various positions of the device precursor to confirm the presence (and quality) or absence of graphene. In particular, the method of the present invention facilitates the clean etching of graphene up to the edge of the patterned alumina such that ohmic contacts may then be provided without having to remove the protective alumina layer. Further, the Raman spectra of the graphene demonstrates that the quality of the graphene proximal to the edge may remain comparable with the quality of the remainder of the underlying and protected portions of graphene (such as at the point of label 415 for the stack of graphene and patterned alumina in FIG. 4). Additionally, the present inventors have used Raman spectroscopy to demonstrate the absence of graphene outside the patterned dielectric between the coating layer and substrate (such as at the point of label 425 for the coating layer in FIG. 4).

[0185] FIG. 5 is a plan view of an electronic device precursor 500. The precursor 500 is suitable for a Hall-sensor and is formed of a 2D-material layer beneath an identically shaped/patterned alumina layer 515, specifically a cross-shape, all of which is formed on a sapphire substrate. Separate gold contacts 520 are provided in direct contact with corresponding edge portions of the underlying 2D-material layer at four portions of the cross, specifically four distal portions which are the ends of each arm of the cross-shape. A continuous air-resistant coating 525 of silica formed by ALD is coated across the entire substrate and the layer structure of the 2D-material and alumina 515 (and therefore all of the edges not in direct contact with the contacts 520) along with all of the contacts 520 themselves. As with FIG. 4, coating layer 525 is illustrated as semi-transparent so as to illustrate the presence of the underlying patterned alumina 515.

[0186] FIG. 6 is a perspective view of an array 600 of electronic device precursors. Array 600 is formed of four electronic device precursors which may be separated by dicing the substrate along the streets 635. Each precursor comprises a portion of the substrate (605a, 605b, 605c and 605d) and formed on each portion is coating layer (625a, 625b, 625c and 625d) which encapsulates layer structures of 2D-materials and patterned dielectric layers. Further, each precursor comprises two ohmic contacts (620a and 620a), portions of which are not encapsulated by the coating layer (625a).

EXAMPLES

According to a First Example

[0187] 1. Graphene was grown on a sapphire substrate according to the process in WO2017/029470. [0188] 2. Al.sub.2O.sub.3 was evaporated onto the graphene using thermal evaporation through a shadow mask with apertures in the shape of a cross. The thickness of the evaporated Al.sub.2O.sub.3 was 10 nm. [0189] 3. The graphene in areas where it remained exposed as the uppermost layer was removed via plasma etching. The settings used for this were 40% power (on a 100 W device) with 6 sccm oxygen flow rate for 30 s. [0190] 4. Ti/Au bar-shaped contacts were evaporated onto the ends of the arms of the cross using another shadow mask. These were made by evaporating 10 nm of Ti and then 120 nm of Au. They were positioned with respect to the cross arms so that they made contact to the edge of the graphene at the ends of the cross arms and extended sideways away from the cross arms. [0191] 5. A second layer of evaporated Al.sub.2O.sub.3 was deposited over the first in a cross shape larger than the first, such that it covered the first cross and left part of each bar contact exposed. [0192] 6. This gave devices on-wafer, which were then processed via standard BEOL processing.

[0193] According to a second example: [0194] 1. Graphene was grown on a sapphire substrate according to the process in WO2017/029470. [0195] 2. Al.sub.2O.sub.3 was evaporated onto the graphene using thermal evaporation through a shadow mask with apertures in the shape of a cross. The thickness of the evaporated Al.sub.2O.sub.3 was 10 nm. [0196] 3. The graphene in areas where it remained exposed as the uppermost layer was removed via plasma etching. The settings used for this were 40% power (on a 100 W device) with 6 sccm oxygen flow rate for 30 s. [0197] 4. Ti/Au bar-shaped contacts were evaporated onto the ends of the arms of the cross using another shadow mask. These were made by evaporating 10 nm of Ti and then 120 nm of Au. They were positioned with respect to the cross arms so that they made contact to the edge of the graphene at the ends of the cross arms and extended sideways away from the cross arms. [0198] 5. A second layer of Al.sub.2O.sub.3 was deposited over the entire wafer using ALD. This layer was 65 nm thick. [0199] 6. This gave devices on-wafer, which were then processed via standard BEOL processing.

[0200] As used herein, the singular form of a, an and the include plural references unless the context clearly dictates otherwise. The use of the term comprising is intended to be interpreted as including such features but not excluding other features and is also intended to include the option of the features necessarily being limited to those described. In other words, the term also includes the limitations of consisting essentially of (intended to mean that specific further components can be present provided they do not materially affect the essential characteristic of the described feature) and consisting of (intended to mean that no other feature may be included such that if the components were expressed as percentages by their proportions, these would add up to 100%, whilst accounting for any unavoidable impurities), unless the context clearly dictates otherwise.

[0201] It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, layers and/or portions, the elements, layers and/or portions should not be limited by these terms. These terms are only used to distinguish one element, layer or portion from another, or a further, element, layer or portion. It will be understood that the term on is intended to mean directly on such that there are no intervening layers between one material being said to be on another material. Spatially relative terms, such as below, beneath, lower, above, upper and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s). It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as below or beneath other elements or features would then be oriented above the other elements or features. Thus, the example term below can encompass both an orientation of above and below. The device may be otherwise oriented and the spatially relative descriptors used herein interpreted accordingly.

[0202] The foregoing detailed description has been provided by way of explanation and illustration, and is not intended to limit the scope of the appended claims. Many variations of the presently preferred embodiments illustrated herein will be apparent to one of ordinary skill in the art, and remain within the scope of the appended claims and their equivalents.