Van der Waals heterostructure memory device and switching method

Abstract

A method of switching between first and second states of a van der Waals heterostructure, vdWH, memory device, a vdWH memory device, and a method of fabricating a vdWH memory device. The vdWH memory device comprises a first two-dimensional, 2D, material; and a second 2D material, wherein, in a first storage state of the memory device, an interface between the first and second 2D material comprises interfacial states; and wherein, in a second storage state of the memory device, interfacial states are modulated compared to the first memory state.

Claims

1. A method of switching between first and second states of a van der Waals heterostructure, vdWH, memory device comprising a first two-dimensional, 2D, material and a second 2D material with an interface therebetween, the method comprising the steps of: exposing the interface to a laser beam while applying an erase voltage signal across the interface for creating interfacial states according to a first storage state of the memory device; and applying a write voltage signal across the interface for modulating the interfacial states according to a second state of the memory device, wherein the vdHW memory devive comprises the second 2D material as a channel on the first 2D material in a field-effect transistor configuration comprising a gate electrode, a source electrode and a drain electrode, and the method comprises applying the erase voltage signal to the gate electrode with a zero bias voltage between the source electrode and the drain electrode.

2. The method of claim 1, comprising applying the write voltage signal to the gate electrode with a zero bias voltage between the source electrode and the drain electrode.

3. The method of claim 1, wherein the gate electrode is disposed as a back gate electrode.

4. The method of claim 1, wherein the first storage state of the memory device is characterized by a first output current with a reading voltage applied between the source electrode and the drain electrode in dark condition.

5. The method of claim 4, wherein the second storage state of the memory device is characterized by a second output current larger than the first reading current with the same reading voltage applied between the source electrode and the drain electrode in dark condition.

6. The method of claim 1, wherein the first 2D material comprises hexagonal boron nitride.

7. The method of claim 1, wherein the second 2D material comprises molybdenum ditelluride or tungsten diselenide.

8. A van der Waals heterostructure, vdWH, memory device comprising: a first two-dimensional, 2D, material; and a second 2D material as a channel on the first 2D material in a field-effect transistor configuration comprising a gate electrode, a source electrode and a drain electrode, wherein, in a first storage state of the memory device, an interface between the first and second 2D material comprises interfacial states; wherein, in a second storage state of the memory device, interfacial states are modulated compared to the first memory state; and wherein the vdWH memory device is configured for applying the erase voltage signal to the gate electrode with a zero bias voltage between the source electrode and the drain electrode.

9. The vdWH memory device of claim 8, configured for exposing the interface to a laser beam while applying an erase voltage signal across the interface for setting the vdWH memory device into the first memory state.

10. The vdWH memory device of claim 8, configured for applying an erase voltage signal across the interface for setting the vdWH memory device into the second memory state.

11. The vdWH memory device of claim 8, configured for applying the write voltage signal to the gate electrode with a zero bias voltage between the source electrode and the drain electrode.

12. The vdWH memory device of claim 8, wherein the gate electrode is disposed as a back gate electrode.

13. The vdWH memory device of claim 8, wherein the first storage state of the memory device is characterized by a first output current with a reading voltage applied between the source electrode and the drain electrode in dark condition.

14. The vdWH memory device of claim 13, wherein the second storage state of the memory device is characterized by a second output current larger than the first reading current with the same reading voltage applied between the source electrode and the drain electrode in dark condition.

15. The vdWH memory device of claim 8, wherein the first 2D material comprises hexagonal boron nitride.

16. The vdWH memory device of claim 8, wherein the second 2D material comprises molybdenum ditelluride or tungsten diselenide.

17. A method of fabricating a van der Waals heterostructure, vdWH, memory device, comprising the steps of: providing a first two-dimensional, 2D, material; providing a second 2D material as a channel on the first 2D material in a field-effect transistor configuration comprising a gate electrode, a source electrode and a drain electrode, with an interface between the first 2D material and the second 2D material; wherein the interface is configured such that, in a first storage state of the memory device, the interface between the first and second 2D material comprises interfacial states and such that in a second storage state of the memory device, interfacial states are modulated compared to the first memory state; and configuring the vdWh memory device for applying the erase voltage signal to the gate electrode with a zero bias voltage between the source electrode and the drain electrode.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Embodiments of the invention will be better understood and readily apparent to one of ordinary skill in the art from the following written description, by way of example only, and in conjunction with the drawings, in which:

(2) FIG. 1A shows schematic cross-sectional drawings illustrating a fabrication process of a vdWH according to an example embodiment.

(3) FIG. 1B shows schematic perspective side view of a vdWH according to an example embodiment.

(4) FIG. 1C shows an optical microscopy image of a MoTe.sub.2/hBN vdWH according to an example embodiment.

(5) FIG. 1D shows the Raman characterization of the exfoliated MoTe.sub.2 and hBN flakes of the vdWH of FIG. 1C.

(6) FIG. 1E shows the transfer characteristics of the MoTe.sub.2 transistor on hBN substrate in the vdWH of FIG. 1C, both linear and logarithm (inset) scales. The bias voltage V.sub.sd is 1.0 V.

(7) FIG. 2A shows the transfer characteristics of the vdWH device according to an example embodiment in dark condition after the initialization process.

(8) FIG. 2B shows the switching ratio as a function of readout voltage Vread. for the device according to an example embodiment.

(9) FIG. 2C shows a graph illustrating a dynamic write-erase process of the vdWH device according to an example embodiment. The gray shadow represents that the laser beam is on. Inset shows the output current of the memory after erasing.

(10) FIG. 3A shows the transfer characteristics evolution of the vdWH memory according to an example embodiment after erasing under different erasing gates from 10 V to 50 V.

(11) FIG. 3B shows the memory window as a function of erasing gate of the vdWH memory according to an example embodiment.

(12) FIG. 3C shows the readout of the storage current after writing at different writing gates from −20 V to −80 V of the vdWH memory according to an example embodiment. The current is readout under bias Vsd=0.1 V and gate Vread=0 V.

(13) FIG. 3D shows the output current as a function of writing gate of the vdWH memory according to an example embodiment.

(14) FIG. 4A shows the evolution of the storage current versus retention time of the vdWH memory according to an example embodiment.

(15) FIG. 4B shows the evolution of the switching ratio versus retention time of the vdWH memory according to an example embodiment.

(16) FIG. 4C shows the evolution of the transfer characteristics of the memory at different cyclic number of the vdWH memory according to an example embodiment.

(17) FIG. 4D shows the evolution of the extracted storage current in both states ‘0’ and ‘1’ as a function of cyclic number of the vdWH memory according to an example embodiment.

(18) FIG. 5 shows a flowchart illustrating a method of switching between first and second states of a van der Waals heterostructure, vdWH, memory device comprising a first two-dimensional, 2D, material and a second 2D material with an interface therebetween, according to an example embodiment.

(19) FIG. 6 shows a schematic drawings of a van der Waals heterostructure, vdWH, memory device 600 according to an example embodiment,

(20) FIG. 7 shows a flowchart illustrating a method of fabricating a van der Waals heterostructure, vdWH, memory device, according to an example embodiment.

(21) FIG. 8A shows the transfer characteristics of the vdWH device according to an example embodiment in dark condition after the initialization process.

(22) FIG. 8B shows the switching ratio as a function of readout voltage Vread. for the device according to an example embodiment.

(23) FIG. 8C shows a graph illustrating a dynamic write-erase process of the vdWH device according to an example embodiment. The gray shadow represents that the laser beam is on. Inset shows the output current of the memory after erasing.

DETAILED DESCRIPTION

(24) Embodiments of the present invention can provide a two-dimensional (2D) non-volatile van der Waals heterostructures (vdWH) memory device enabled by the artificially created interfacial states between hexagonal boron nitride (hBN) and molybdenum ditelluride (MoTe.sub.2). The memory originates from the microscopically coupled optical and electrical responses of the vdWH, with the high reliability reflected by its long data retention time over 10.sup.4 s and large write-erase cyclic number exceeding 100, according to an example embodiment. Moreover, the storage currents in the memory according to an example embodiment can be precisely controlled by the writing and erasing gates, demonstrating the tunability of its storage states.

(25) In an example embodiment, the interfacial states can be effectively modulated through microscopically controlling the optical and electrical responses of the vdWH, which leads to distinct storage states in the memory.

(26) Embodiments of the present invention can make it possible to realize a high performance 2D non-volatile vdWH memory device.

(27) Fabrication of 2D MoTe.sub.2/hBN vdWH Device According to an Example Embodiment

(28) The hybrid structure of MoTe.sub.2 and hBN according to an example embodiment was achieved by a dry transfer method in a glovebox (Ar atmosphere). With reference to FIG. 1A, multilayer hBN 110 flake was firstly mechanically exfoliated onto Si substrate 112 coated with 300 nm SiO.sub.2 dielectric. In the following, the MoTe.sub.2 114 flake exfoliated on a transparent polydimethylsiloxane (PDMS) substrate was aligned on the hBN flake using an optical microscope. After the alignment, the PDMS film was pressed on the SiO.sub.2/Si substrate 110 for ˜2 minutes followed by a slow lift up, during which the MoTe.sub.2 114 flake was transferred onto the hBN 110 flake. After transfer, the vdWH (110, 114) was spin coated by poly(methyl methacrylate) (PMMA) 116 in the same glovebox for device fabrication. The standard e-beam lithography (EBL) was performed to define the MoTe.sub.2 memory channel and the electrical contacts, after which the metal electrodes (Cr/Au) e.g. 104 were deposited using thermal evaporation. After liftoff of the PMMA 115 layer in acetone solution, the vdWH device 100 according to an example embodiment was wire-bonded onto a chip carrier and loaded into a high vacuum chamber (pressure approximately 10.sup.−7 mbar) for characterizations.

(29) Electrical Characterization of the vdWH Memory Devices According to Example Embodiments

(30) The devices according to example embodiments were characterized in a high vacuum chamber (˜10.sup.−7 mbar). The electrical measurements were conducted by using an Agilent 2912A source measure unit. A micro-sized laser beam with wavelength 405 nm was used to modulate the memory performance. The light intensity of the laser beam was calibrated by THORLABS GmbH (PM 100A) power meter.

(31) Results and Analysis of Example Embodiments

(32) Referring again to FIG. 1A, in the device fabrication process according to an example embodiment the few-layer hBN 110 is mechanically exfoliated onto SiO.sub.2/Si substrate 112, followed by the dry transfer of MoTe.sub.2 114 flake. The metal contacts e.g. 104 are thermally deposited on the MoTe.sub.2 114 channel. FIG. 1C demonstrates the optical microscopy image of the as-fabricated MoTe.sub.2/hBN vdWH device 100 according to an example embodiment in a back-gated field-effect-transistor (FET) configuration. For each pair of contacts e.g. 104, 105, there is one source and one drain. There is no restriction for which is which, since the contacts are symmetry to each other. The measurements presented below were obtained between one pair of contacts at a time, using a gate electrode at the back of the Si/SiO2 substrate 112.

(33) The Raman measurement reveals the crystallinity of the MoTe.sub.2 flake (FIG. 1D), with three characteristic peaks located at ˜172 cm.sup.−1, 235 cm.sup.−1, and 291 cm.sup.−1, respectively. The hBN flake exhibits a single Raman characteristic peak at ˜1365 cm.sup.−1. FIG. 1E shows the transfer curve (I.sub.sd−V.sub.g) of the pristine MoTe.sub.2 transistor on hBN flake in both linear and logarithm (inset) scales under bias voltage V.sub.sd=1.0 V, which exhibits a typical n-type dominated ambipolar transport behavior. It is noted that the transfer curve shows weak hysteresis under the backward (V.sub.g from 50 V to −80 V) and forward (V.sub.g from −80 V to 50 V) sweepings, indicating the negligible trapping charges at the pristine MoTe.sub.2/hBN interface.

(34) With reference to FIGS. 1A and 1B, a laser beam 118 (λ=405 nm) was then employed to expose the device 100 under a positive gate V.sub.g=50 V and zero bias, a process which is denoted as initialization. The laser beam 118 was fine-focused on one channel (between one pair of electrodes) at a time. The laser intensity is calibrated at around 200 mW/cm.sup.2, and the exposure time is 2 s. After the initialization, the transfer curve (FIG. 2A) was swept in both the backward and forward directions in dark condition again. Intriguingly, the transfer characteristic demonstrates a remarkable hysteresis and threshold voltage (V.sub.th) shift ΔV (i.e. memory window) ˜60 V during the bi-directional sweeping, which indicates a significant memory behavior. To further investigate such memory behavior, the dynamic ‘write-erase’ process was carried out on the device according to an example embodiment to set the device to state ‘1’ and state ‘0’, as shown in FIG. 2C. The readout of pristine channel current is ˜0.5 μA under V.sub.sd=1.0 V and V.sub.g=0 V, which is assigned as state ‘1’, and consistent with the transfer characterization in FIG. 1E. The same initialization process was then conducted to erase the channel current, followed by the readout operation. The output current is dramatically reduced to a low level of ˜0.15 nA (inset of FIG. 2C), suggesting that the device is in state ‘0’. The reduction of the current is due to charge being “scattered” at the artificial interfacial states created during initialization. Additionally, the erased current is maintained without significant change under V.sub.sd=1.0 V, illustrating its non-volatility. A negative gate pulse (V.sub.g=−80 V, duration ˜2 s) is then used to write the device, which reverts the output current to its original level, and the device returns to state ‘1’. To evaluate the distinguishability of the storage states in the memory device, the switching ratio R was calculated as R=I.sub.written/I.sub.erased, which is defined as the output current ratio between the state ‘1’ and state ‘0’.

(35) As shown in FIG. 2B, R is estimated to be ˜3×10.sup.3 at V.sub.read=0 V, which gradually decays as the readout voltage is increased to ˜50 V. This large switching ratio indicates the significant current difference between the written and erased states, which is very promising for multibit data storage application according to example embodiments. It is noted that the integration of micro-size laser beam in the device chip according to an example embodiment is involved for the development of the MoTe.sub.2/hBN vdWH memory. The photonic chip which can act as laser beam source has been realized with high performance by choosing suitable materials or carefully designing the chip configuration [9,10]. Based on these advanced photonic chip technology, the micro-size laser beam can be integrated in a memory in a practical device package according to an example embodiment.

(36) FIG. 3A shows the transfer characteristics evolution of the vdWH memory according to an example embodiment in bi-directional sweeping under different erasing gate (V.sub.erase from 10 V to 50 V). The backward transfer curve keeps positively shifting as the erasing gate increases from 10 V to 50 V, leading to a progressively enlarged hysteresis and memory window from ˜40 V to ˜60 V (FIG. 3B). These results illustrate the performance tunable characteristics of the vdWH memory according to an example embodiment via controlling the erasing gate. In addition to the erasing gate, the memory performance can also be modulated by the writing gate, as shown in FIG. 3C and 3D. The output current I.sub.written in storage state ‘1’ gradually rises from ˜3.3 nA to ˜500 nA, with increasing the V.sub.write from −10 V to −80 V, illustrating the tunable nature of the I.sub.written in a wide range.

(37) To evaluate the reliability of the vdWH memory device according to an example embodiment, the data retention capability and cyclic write-erase endurance are investigated. FIG. 4a shows the output current (under V.sub.sd=1.0 V and V.sub.g=0 V) as a function of waiting time up to 10.sup.4 s, at different storage states ‘0’ and ‘1’. It is noted that the memory was kept isolated from the external perturbations (such as electric field and light) after erasing or writing, and the output currents were readout in a fixed interval of 2×10.sup.3 s. Despite of the gradual evolution of the output currents, both the written and erased currents are nearly retained without significant change as prolonging the retention time to 10.sup.4 s. Additionally, the switching ratio can still maintain at a high level around 1.1×10.sup.3 (FIG. 4b), illustrating the high distinguishability of the states ‘0’ and ‘1’ throughout this retention period. These results reveal the excellent non-volatile property of the memory device according to an example embodiment. The write-erase dynamical process was also repeated for 100 cycles, with the bi-directional transfer characteristics for the selected cycles shown in FIG. 4C. The transfer curves under the different cycles are almost overlapped with each other in both the backward and forward sweeping directions, indicating the outstanding repeatability of the memory according to an example embodiment. The output currents in both storage state ‘0’ and ‘1’ are extracted at V.sub.read=0 V from the transfer characterization, and plotted as a function of cyclic number in FIG. 4D. The currents demonstrate weak fluctuation in their corresponding storage state in the 100 cycles. Moreover, the deviation from the average values of both the written and erased currents for each V.sub.read is within 50%, further revealing that the output currents are highly-reproducible. Given the robust data retention capability and cyclic endurance, the interfacial states assisted vdWH memory demonstrates great potential for non-volatile data storage.

(38) In another example embodiment, a WSe.sub.2/hBN memory was fabricated and analyzed. FIGS. 8A-C show the device performance of the WSe.sub.2/hBN memory according to an example embodiment, which is similar to the MoTe.sub.2/hBN memory in FIGS. 2A-C. Again, a laser beam 118 (λ=405 nm) was employed to expose the device under a positive gate V.sub.g=50 V and zero bias, a process which is denoted as initialization. The laser beam was fine-focused on one channel (between one pair of electrodes) at a time. The laser intensity is calibrated at around 200 mW/cm.sup.2, and the exposure time is 2 s. After the initialization, the transfer curve (FIG. 8A) was swept in both the backward and forward directions in dark condition again. Again, the transfer characteristic demonstrates a remarkable hysteresis and threshold voltage (V.sub.th) shift ΔV (i.e. memory window) ˜77 V during the bi-directional sweeping, which indicates a significant memory behavior. To further investigate such memory behavior, the dynamic ‘write-erase’ process was carried out on the device according to an example embodiment to set the device to state ‘1’ and state ‘0’, as shown in FIG. 8C. The readout of pristine channel current is ˜60 nA under V.sub.sd=1.0 V and V.sub.g=0 V, which is assigned as state ‘1’. The same initialization process was then conducted to erase the channel current, followed by the readout operation. The output current is dramatically reduced to a low level of ˜60 pA (inset of FIG. 8C), suggesting that the device is in state ‘0’. Again, the reduction of the current is due to charge being “scattered” at the artificial interfacial states created during initialization. Additionally, the erased current is maintained without significant change under V.sub.sd=1.0 V, illustrating its non-volatility. A negative gate pulse (V.sub.g=−80 V, duration ˜2 s) is then used to write the device, which reverts the output current to its original level, and the device returns to state ‘1’. To evaluate the distinguishability of the storage states in the memory device, the switching ratio R was calculated as R=I.sub.written/I.sub.erased, which is defined as the output current ratio between the state ‘1’ and state ‘0’. There is a difference in the threshold voltage V.sub.th of different devices/materials, in the sweeping direction from positive voltage to negative voltage. In MoTe.sub.2 device (compare FIG. 2) the V.sub.th is around 0V, while in WSe.sub.2 (compare FIG. 8) the V.sub.th is ˜20V. The switching ratio maximum occurs at the value of V.sub.th.

(39) FIG. 5 shows a flowchart 500 illustrating a method of switching between first and second states of a van der Waals heterostructure, vdWH, memory device comprising a first two-dimensional, 2D, material and a second 2D material with an interface therebetween, according to an example embodiment. At step 502, the interface is exposed to a laser beam while applying an erase voltage signal across the interface for creating interfacial states according to a first storage state of the memory device. At step 504. a write voltage signal is applied across the interface for modulating the interfacial states according to a second state of the memory device.

(40) The vdWH memory device may comprise the second 2D material as a channel on the first 2D material in a field-effect transistor configuration comprising a gate electrode, a source electrode and a drain electrode, and the method comprises applying the erase voltage signal to the gate electrode with a zero bias voltage between the source electrode and the drain electrode.

(41) The method may comprise applying the write voltage signal to the gate electrode with a zero bias voltage between the source electrode and the drain electrode.

(42) The gate electrode may be disposed as a back gate electrode.

(43) The first storage state of the memory device may be characterized by a first output current with a reading voltage applied between the source electrode and the drain electrode in dark condition.

(44) The second storage state of the memory device may be characterized by a second output current larger than the first reading current with the same reading voltage applied between the source electrode and the drain electrode in dark condition.

(45) The first 2D material may comprise hexagonal boron nitride or other materials, such as metal oxides which contain large amounts of defects.

(46) The second 2D material may comprise molybdenum ditelluride or other 2D semiconductors such as molybdenum disulfide, tungsten diselenide.

(47) FIG. 6 shows a schematic drawings of a van der Waals heterostructure, vdWH, memory device 600 according to an example embodiment, comprising a first two-dimensional, 2D, material 602; and a second 2D material 605, wherein, in a first storage state of the memory device 600, an interface 606 between the first 2D material 602 and the second 2D material 605 comprises interfacial states e.g. 608; and wherein, in a second storage state of the memory device 600, interfacial states e.g. 608 are modulated compared to the first memory state.

(48) The vdWH memory device 600 may be configured for exposing the interface 606 to a laser beam while applying an erase voltage signal across the interface 606 for setting the vdWH memory device 600 into the first memory state.

(49) The vdWH memory device 600 may be configured for applying an erase voltage signal across the interface 606 for setting the vdWH memory device 600 into the second memory state.

(50) The vdWH memory device 600 may comprise the second 2D material 605 as a channel on the first 2D material 602 in a field-effect transistor configuration comprising a gate electrode, a source electrode and a drain electrode.

(51) The vdWH memory device 600 may be configured for applying the erase voltage signal to the gate electrode with a zero bias voltage between the source electrode and the drain electrode.

(52) The vdWH memory device 600 may be configured for applying the write voltage signal to the gate electrode with a zero bias voltage between the source electrode and the drain electrode.

(53) The gate electrode may be disposed as a back gate electrode.

(54) The first storage state of the memory device 600 may be characterized by a first output current with a reading voltage applied between the source electrode and the drain electrode in dark condition.

(55) The second storage state of the memory device may be characterized by a second output current larger than the first reading current with the same reading voltage applied between the source electrode and the drain electrode in dark condition.

(56) The first 2D material 602 may comprise hexagonal boron nitride.

(57) The second 2D material 605 may comprise molybdenum ditelluride or tungsten diselenide.

(58) FIG. 7 shows a flowchart 700 illustrating a method of fabricating a van der Waals heterostructure, vdWH, memory device, according to an example embodiment. At step 702, a first two-dimensional, 2D, material is provided. At step 704, a second 2D material is provided, with an interface between the first 2D material and the second 2D material, wherein the interface is configured such that, in a first storage state of the memory device, the interface between the first and second 2D material comprises interfacial states and such that in a second storage state of the memory device, interfacial states are modulated compared to the first memory state.

(59) As described above, a non-volatile vdWH memory device according to an example embodiment has been provided with the assistance of the artificially created interfacial states between MoTe.sub.2 and hBN. The dynamic write-erase process has been repeated for 100 cycles with weak fluctuation of the transfer characteristics and output currents, indicating the outstanding reliability of the memory device according to example embodiments. On the other hand, both the written and erased currents can be maintained without significant decay in the retention time of ˜10.sup.4 s, which illustrates the excellent non-volatile characteristics of the memory according to example embodiments. Embodiments of the present invention provide for artificially producing and effectively modulating the interfacial states in vdWH, making it possible to realize high performance vdWH memory devices, opening up new opportunities to utilize interfacial-state engineering technique for the design and architecture of 2D electronic and optoelectronic devices according to various embodiments.

(60) Embodiments of the present invention can have one or more of the following features and associated advantages:

(61) TABLE-US-00001 Feature Benefit/Advantage Interfacial The interfacial states in the vdWH states creation can be created under light illumination to realize the memory effect. High reliability Long retention time over 10.sup.4 s and large write-erase cyclic number exceeding 100 Gate controllable The storage current can memory be easily controlled by performance the external gate voltages

(62) The above description of illustrated embodiments of the systems and methods is not intended to be exhaustive or to limit the systems and methods to the precise forms disclosed. While specific embodiments of, and examples for, the systems components and methods are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the systems, components and methods, as those skilled in the relevant art will recognize. The teachings of the systems and methods provided herein can be applied to other processing systems and methods, not only for the systems and methods described above.

(63) It will be appreciated by a person skilled in the art that numerous variations and/or modifications may be made to the present invention as shown in the specific embodiments without departing from the spirit or scope of the invention as broadly described. The present embodiments are, therefore, to be considered in all respects to be illustrative and not restrictive. Also, the invention includes any combination of features described for different embodiments, including in the summary section, even if the feature or combination of features is not explicitly specified in the claims or the detailed description of the present embodiments.

(64) For example, in different embodiments other 2D semiconductors such as molybdenum disulfide may be used as the second 2D material.

(65) In general, in the following claims, the terms used should not be construed to limit the systems and methods to the specific embodiments disclosed in the specification and the claims, but should be construed to include all processing systems that operate under the claims. Accordingly, the systems and methods are not limited by the disclosure, but instead the scope of the systems and methods is to be determined entirely by the claims.

(66) Unless the context clearly requires otherwise, throughout the description and the claims, the words “comprise,” “comprising,” and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is to say, in a sense of “including, but not limited to.” Words using the singular or plural number also include the plural or singular number respectively. Additionally, the words “herein,” “hereunder,” “above,” “below,” and words of similar import refer to this application as a whole and not to any particular portions of this application. When the word “or” is used in reference to a list of two or more items, that word covers all of the following interpretations of the word: any of the items in the list, all of the items in the list and any combination of the items in the list.

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