Abstract
A system for generating a voltage at a pixel array includes a plurality of display pixels forming the pixel array, each display pixel comprising a pixel circuit for driving the pixel. The system further comprises a row formatter configured to store a plurality of bits representing image data for a row of display pixels of the LCOS array; a row controller configured to write a subset of the plurality of bits representing image data for a pixel of the row into a plurality of data latches of said pixel circuit; and a waveform generator for generating reference pulses represented by a set of reference bits. The pixel circuit is configured to compare each reference bit to corresponding bits stored in the latches of each pixel circuit, and generate voltage at an electrode of each pixel based on this comparison.
Claims
1. A system for generating and supplying a voltage to a pixel array, said system comprising: a plurality of display pixels forming the pixel array, each display pixel comprising a pixel circuit for driving the pixel and the pixel circuit including a plurality of data latches; a row formatter configured to store a plurality of bits representing image data for a row of display pixels of the pixel array; a row controller configured to write a subset of the plurality of bits representing image data for a display pixel of the row into the plurality of data latches of said pixel circuit; a waveform generator for generating reference pulses represented by a set of reference bits and wherein a number of the set of reference bits is equal to or corresponds to the number of bits stored in the data latches of each pixel circuit; and wherein the pixel circuit is configured to compare each reference bit to corresponding bits stored in the data latches of each pixel circuit, and to generate a voltage at an electrode of each pixel based on this comparison.
2. The system of claim 1, wherein the voltage supplied to the pixel electrodes modulates at least one of polarization, reflectivity, amplitude and phase of light reflected from the display pixels.
3. The system of claim 1, wherein the number of bits stored in the data latches of each pixel circuit is 4 to 10 bits.
4. The system of claim 1, wherein the waveform generator is connected to each pixel via a Global Modulation Bus (G-bus), wherein a width of the G-bus is equal to the number of bits stored in the latches of each pixel circuit.
5. The system of claim 4, wherein the waveform generator is configured to send out a word of memory contents on the G-bus periodically in sequence to generate a plurality of voltage pulses equal to the width of the G-bus on different G-bus lines of the G-bus.
6. The system of claim 5, wherein a voltage pulse on a G-bus line of the G-bus may be divided across several G-bus lines.
7. The system of claim 6, wherein a duration of each voltage pulse on each line of the G-bus is programmable.
8. The system of claim 7, wherein the pixel array is a liquid crystal on silicon array, said liquid crystal on silicon array comprising a liquid crystal layered between two substrates, and wherein the duration of the voltage pulses is substantially shorter than a Liquid Crystal response time.
9. The system of claim 8, wherein all the bits stored in the data latches of the pixel circuit are compared to their corresponding bits stored in the waveform generator within a time period shorter than the Liquid Crystal response time.
10. The system of claim 9, wherein the pixel circuit further comprises an output latch, and wherein the output latch is input with a bit “1” if the corresponding bit in the data latch is equal to “1”, and otherwise the output latch is input with a bit “0” when a Gset signal output from the waveform generator is applied to the output latch.
11. The system of claim 10, wherein an onset of the Gset signal is coincident with a start of each voltage pulse on each of the G-bus lines.
12. The system of claim 11, wherein an output of the output latch is input to a level shifter.
13. The system of claim 12, wherein the pixel array is an LCOS array, an wherein an output of the level shifter is a voltage with a higher voltage when an output of the output latch of the pixel circuit is a bit “1”, and a lower voltage if the output of the output latch of the pixel circuit is a bit “0”, wherein the voltage on the output of the level shifter is applied to the electrode of each pixel in the LCOS array.
14. The system of claim 13, wherein there is no temporal overlap between the voltage pulses on different G-bus lines.
15. The system of claim 1, further comprising a display loader configured to write a value for the plurality of bits representing image data for a row of display pixels into the row formatter and/or configured to write a value for the subset of the plurality of bits representing image data for a pixel of the row into the plurality of data latches of each pixel circuit.
16. The system of claim 1, wherein the plurality of bits representing image data for a row of display pixels is loaded from a storage system.
17. The system of claim 16, wherein a logic function is used to compare all the bits stored in the data latches of each pixel circuit to their corresponding reference bits within a time period shorter than a Liquid Crystal response time.
18. The system of claim 17, wherein a duration of each voltage pulse is equal to a number of wave-step clock periods corresponding to a wave-step value stored in a waveform delta memory.
19. The system of claim 18, wherein each wave-step value stored in the waveform delta memory represents a different desired gray-scale value.
20. A system for generating and supplying a voltage to a pixel array, said system comprising: a row formatter configured to store a plurality of bits representing image data for a row of display pixels of a pixel array; a row controller configured to write a subset of the plurality of bits representing image data for a pixel of the row into a plurality of data latches of pixel circuits associated with the display pixels; a waveform generator for generating reference pulses represented by a set of reference bits; and wherein the system is configured to compare each reference bit to corresponding bits stored in the data latches of each pixel circuit, and to generate a voltage at an electrode of each display pixel based on this comparison.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
[0032] The present disclosure is illustrated and described herein with reference to the various drawings, in which like reference numbers are used to denote like system components, as appropriate, and in which:
[0033] FIG. 1 is a prior-art display system.
[0034] FIG. 2 is a diagram of the DPM—a 2112×2112 pixel display according to an embodiment of the present disclosure;
[0035] FIG. 3 is a DPM operation flow chart according to an embodiment of the present disclosure;
[0036] FIG. 4 is a partial array diagram according to an embodiment of the present disclosure;
[0037] FIG. 5 is a row formatter detail according to an embodiment of the present disclosure;
[0038] FIGS. 6a and 6b show a pixel data latch schematic (6a) and a layout view (6b) according to an embodiment of the present disclosure;
[0039] FIG. 7 is an optimized layout of 8 pixel data latches according to an embodiment of the present disclosure;
[0040] FIG. 8 is a waveform generator detail according to an embodiment of the present disclosure;
[0041] FIG. 9 is a logic diagram of a DPM pixel according to an embodiment of the present disclosure;
[0042] FIG. 10 is a pixel schematic according to an embodiment of the present disclosure;
[0043] FIG. 11 a simple G-bus Waveform example according to an embodiment of the present disclosure;
[0044] FIG. 12 is a Pixel electrode waveform for the data pattern “10101010” using the G-bus Waveform of FIG. 11;
[0045] FIG. 13 is a pixel logical diagram for another embodiment of the disclosure.
[0046] FIG. 14 is a waveform generator block diagram for another embodiment of the disclosure;
[0047] FIG. 15 is an example Gamma curve implemented by embodiments of the disclosure;
[0048] FIG. 16 is an illustration of the contents of the waveform generator memory for the waveform generator of FIG. 14; and
[0049] FIG. 17 is a G-bus waveform diagram for another embodiment of the disclosure.
DETAILED DESCRIPTION
[0050] FIG. 1 illustrates a simplified block diagram of a typical conventional display system 100. Such known displays rely on a controller (usually in a separate driver IC) 110 to write “Bit-Planes” to the pixel array 120, located within a display circuit 130. The display circuit 130 also includes a column scanner 140, which stores and provides bit-plane data 145 for the pixel array 120, and a row scanner 150, which provides control signals 155 to enable the data 145 to be written into array 120. Each bit-plane write will write either a “1” or “0” to every pixel in the display 120. Any time it is desirable to change the state of any pixel, at any possible gray-code, it is necessary to write an entire new bit-plane to the array 120. This has several disadvantages.
[0051] Firstly, writing a bit-plane takes significant time. For example, HD displays with >2 million pixels typically take between 50 μs and 100 μs to write a bit-plane. This time places a lower limit on how frequently a pixel can change state, and therefore determines the shortest pulse that can appear on a pixel electrode. Secondly, such displays 100 are very inefficient in terms of the array write activity. Most of the time these bit-plane writes will write “1” to pixel memory (e.g., Static Random-Access Memory or SRAM) that are already in the 1-state, and write “0” to SRAMs that are already in the 0-state. These redundant writes do not serve any useful purpose and are wasteful of power. Furthermore, they are inherent in the nature of a bit-plane display 100 and cannot be eliminated without adding a lot of additional complexity to the pixel 120 and array drive circuitry.
[0052] Thirdly, it takes a lot of data bandwidth to feed all this bit-plane data 145 to the display 100, much of which is effectively wasted due to the redundancy noted above. For example, to send a continuous sequence of bit-planes to a 1920×1080 HD display (using 100 μs bit-plane time) takes in excess of 20 Gb/s. Supporting this kind of data flow to a display requires extreme interface technology (wide parallel buses or multiple SERDES links) with the attendant high power consumption these imply. It also places demands on the driver IC 110 that are difficult to support and consumes large amounts of power in that chip as well.
[0053] FIG. 2 illustrates a block diagram of a LCoS display device 200 according to an embodiment of the present disclosure. FIG. 2 includes, but is not limited to, the following components: Control Registers 210; Cache System 220; Display Loader 230; Row Formatter 240; Row Control (Ctrl) 250; Waveform Generator 260; Command FIFO file 270; and 2 k×2 k pixel array 280 (gray block on the right). Other parts of the diagram may vary from one embodiment to another without substantially affecting the basics of embodiments of the present disclosure.
[0054] In FIG. 2 is a storage system 220, for example, a cache system or storage system. In an embodiment of the present disclosure, the storage system includes storage devices, such as memory devices. The cache or storage system 220 contains working copies of image data, an image or images organized as three (3) color caches for Red 290, Green 300, and Blue 310 data each of 8-bits depth. The image date includes a plurality of bits. It should be understood by one of ordinary skill in the art that the colors may vary. If the display is to be operated as a monochrome display, only one of these will actually be used. The data in these caches 220 is written-in during the previous frame, using whatever image interface is appropriate for the particular display.
[0055] Before actual display operation can begin, an external control device 315 (CPU 316 or other data source or host) must write 330 values to the “Control Registers” 210 to control the operation of the display. The control values may be stored in memory 317 on the external device 315. These control values may contain some or all of the following: image size in X, Y pixels; image offset (if any) from left/top edges; image flip (if desired) in Horizontal and/or Vertical; row-strobe setup and hold timing adjustments; timing resolution of the Waveform Generator 260; number of Waveform Generator pulses per sub-frame; and other mode-control settings. It is also necessary for the external control device 315 to fill up the Command FIFO 270 with a series of internal commands. Some of these commands define the exact waveform and timing for the Waveform Generator 260. For example, the duration of each voltage pulse on the G-bus line may also be programmable via commands written to the display from software on the host or source. In one embodiment, there may be no temporal overlap between the voltage pulses on different G-bus lines. Turning to the flow-chart 400 provided in FIG. 3, once the control registers have been written, the display 280 waits for a “Start of Frame” event at step 410. Generally, this will be decoded by a communications interface, for example, a MIPI interface. For a Color Sequential device such as shown in FIG. 2, there will actually be 3 or more color sub-frames. In this case, the flow-chart shown in FIG. 3 applies to each of these color sub-frames.
[0056] FIG. 4 illustrates a simplified diagram of the “pixel array” 280 according to one embodiment of the disclosure. The array 280 is just a rectangular matrix of individual pixels. It should be understood by one of ordinary skill in the art that the shape of the pixel array may vary. In an embodiment of the disclosure, the pixels include pixel circuits 285, connected to a regular array of row and column wires. Each of the individual pixel circuits 285 has a “Pixel Electrode” or LED 630 (see FIG. 9) connected to its output in an embodiment of the present disclosure, the Pixel Electrodes 630 may be square metal plates that lie directly over the pixel circuit 285. In an embodiment of the present disclosure, the pixel electrode may be a reflective device, for example a metallic reflective mirror device. In an embodiment of the present disclosure, the electrode may be an LED or an electrode coupled to an LED. In an embodiment of the present disclosure, the electric field that controls the behavior of the Liquid Crystal forms between these Pixel Electrodes 630 and the Vcom electrode (not shown), which is a continuous transparent conductive film on the opposite side of the Liquid Crystal. The Liquid Crystal may be a Liquid Crystal on silicon array (LCoS) including a liquid crystal layered between two substrates. For purposes of describing embodiments of the present disclosure, an LCOS display is reference. However, the embodiments of the present disclosure, may incorporate or be used with other types of displays, for example an LED display, such as a microLED display. Also, any reference to a display is likewise a reference to a microdisplay.
[0057] The array 280 is set up so that individual rows of pixel circuits 285 can be written in one operation, by asserting the “L_x” and “Ln_x” row strobe pair of inputs or data inputs for that row, where the “_x” just indicates which row is being driven. Note that in FIG. 4 all the inputs or outputs (G[7:0], L, Ln, Gset, UPDATE, RRead, D[7:0], GXOR, and DATAOUT) have similar “_x” notation appended to them. This serves to indicate which row or column each voltage is associated with. In an actual implementation, some of these inputs/outputs will be buffered versions of the originating signal, in order to keep circuit loading from becoming too high. For example, in the first column the D[7:0]_0 voltage drives the inputs to 2112 pixel circuits in the first column. This is already a fairly heavy electrical load, and, in an embodiment of the present disclosure, D[7:0]_0, D[7:0]_1, D[7:0]_2, . . . are each driven from non-inverting buffers connected to a “master” D[7:0] The “_x” notation and these buffering issues will be omitted in the rest of description required for clarity purposes. In addition, FIG. 4 shows input “RRead_x” and output “DATAOUT_x”. These are internal test inputs/outputs used for on-chip testing. It should be understood by one of ordinary skill in the art that the number of pixels, number of pixel circuits, and the size of each pixel may vary in embodiments of the present disclosure.
[0058] Referring back to the flow chart 400 of FIG. 3, once the Start-of-Frame signal 410 has been received by the row controller or “Display Loader” 230 from the data source (via the Parser 275 and Command FIFO 270, using a timebase 276) the Display Loader 230 begins to write 420 the appropriate data into the “Row Formatter” 240 during the next 16 clocks. A simplified diagram of the Row Formatter 240 is shown in FIG. 5. The arrows 245 represent 16 writes of 1024 bits each, which has arrived from the Display Loader 230. The Row Formatter 240 handles image flip and offset, and routes the data into a row-buffer register 255 that is inside the Row Formatter 240. It also performs padding the 2048 active image columns with 64 additional “steering” data columns. It should be understood by one of ordinary skill in the art that the number of steering columns may vary. The row-buffer 255 has 2112 individual 8-bit outputs 265 that form the 8-bit “Column-Lines” of the array. These outputs 265 of the row-buffer 255 are connected to the display columns of the array 280, as showing in FIG. 4. Once the row buffer 255 is filled up, the Display Loader 230 (via the “Row Cntrl” block 250) asserts 430 the first “L/Ln” row strobe data pair for the first row. It should be understood by one of ordinary skill in the art that the number of bits may vary, data may be expressed by a voltage, and the number of bit outputs may vary.
[0059] For each pixel in the row, the L/Ln voltage pair enables an 8-bit data latch 500 in the pixel to capture (or latch) the data from the associated column. In an embodiment of the present disclosure, there may be, between and including, four to ten latches. However, it should be understood by one of ordinary skill in the art that the number of latches may vary. This strobe pair of L/Ln voltage remains asserted for a few clocks (the exact number is programmable via a field in the Control Register) in order to give all the data latches in the first row of pixel circuits time to capture the data. Once these few clocks are up, the L/Ln pair is de-asserted. FIG. 6a shows the schematic of the Pixel Data Latch 500 (for 1-bit), and FIG. 6b is a simplified view of how this appears when arranged on the silicon or backplane of a display. FIG. 7 shows a 4×2 (w/h and V mirroring) array 550 of 8 of these latches 500, which is what is used in each pixel. This illustrates that the latch design can be arrayed together very compactly. The Pixel Data Latch 500 schematic is a variant of the standard “6T” SRAM. It has been modified to include “unloading” transistors which allow ordinary logic signals to easily set or clear this latch when the “L” and “Ln” latch enable is asserted. The complementary pair of inputs L & Ln are used instead of a single-ended input because it makes the pixel transistor-level design simpler. However, in an embodiment of the present disclosure, a single ended input may be utilized by adding additional inversion logic.
[0060] Subsequently, Display Loader 230 again begins to write 440 the appropriate data into the row-buffer 255 of the “Row Formatter” 240, and asserts 450 the next “L/Ln” row strobe pair for the next row. At step 460 in FIG. 3, the display device 200 checks to see if the last row has been reached. If not, steps 440 to 460 is repeated until all 2112 rows in the array 280 have been written. At this stage, all pixels in the array 280 now contains the image data. This entire process may take approximately 50-100 μs.
[0061] At this point in time, all of the data needed for the current frame (or color sub-frame if this is a Color Sequential display) has been loaded into the pixel data latches, and the actual display process can begin. From this point until the start of the next frame or sub-frame, the data interface and cache memories are not used, and all display data needed to define the image resides within the static-ram pixel data latches 500 of the pixels.
[0062] The process is now at the “Send Start command to Waveform Generator” at box 470 in FIG. 3. A simplified block diagram of the Waveform Generator 260 is shown in FIG. 8. The Waveform Generator 260 receives a command 274 from the Command FIFO 270. Additionally, the Waveform Generator 260 comprises a waveform generator timebase 266, which is a logic block that processes a clock to produce a further clock and optionally a start/stop signal and sends these digital signals 267 to drive both a loadable/clearable address counter 268, and a waveform generator memory 272. At step 260, the waveform memory address in the memory 272 is set to “0”. The function of the Waveform Generator 260 is to drive a pattern of pulses (represented by G[7:0]) onto the 8-bit “G-bus” 262 that in turn connects to every pixel in the display 280, and to drive the “Gset” signal which is also routed to every pixel in the display 280. The G-bus 262 works with the logic in each pixel to convert the pixel data stored in the pixel data latches 500 into waveforms that are presented on the pixel electrodes 630 or to the pixels 281. The G-bus signals serve to sequentially gate versions of the individual bits of the pixel data latches 500 onto the pixel electrodes 630, with the amount of time each is gated onto the pixel electrodes 630 being determined by the timing of the G-bus signals. The Gset signal is a latch-enable for the pixel output latch. The actual waveform on the G-bus 262 is programmable, and indeed must be programmed at the start of operation. Determining this waveform is a complex process involving simulations of the LC behavior. However, there are some common rules that these waveforms must obey for proper DPM operation: 1) only one of the 8 G-bus signals can be true (“1”) at any instant in time; 2) there must be at least 1 pulse on each line in the G-bus in each “sub-cycle” or “sub-frame”; and 3) there must be a Gset pulse coincident with the start of each pulse on any of the 8 lines of the G-bus.
[0063] To understand how this works, it is helpful to look more closely at the logic in a pixel, and a minimal G-bus waveform. FIG. 9 shows a pixel block diagram 600 showing the pixel logic. The pixel logic 600 has been designed to be implemented with very few transistors. As can be seen in FIG. 9, there is a row of 8 AND-gates 610, and OR gates 620 to collect the outputs from the AND-gates 610. Normal “Standard-Cell” AND or OR gates typically takes about 8-10 transistors each, and a standard-cell D-Latch (like the pixel data latches can take 20 or more transistors). However, in embodiments of a latch in accordance with embodiments of the present disclosure only 8 transistors are used, and single FETs as AND gates are used. This can be done in some cases, and the design has been deliberately crafted to make this possible. In FIG. 9, it can be seen that the output of the OR gates 620 is fed into another AND gate 640, together with the Gset from the Waveform Generator 260. The same Gset is also fed directly into an output latch 650, along with the output of the AND gate 640. In some embodiments, the output of the latch 650 is fed into a XOR gate 660, along with a related GXOR signal. The signal GXOR and a related XOR gate are optional features, and are not required in all implementations. Their purpose is to invert the waveform going to the level-shifter 670. This is an advantage in non-Color-Sequential applications, where it is usually necessary to replay an inverted version of the image in order to achieve DC-balance and to avoid image-sticking. By including this XOR function 660, the image can be inverted without needing to reload the image. For Color-Sequential applications this capability has no value. Displays designed for such applications will usually omit this gate and the related control signals. Finally, the output of the XOR gate (or the latch 640) is directed to pixel electrodes 630
[0064] FIG. 10 shows a transistor-level pixel schematic 700 of pixel logic of FIG. 9. A dashed-rectangle shows the FETs that are AND-gate 610 equivalents, and the common connection pointed out functions as a “Wired-NOR” structure in place of the OR-gates 620. Again, Wired-OR or Wired-NOR connections are a circuit feature well-known to practitioners of digital design, and the use in this case saves a lot of transistors. It is estimated that this pixel design would take in excess of 250 transistors if implemented using Standard-Cell logic, but this version takes approximately 95 transistors (not including the level-shifter, which uses larger high-voltage transistors). It has been shown that all this circuitry, including a suitable level-shifter 670, can be laid-out to fit in a small pixel area, for instance in a 3 um×3 um pixel using a 28 nm process geometry.
[0065] FIG. 10 shows one version of the Pixel Electrode Level-Shifter 670, but other Level-Shift designs could be used with embodiments of this present disclosure without changing its validity. Additionally, there are other modifications that could be made to the design that do not invalidate it. For example, PFET transistors could be used instead of NFET ones, the Q and Qn outputs of the data latches 500 could be exchanged, signals could be replaced by their inverted versions, a non-differential version of the row strobe (L/Ln) could be utilized, etc. As mentioned before, the signal GXOR and a related XOR gate 660 are optional features of embodiments of the present disclosure.
[0066] FIG. 11 illustrates a simple G-bus waveform 800. As can be seen, the G-bus signals are binary-weighted pulses, with the MSB on G[7] and the LSB on G[0]. Looking at the start of the waveform 800, imagine that the data pattern in this pixel is decimal 170, which in binary is “10101010” (this was stored on the “8-bit latch” 550 in the pixels during the data load operation). FIG. 11 illustrates that G[7] is true for the first half of the 32 μs sub-frame (this is step 480 in FIG. 3, where the waveform generator 260 outputs a pulse for G[7]). At step 490, a comparison between G[7] and D[7] is done to see if their corresponding bits match. FIG. 9 illustrates that if G[7] is “1”, and if D[7] is also “1” (as is true for decimal 170), this will result in a “1” at the output of the uppermost AND gate. This 1 will be passed through the OR gates 620 and will end up at the input of the output latch 650 (step 491), but only when the Gset signal is also set to true. This will set the output latch 650, whose output passes through the level-shifter 670 and ends up on the pixel electrode 630. The result is that the pixel electrode 630 will be high for the first half of the frame.
[0067] At the end of the G[7] pulse, FIG. 11 illustrates that a new pulse begins on G[6]. However, the bit from the data latch 550 for D[6] is a “0”. Since G[6] and D[6] are AND′ d together, the output of this AND gate will be 0 and this 0 will end up at the input of the output latch 650 (step 492 in FIG. 3). If a Gset pulse is present at the beginning of the G[6] pulse, this will result in the output latch 650 being cleared to the low state and based on the G-bus timing this will mean that the pixel electrode 630 voltage will be low for the next ¼ of the frame. At the end of the G[6] pulse, there is a new pulse on G[5], and since D[5] is also “1” the G[5] pulse will end up causing the output latch to be set again, and pixel electrode 630 will again be high—this time for the next ⅛ of the sub-cycle. This repeats sequentially for G[4], G[3], G[2], G[1], and G[0].
[0068] Thus, after each pulse the display device 200 checks to see if the previous pulse was the last pulse stored in the waveform memory 272 (step 495 in FIG. 3). If not, the waveform memory address in memory 272 is incremented by one (step 496), and steps 480 to 495 are repeated. Otherwise, the Gset signal is pulses with “0” to end the waveform at step 497. At this time, voltage waveform is generated on the pixel electrode 630 based on the data value of “10101010”, pulses that are alternating high—low—high—low—high—low—high—low, with the total sequence taking 32 μs in this example.
[0069] FIG. 12 shows this resulting voltage waveform 900 of the above process. Exact values for “high” and “low” depend on the level-shifter 670 and external Vpix supplies (these are not shown).
[0070] FIG. 11 and FIG. 12 illustrate a 32 μs period during which each bit of the data on the data latch 550 is used. This is what is referred to herein as a “sub-cycle” or “color sub-frame”, and 32 μs is a realistic minimum sub-frame duration. In some applications, image frames or color sub-frames last much longer than 32 μs, so this process may be repeated for as many times as are required to fill-up the frame or sub-frame. Indications of this can be seen in FIG. 12, where the end of the previous sub-frame and the beginning of the following sub-frame can be seen. The total time resulting from the number of segments in the sub-frame multiplied by the number of repetitions of the sub-frame, must be equal or less than the length of the waveform memory. Note also that the waveform generator 260 has a programmable time-base. If desired, different time-base values can be used to make the sub-frame be proportionally longer or shorter, as needed. Finally, it can be noted advantageously that 1) nothing in this system requires only 1 pulse per G-bus line, and 2) nothing requires the G-bus pulses to be in any particular order. For example, the MSB could be divided into say 4 pieces each of ¼ the normal duration, and these pieces could be scattered among the other pulses. This flexibility is an important advantage of embodiments of the present disclosure and allows the exact behavior of the DPM modulation to be almost infinitely tweaked. It is envisioned that multiple different Waveform Generator patterns according to the embodiments herein may be designed depending on the needs of specific customers and/or display applications. These may be included in system software according to embodiments of the present disclosure and can be loaded during a system boot-up process.
[0071] The action of the circuitry of the embodiments of this disclosure result in a binary-weighted waveform at the pixel electrode 630 or pixel 281 that repeats a fixed number of times during the frame. How this affects the LC state depends on the waveform timing. The Liquid-Crystals commonly in use in microdisplays like this have rise and fall times in the range of 400 μs to 2 ms. For voltage pulses at the pixel electrode equal to or longer than say ˜100 μs, the LC can at least begin to respond to the voltage pulse by at least beginning to change state during the pulse. For example, for a drive waveform consisting of intermediate-length pulses like these, it becomes quite difficult to predict the response. The LC sees the pulses as long-enough to approach a steady-state conditions and tries to fully respond to them, becoming fully-on or fully-off. Generally, the pulses are not long enough to quite allow a full response before the next pulse begins. The result is that the LC exhibits a “history effect”, where its response to any given pulse sequence depends on the history of recent previous pulses. This is nearly impossible to correct for, and as a result displays of this sort have to use PWM techniques—these are more resistant to errors due to history effects.
[0072] When observing the output with a fast-responding light sensor, the LC transmission would rapidly vary between mostly “on” and mostly “off” while displaying a mid-gray, for example. (“Rapidly” in this context is with rise/fall times in the 400 μs to 2 ms range, as noted previously). The eye can average these out and give an acceptable appearance of continuous-tone gray-scale, although getting a smoothly varying gray-ramp can be difficult because of the non-linear consequences of the History-effect. However, when trying to operate in Phase-mode this does not work at all because phase errors actually affect the details of image feature positions, and the eye cannot average this out.
[0073] However, the situation changes dramatically if the pulse-lengths become much shorter, and this is why DPM has a big advantage. Embodiments of the present disclosure are not restricted to bit-plane timing, and so the individual pulses in a DPM sub-frame can be as short as desired. In an embodiment, the DPM has the complete sub-frame as short as 32 μs, with individual pulses as short as 125 ns. The LC cannot respond in any substantial way to the individual pulses in such a sequence. Instead, the LC or pixel 281 will respond to the RMS equivalent of the voltage on the pixel electrode 630. This is both a quantitative and qualitative difference. In conventional digital displays, the eye averages the optical appearance of a series of LED or LC-generated light pulses into an equivalent gray-scale. In contrast, in a DPM digital display according to embodiments of the present disclosure, the Liquid-Crystal averages a series of voltage pulses into an equivalent gray-scale. LC displays respond to an emulated series of DPM-style voltage pulses in exactly the same way that they respond to the RMS-equivalent DC voltage.
[0074] The advantages for an Amplitude-mode display are mainly that true 8-bit operation without needing to resort to dithering is readily possible (because one can generate shorter pulses than would be possible in a bit-plane display). The advantages for a Phase-mode display are more dramatic. The phase smoothness (or amount of phase-ripple) for a prior-art digital display depends on the length of a bit-plane, as noted typically 50 μs to 100 μs. This bit-plane timing causes significant alternating overshoot and undershoot in a prior-art phase-mode display (generally 2-5%) which are very objectionable, and interferes with getting a clear phase-mode image. Because DPM phase-mode displays according to embodiments of the present disclosure, do not have this minimum bit-plane duration requirement, they can readily generate phase-shifts with peak ripple numbers at least an order of magnitude (10×) smaller than comparable non-DPM displays.
[0075] FIG. 12 includes a dashed line 910. This is an indication of what this pulse sequence would look like to the Liquid Crystal. This is the case because the longest pulse in this sequence is 16 μs, which is about 1/30.sup.th of the normal LC rise or fall time. Because these pulses are so much shorter than the LC can respond to, the LC responds to the RMS equivalent voltage of the entire sequence—suggested by the dashed line 910.
[0076] In another embodiment 1000 of the pixel, illustrated in FIG. 13, the AND/OR tree is replaced by a more complex logic function 1010, such as XOR/OR, forming a comparison function between the value stored in the Pixel Memory 1020 and the value on the G bus 262. As before, a GSET signal is provided which pulses at each change of the G bus value to update the final latch 1030 that is coupled to the final pixel driver or Level Shifter 1040. In an embodiment, the G bus 262 may contain a multi-bit binary counting pattern, increasing or decreasing in value at certain programmed points in time, and the logic function 1010 will cause the logic result Y to be true only when the G bus value matches the value stored in the pixel memory 1020. Combined with an initial SET or RESET, this combination results in a pulse-width-modulation (PWM) function where the width of the resulting pulse on the pixel electrode 630 is controlled by both the pixel memory contents and the timing and sequence of values on the G bus 262.
[0077] In an embodiment 2000, the waveform generator of FIG. 8 is replaced by that of FIG. 14 to produce an increasing or decreasing multi-bit value on the G bus 262. As before, waveform generator 2000 receives a command 2010 from the Command FIFO 270, and comprises a waveform generator timebase 2020 and a waveform delta memory 2030. Once the direction is selected, and an initial value (generally 0 or the maximum count, such as 255 for an 8-bit value) is loaded into an Up/Down counter 2040, which drives the G bus 262. The output of the up-down counter 2040 is also used as the address to fetch a data value from a waveform delta memory 2030, and this value is loaded into a down counter 2050. The waveform generator timebase 2020 provides a wave-step clock signal 2060 (a periodic clock waveform) which advances both counters 2040, 2050. When the down counter 2050 reaches 0, the Advance signal 2070 is issued to the Up/Down counter 2040, allowing it to decrement or increment. The incrementing and decrementing of the up/down counter 2040 after programmable numbers of cycles stored in the waveform delta memory 2030 enables the display to have a programmable response. One color sub-frame may comprise many increments/decrements as shown in FIG. 17 discussed below. FIG. 15 compares an ideal Gamma curve 3000, with a linear level 3010. Here, the 8-bit Gray Level is expanded into a 16-bit linear light level, according to an exponent Gamma (Gamma=2.2 in this example). For instance, a Gray Level of 50 may correspond to 3% normalized intensity, corresponding to a pulse width of 487 wave-step clock periods, and a gray level of 200 may correspond to a normalized intensity level of 58%, corresponding to a pulse width of 9421 wave-step clock periods.
[0078] FIG. 16 illustrates example contents of the waveform delta memory 2030. In this example, the desire is to have the Gray Level value, corresponding to the value stored in each Pixel Memory map to a pulse whose width is equal to the number of wave-step clock periods, or clock periods of the wave-step clock signal. With the prescribed structure of the waveform generator 2000 from FIG. 14, one only needs to store the difference between desired duration values in the waveform delta memory 2030 as shown in the Waveform Delta column.
[0079] FIG. 17 illustrates the sequence of values on the G bus 262 generated by the waveform generator of FIG. 14 2000, illustrating a counter 4010, and the corresponding pixel output 4020 for approximately 16,000 steps representing one color sub-frame 4030. The top part 4040 presents a down-counting sequence and the bottom part presents an up-counting sequence 4050. Larger values, such as 255, may be programmed to persist on the bus 262 for longer periods of time, while lower values may be programmed to persist for shorter periods of time. Displays according to the principles and embodiments described herein have unique characteristics not available using any other technology, particularly in the area of phase modulation. Embodiments herein include a small-pixel phase microdisplay capable of near-zero phase ripple, high efficiency, high contrast, and 8-bits of phase modulation depth. Because no external driver chip is needed, and because small pixels (3 um-4 um) are possible, the overall display size is smaller than existing display plus driver solutions. The combination of high-bit-depth, high optical efficiency and contrast, and small physical size make it a natural fit for the emerging application areas of Augmented Reality, other Head-Mounted display applications, and compact Heads-Up vehicle displays using Amplitude mode.
[0080] The phase-modulation capability of the embodiments herein are also a significant advantage. The combination of high-bit-depth (8 bits), high speed, very-low phase ripple, and small pixels are suitable for devices such as holographic display applications, which have wide diffraction angles and require small pixels. Thus, the embodiments herein which provide sizes of approximately 3 μm are ideal when optical efficiency and wide diffraction angles are required.
[0081] The subject matter described herein can be implemented in digital electronic circuitry, or in computer software, firmware, or hardware, including the structural means disclosed in this specification and structural equivalents thereof, or in combinations of them. The subject matter described herein can be implemented as one or more computer program products, such as one or more computer programs tangibly embodied in an information carrier (e.g., in a machine readable storage device), or embodied in a propagated signal, for execution by, or to control the operation of, data processing apparatus (e.g., a programmable processor, a computer, or multiple computers). A computer program (also known as a program, software, software application, or code) can be written in any form of programming language, including compiled or interpreted languages, and it can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. A computer program does not necessarily correspond to a file. A program can be stored in a portion of a file that holds other programs or data, in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files that store one or more modules, sub programs, or portions of code). A computer program can be deployed to be executed on one computer or on multiple computers at one site or distributed across multiple sites and interconnected by a communication network.
[0082] The processes and logic flows described in this specification, including the method steps of the subject matter described herein, can be performed by one or more programmable processors executing one or more computer programs to perform functions of the subject matter described herein by operating on input data and generating output. The processes and logic flows can also be performed by, and apparatus of the subject matter described herein can be implemented as, special purpose logic circuitry, e.g., an FPGA (field programmable gate array) or an ASIC (application specific integrated circuit).
[0083] Processors suitable for the execution of a computer program include, by way of example, both general and special purpose microprocessors, and any one or more processor of any kind of digital computer. Generally, a processor will receive instructions and data from a read only memory or a random access memory or both. The essential elements of a computer are a processor for executing instructions and one or more memory devices for storing instructions and data. Generally, a computer will also include, or be operatively coupled to receive data from or transfer data to, or both, one or more mass storage devices for storing data, e.g., magnetic, magneto optical disks, or optical disks. Information carriers suitable for embodying computer program instructions and data include all forms of nonvolatile memory, including by way of example semiconductor memory devices, (e.g., EPROM, EEPROM, and flash memory devices); magnetic disks, (e.g., internal hard disks or removable disks); magneto optical disks; and optical disks (e.g., CD and DVD disks). The processor and the memory can be supplemented by, or incorporated in, special purpose logic circuitry.
[0084] The subject matter described herein can be implemented in a computing system that includes a back end component (e.g., a data server), a middleware component (e.g., an application server), or a front end component (e.g., a client computer mobile device, wearable device, having a graphical user interface or a web browser through which a user can interact with an implementation of the subject matter described herein), or any combination of such back end, middleware, and front end components. The components of the system can be interconnected by any form or medium of digital data communication, e.g., a communication network. Examples of communication networks include a local area network (“LAN”) and a wide area network (“WAN”), e.g., the Internet.
[0085] It is to be understood that the disclosed subject matter is not limited in its application to the details of construction and to the arrangements of the components set forth in the following description or illustrated in the drawings. The disclosed subject matter is capable of other embodiments and of being practiced and carried out in various ways. Also, it is to be understood that the phraseology and terminology employed herein are for the purpose of description and should not be regarded as limiting. As such, those skilled in the art will appreciate that the conception, upon which this disclosure is based, may readily be utilized as a basis for the designing of other structures, methods, and systems for carrying out the several purposes of the disclosed subject matter. It is important, therefore, that the claims be regarded as including such equivalent constructions insofar as they do not depart from the spirit and scope of the disclosed subject matter.
[0086] Although the disclosed subject matter has been described and illustrated in the foregoing exemplary embodiments, it is understood that the present disclosure has been made only by way of example, and that numerous changes in the details of implementation of the disclosed subject matter may be made without departing from the spirit and scope of the disclosed subject matter, which is limited only by the claims which follow.
