Method of Operating an Inverter and Inverter

Abstract

A method operates an inverter by driving respective switching means of the bridge arms using pulse width modulation with a temporally changeable duty cycle such that voltages between the bridge connections have a temporally predefined profile. The respective switching means of the bridge arms are driven with flat-top modulation for particular angular ranges of a respective fundamental oscillation. A respective duty cycle for the respective switching means of the bridge arms is selected such that, during a respective period of the pulse width modulation, at least two shunt resistors always perform their measurement function for a minimum time.

Claims

1.-5. (canceled)

6. A method for operating an inverter, wherein the inverter comprises: a number of bridge arms having respective bridge connections, wherein a respective bridge arm is electrically connected to a first intermediate circuit pole of the inverter on a first side and wherein a respective bridge arm is electrically connected to a second intermediate circuit pole of the inverter on a second side, wherein a respective bridge arm has at least two switching means, wherein a respective bridge connection is electrically connected, depending on a switching state of the switching means of the bridge arm, either to the first intermediate circuit pole or to the second intermediate circuit pole, and wherein a shunt resistor is arranged in a respective bridge arm, which shunt resistor performs or does not perform a measurement function depending on a switching state of the switching means, wherein the method comprises the steps of: driving the respective switching means of the bridge arms using pulse width modulation with a temporally changeable duty cycle such that voltages between the bridge connections have a temporally predefined profile, wherein the respective switching means of the bridge arms are driven with flat-top modulation for particular angular ranges of a respective fundamental oscillation, and wherein a respective duty cycle for the respective switching means of the bridge arms is selected such that, during a respective period of the pulse width modulation, at least two shunt resistors always perform their measurement function for a minimum time.

7. The method according to claim 6, wherein the minimum time is greater than 5 s.

8. The method according to claim 7, wherein a respective duty cycle for those switching means of the bridge arms that electrically connect the respective bridge connection to the second intermediate circuit pole is selected such that, at the same time, at least two duty cycles are always greater than a threshold value.

9. The method according to claim 6, wherein a control angle of the pulse width-modulated driving satisfies the following: 3030 and 0.

10. An inverter, comprising: a number of bridge arms having respective bridge connections, wherein a respective bridge arm is electrically connected to a first intermediate circuit pole of the inverter on a first side and wherein a respective bridge arm is electrically connected to a second intermediate circuit pole of the inverter on a second side, a respective bridge arm has at least two switching means, wherein a respective bridge connection is electrically connected, depending on a switching state of the switching means of the bridge arm, either to the first intermediate circuit pole or to the second intermediate circuit pole, and a shunt resistor is arranged in a respective bridge arm, which shunt resistor performs or does not perform a measurement function depending on a switching state of the switching means; and a control unit that is configured to: drive the respective switching means of the bridge arms using pulse width modulation with a temporally changeable duty cycle such that voltages between the bridge connections have a temporally predefined profile, wherein the respective switching means of the bridge arms are driven with flat-top modulation for particular angular ranges of a respective fundamental oscillation, and wherein a respective duty cycle for the respective switching means of the bridge arms is selected such that, during a respective period of the pulse width modulation, at least two shunt resistors always perform their measurement function for a minimum time.

11. The method according to claim 10, wherein the minimum time is greater than 5 s.

12. The method according to claim 11, wherein a respective duty cycle for those switching means of the bridge arms that electrically connect the respective bridge connection to the second intermediate circuit pole is selected such that, at the same time, at least two duty cycles are always greater than a threshold value.

13. The method according to claim 10, wherein a control angle of the pulse width-modulated driving satisfies the following: 3030 and 0.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The invention is described in detail below with reference to the drawings, in which:

[0025] FIG. 1 shows a schematic circuit diagram of an inverter according to the invention,

[0026] FIG. 2 shows angle-dependent profiles of duty cycles of switching means of the inverter illustrated in FIG. 1,

[0027] FIG. 3 shows angle-dependent profiles of voltages between bridge connections of the inverter illustrated in FIG. 1, and

[0028] FIG. 4 shows, by way of example, a pulse width-modulated driving signal of a switching means of the inverter illustrated in FIG. 1.

DETAILED DESCRIPTION OF THE DRAWINGS

[0029] FIG. 1 shows an inverter 1 having three bridge arms 2, 3, 4 with respective bridge connections 13, 14 and respectively 15. A three-phase current motor may be connected to the bridge connections 13, 14 and 15, for example. The bridge connections 13, 14 and 15 may correspond for example to phase potentials U, V and W, respectively, as illustrated.

[0030] A respective bridge arm 2, 3, 4 is electrically connected to a first intermediate circuit pole 5 of the inverter 1 on an upper side and electrically connected to a second intermediate circuit pole 6 of the inverter 1 on a lower side. A positive intermediate circuit potential is present at the first intermediate circuit pole 5 and a negative intermediate circuit potential is present at the second intermediate circuit pole 6, a potential difference between these potentials forming an intermediate circuit voltage that is buffered by way of an intermediate circuit capacitor 21.

[0031] The first bridge arm 2 has two series-connected semiconductor switching means 7 and 8 and a shunt resistor 16 connected between the semiconductor switching means 8 and the second intermediate circuit pole 6. The first semiconductor switching means 7, the second semiconductor switching means 8 and the shunt resistor are connected in series between the first intermediate circuit pole 5 and the second intermediate circuit pole 6. The bridge connection 13 is formed by a connecting point between the semiconductor switching means 7 and 8 and is therefore electrically connected to the first intermediate circuit pole 5 when the first semiconductor switching means 7 is in the on state and the second semiconductor switching means 8 is in the off state. Accordingly, the bridge connection 13 is electrically connected to the second intermediate circuit pole 6 via the shunt resistor 16 when the second semiconductor switching means 8 is in the on state and the first semiconductor switching means 7 is in the off state.

[0032] The second bridge arm 3 accordingly has two series-connected semiconductor switching means 9 and 10 and a shunt resistor 17 connected between the second semiconductor switching means 10 and the second intermediate circuit pole 6. The first semiconductor switching means 9, the second semiconductor switching means 10 and the shunt resistor 17 are connected in series between the first intermediate circuit pole 5 and the second intermediate circuit pole 6. The bridge connection 14 is formed by a connecting point between the semiconductor switching means 9 and 10 and is therefore electrically connected to the first intermediate circuit pole 5 when the first semiconductor switching means 9 is in the on state and the second semiconductor switching means 10 is in the off state. Accordingly, the bridge connection 14 is electrically connected to the second intermediate circuit pole 6 via the shunt resistor 17 when the second semiconductor switching means 10 is in the on state and the first semiconductor switching means 9 is in the off state.

[0033] The third bridge arm 4 accordingly has two series-connected semiconductor switching means 11 and 12 and a shunt resistor 18 connected between the second semiconductor switching means 12 and the second intermediate circuit pole 6. The first semiconductor switching means 11, the second semiconductor switching means 12 and the shunt resistor 18 are connected in series between the first intermediate circuit pole 5 and the second intermediate circuit pole 6. The bridge connection 15 is formed by a connecting point between the semiconductor switching means 11 and 12 and is therefore electrically connected to the first intermediate circuit pole 5 when the first semiconductor switching means 11 is in the on state and the second semiconductor switching means 12 is in the off state. Accordingly, the bridge connection 15 is electrically connected to the second intermediate circuit pole 6 via the shunt resistor 18 when the second semiconductor switching means 12 is in the on state and the first semiconductor switching means 11 is in the off state.

[0034] The shunt resistors 16, 17, 18 perform their measurement function (only) when the lower switching means 8, 10 and 12, respectively, are closed for a minimum time and the upper switching means 7, 9 and 11, respectively, are accordingly open.

[0035] The method according to the invention is described in detail below with reference to FIGS. 2 to 4.

[0036] With reference to FIGS. 2 to 4, the lower switching means 8, 10 and 12 of the bridge arms 2, 3 and 4, respectively, are driven using pulse width modulation with a temporally changeable duty cycle PWM1, PWM2 and PWM3, respectively, such that voltages U1, U2 and U3, respectively, between the bridge connections 13, 14, 15 have a temporally predefined, approximately sinusoidal profile. The voltage U1 corresponds to a potential difference between the bridge connections 14 and 15 or V and W, the voltage U2 corresponds to a potential difference between the bridge connections 13 and 14 or U and V, and the voltage U3 corresponds to a potential difference between the bridge connections 15 and 13 or W and U.

[0037] The lower switching means 8 of the bridge arm 2 is driven with the duty cycle PWM1, the lower switching means 10 of the bridge arm 3 is driven with the duty cycle PWM2, and the lower switching means 12 of the bridge arm 4 is driven with the duty cycle PWM3. The profile of the duty cycles for the upper switching means 7, 9 and 11, respectively, results as (1PWM1), (1PWM2) and (1PWM3), respectively.

[0038] With reference to FIG. 4, a value of a respective duty cycle PWM1, PWM2 and PWM3, respectively, indicates to which portion, with respect to a period PER of the pulse width modulation with the period duration PD, a lower switching means 8, 10 and 12, respectively, is connected. A duty cycle of 100% indicates that the lower switching means 8, 10 and respectively 12 is continuously switched on during a period PER. A duty cycle of 0% indicates that the lower switching means 8, 10 and 12, respectively, is continuously switched off during a period PER.

[0039] With continuing reference to FIG. 2, the respective switching means 7, 8; 9, 10; 11, 12 of the bridge arms 2, 3 and 4, respectively, are driven with flat-top modulation for particular angular ranges WB1, WB2, WB3, WB4, WB5, WB6 of a respective fundamental oscillation GS.

[0040] Thus, in the angular range WB1, the lower switching means 12 of the bridge arm 4 is continuously off and the upper switching means 11 of the switch arm 4 is continuously on. A change in switching state of the switching means takes place only in bridge arms 2 and 3.

[0041] In the angular range WB2, the lower switching means 8 of the bridge arm 2 is continuously on and the upper switching means 7 of the bridge arm 2 is continuously off. A change in switching state of the switching means takes place only in bridge arms 3 and 4.

[0042] The same applies to the angular ranges WB3 to WB6.

[0043] As illustrated in FIG. 2, a respective duty cycle PWM1, PWM2, PWM3 for the respective switching means 8, 10 and 12 of the bridge arms 2, 3 and 4, respectively, is selected such that, at the same time, at least two duty cycles are always greater than 8%. This has the effect that at least two of the shunt resistors 16, 17, 18 are always able to perform their measurement function for a minimum time of 10 s within a period of the pulse width modulation.

[0044] With reference to FIG. 4, a control angle of the pulse width-modulated driving is 30.

[0045] The invention allows power loss-optimized driving of an electric motor in connection with an improved emitter current measurement. To reduce the inverter switching losses, flat-top modulation is applied instead of sine-weighted modulation. In this case, for the predefined angular ranges, a switching means or end-stage switch of a bridge arm is constantly switched on, and the inverse is switched off (blocking operation). Only the switching means of the remaining bridge arms are driven using pulse width modulation. This considerably reduces the switching losses.

[0046] The flat-top modulation is performed in a current vector-optimized manner, that is to say the blockwise switching on of a switching means is phase-shifted by 30. Due to the fact that the chained motor voltage then reaches the maximum value in the region of non-pulsed operation, the maximum current is also present here (at cosphi=1).

[0047] A potential problem here is the measurement of the motor currents by way of an emitter shunt current measurement. Since two upper switching means are switched on at the same time in certain angular ranges, a reliable current measurement would not be possible. Depending on the switching frequency, around 8% duty cycle is necessary in order to ensure a sufficiently long switch-on time of the lower IGBT (for example 10 s at 8 kHz PWM).

[0048] Immediately before two duty cycles undershoot the threshold of for example 8% duty cycle at the same time, early switching is performed to the blocking operation of the lower switching means by way of one of the bridge arms, such that a situation whereby two duty cycles undershoot the threshold of for example 8% duty cycle at the same time is avoided. It is thereby always ensured that two current measurements deliver a correct value. The third current value may be calculated using a sum current formula.

[0049] The current measurement values of the shunt resistors of the bridge arms having the two highest duty cycles are used to measure the current.

[0050] It is furthermore advantageous in the method according to the invention that, before switching into the respective next block, all three lower switching means are always active (>>8%). A sample and hold capacitor of a current sensor system is thus already charged in good time. There are no corners in the current measurement signal.

[0051] By way of example, the following advantages are able to be achieved by way of the invention in comparison with a conventional sine modulation: a cost saving (smaller heat sinks, IGBT), smaller structural size of the inverters or frequency converters that comprise such inverters, lower power loss in the frequency converter, and lower bearing currents in the motor.

[0052] By way of example, the following advantages are able to be achieved by way of the invention in comparison with a conventional flat-top modulation: better current measurement quality, and lower power loss since there is blocking operation at maximum current.

[0053] In comparison with a conventional current vector-oriented flat-top modulation, it is possible to achieve an improved current measurement quality.