PATTERNING OF ELECTROLESS METALS

Abstract

The present invention relates to methods and systems that utilize a catalyst or thin metal film by atomic level deposition (ALD) of one or more metals that allows fine traces deposition to the trench formed in a dielectric material, thereby minimizing potential physical damage due to embedded conductor format and making the fine space between traces to prevent electromigration in the traces.

Claims

1. A method of patterning of a metal deposited by electroless plating in a multi layered circuitry comprising: activating a surface of a substrate by depositing a first catalyst layer comprising a first catalyst material; masking a first negative circuit pattern on the first catalyst layer using a first dielectric material; applying a first electroless metal onto a non-masked portion of the first catalyst layer; and wherein the first catalyst layer has an average thickness of less than 50 nanometers.

2. The method of claim 1, wherein the substrate comprises at least one of the group consisting of a polyimide, a film, a cloth, a plastic, a metal, a ceramic, and a resin.

3. The method of claim 1, wherein the substrate comprises a printed circuit board.

4. The method of claim 1, wherein the first catalyst material comprises at least one of the group consisting of palladium, silver, gold, nickel, copper, rhodium, cobalt, iridium, and platinum.

5. The method of claim 1, wherein the first catalyst material is deposited as a first catalyst precursor over the substrate and then is activated to an almost zero valent metal.

6. The method of claim 5, wherein the first catalyst precursor comprises an organo-metal.

7. The method of claim 6, wherein the organo-metal comprises a metal carboxylate.

8. The method of claim 1, wherein the first catalyst layer has an average thickness of less than 25 nanometers.

9. The method of claim 1, wherein the first catalyst layer has an average thickness of less than 15 nanometers of the catalyst.

10. The method of claim 1, wherein the first dielectric material comprises at least one of the group consisting of an epoxy resin, a cyanate ester resin, a polyphenylene ester resin, a polyimide resin, a bismaleimide trianzine resin, a polyethylene terephthalate resin, a hydrocarbon resin, a polyfluoro carbon, a LCP resin and an inorganic resin.

11. The method of claim 1, wherein the first dielectric material is photosensitive.

12. The method of claim 1, wherein the first electroless metal comprises at least one of the group consisting of copper, nickel, palladium, platinum, tin, silver, and gold.

13. The method of claim 1, further comprising: a) depositing a second catalyst layer comprising a second catalyst material onto each the first dielectric material and the first electroless metal; b) depositing a second dielectric material over the second layer of the second catalyst material; c) masking a second negative pattern (optionally including a z-axis connection) onto the second catalyst layer using a second dielectric material; d) depositing a second electroless metal onto a non-masked portion of the second catalyst layer; and e) optionally repeating the method from step (a) to step (d), thereby generating a multilayer circuit, wherein each of the first, second and any subsequent catalyst layers independently has an average thickness of less than 50 nanometers.

14. The method of claim 13, wherein each of the second and subsequent catalyst materials independently comprises at least one of the group consisting of palladium, silver, gold, nickel, copper, rhodium, cobalt, iridium, and platinum.

15. The method of claim 13, wherein each of the second and subsequent dielectric materials independently comprises at least one of the group consisting of an epoxy resin, a cyanate ester resin, a polyphenylene ester resin, a polyimide resin, a bismaleimide trianzine resin, a polyethylene terephthalate resin, a hydrocarbon resin, a polyfluoro carbon, a LCP resin and an inorganic resin.

16. The method of claim 13, wherein each of the second and any subsequent electroless metals comprises at least one of the group consisting of copper, nickel, palladium, platinum, and gold.

17. The method of claim 13, wherein the negative hole pattern is formed by photolithography or abrasion.

18. A method of patterning a metal in a multi layered circuit, the method comprising: placing a thin metal film on a surface of a base material; masking a first negative circuit pattern on the thin metal film using a first dielectric material; depositing a first metal onto a non-masked portion of the thin metal film; and removing both the base material and the thin metal film; wherein the first metal comprises at least one of the group consisting of the first dielectric material and a first electroless material; and wherein the thin metal film has an average thickness of less than 20 micrometer.

19. The method of claim 18, wherein the thin metal film is at least one of the group consisting of copper, silver, nickel, iron, tin, zinc, cobalt, lead, aluminum, and corresponding alloys.

20. The method of claim 18, wherein the base material comprises from metal, plastic or ceramic.

21. The method of claim 18, wherein the thin metal film is mechanically or chemically removed from the base material.

22. The method of claim 18, wherein the base material comprises the same metal as the thin metal film.

23. The method of claim 18, wherein the base material comprises a polyethylene terephthalate or a thermoplastic film.

24. The method of claim 18, further comprising: a) depositing a first catalyst layer of a first catalyst material onto the first dielectric material and the first metal; b) depositing a second dielectric material over the first layer of the catalyst material; c) masking a negative hole pattern (z-axis connection) onto the first catalyst layer using the second dielectric material; d) depositing a second electroless material onto a non-masked portion of the first catalyst layer; e) optionally repeating the method from step (a) to step (d), thereby generating a multilayer circuit.

25. The method of claim 24, wherein each of the first and any subsequent catalyst layers comprises at least one of the group consisting of palladium, silver, gold, nickel, copper, rhodium, cobalt, iridium and platinum.

26. The method of claim 18, wherein each of the first, the second and subsequent dielectric materials comprises at least one of the group consisting of a epoxy resin, a cyanate ester resin, a polyphenylene ester resin, a polyimide resin, a bismaleimide trianzine resin, a polyethylene terephthalate resin, a hydrocarbon resin, a polyfluoro carbon, a LCP resin, and an inorganic resin.

27. The method of claim 18, wherein each of the first, the second and subsequent electroless materials comprises at least one of the group consisting of copper, nickel, palladium, platinum, tin, silver, and gold.

28. The method of claim 24, wherein the negative hole pattern is formed by photolithography or abrasion.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0032] FIG. 1 illustrates a flowchart of one embodiment of a method of patterning of electroless metals.

[0033] FIG. 2 illustrates a step diagram of one embodiment of a method of patterning of electroless metals.

[0034] FIG. 3 illustrates a flowchart of another embodiment of a method of patterning of metals.

[0035] FIG. 4 illustrates a step diagram of another embodiment of a method of patterning of metals.

DETAILED DESCRIPTION

[0036] The present invention relates to methods, systems and devices for patterning metals on a substrate. One aspect of the present invention includes a method of patterning of electroless metals using electroless plating. Electroless plating uses a redox reaction to deposit metal on an object without the use of external electrical power. One of the main advantages of electroless plating is that it allows even deposition of a metal ion to all parts of the object including edges, inside of holes and irregularly shaped objects which are difficult to achieve even deposition of a metal ion by use of electrolytic plating.

[0037] FIG. 1 illustrates one preferred embodiment of method 100 of patterning an electroless metal using electroless plating. In this embodiment, the method begins with step 105 of depositing a catalyst on the substrate to form a catalyst layer such that the substrate is at least partially coated by the catalyst layer. The substrate can be a printed circuit board and any suitable types of material, rigid or flexible, can be used as a substrate. For example, a substrate can include materials of polyimide, a cloth, a plastic, a metal, a ceramic, and a resin. It is further contemplated that many precious metals can be used as catalyst for electroless plating, including for example, palladium, gold, silver, copper, rhodium, cobalt, iridium, and platinum. Also the conductive metal such as copper that will be plated over later can be used as self catalyst.

[0038] In a preferred embodiment, the catalyst includes elemental and active metal. The active catalyst approximately has a zero valence. The active catalyst is also ideally generated or otherwise disposed as atomic-level layers onto the substrate. The thickness of the catalyst will be limited by the insulation resistance between features.

[0039] The catalyst precursor may be used to achieve thin enough catalyst layer deposition. It may be applied as a solution. For example, a palladium precursor solution can be prepared to include a Lewis base ligand and a palladium compound in a solvent. For example, in a specific embodiment, the palladium precursor solution is prepared in a form of palladium propionate (e.g., palladium (II) propionate-cyclopentylamine complex, etc.). The catalytic precursor can be an organo-metal including carbonate. Additional details on preparing a palladium propionate solution are described in the U.S. Pat. No. 8,628,818, which is incorporated herein by reference.

[0040] The catalyst precursor or a catalyst precursor solution can be delivered to a substrate in any number of different manners. For example, the catalyst precursor can be deposited without a pattern onto the substrate. A deposition involves coating a large portion or the entire substrate surface with the palladium ink. The coating method can be selected from a variety of common coating methods such as bar coating, spray coating, dip coating, roll coating, ink jet printing, offset printing and most of other common methods.

[0041] It is especially preferred that the catalyst layer has an average thickness of less than 50 nanometer, more preferably less than 25 nanometer, and most preferably less than 15 nanometer. Once the catalyst layer is placed on the substrate, the method continues with step 110 of placing a layer of patterned dielectric material on the catalyst layer. The dielectric material includes at least one of the group consisting of an epoxy resin, a cyanate ester resin, a polyphenylene ester resin, a polyimide resin, a bismaleimide trianzine resin, a polyethylene terephthalate resin, a hydrocarbon resin, a polyfluoro carbon, a LCP resin, and an inorganic resin.

[0042] In a preferred embodiment, the dielectric material is plated on a negative pattern of the final conductive circuitry pattern that is substantially opposite to what the final conductive circuitry pattern will be on the substrate. In some embodiments, the negative pattern is at least partially two-dimensional (X-axis and Y-axis). However, it is contemplated that the negative pattern be three dimensional (X-, Y- and Z-axis), linear (e.g., one-dimensional), or include a combination.

[0043] The negative pattern of the dielectric can be created by various printing and/or photolithography techniques. For example, conventional screen or stencil printing, and inkjet printing allows selective dielectric material deposition. Preferably, photosensitive dielectric material with ink, paste and film format used with UV or other wavelength exposure unit that allows higher density design and/or shorter process time than selective printing methods.

[0044] The other negative pattern of dielectric can be created by abrasion, laser ablasion or milling.

[0045] After the dielectric material is placed on the catalyst layer, the method continues with step 115 of placing a layer of electroless metal on the layer of patterned dielectric. Although electroless material is applied onto a catalytic layer, it cannot be deposited on the portions coated with dielectric material in the substrate, but deposited on the portions where catalytic layer is exposed. The electroless metal deposition can be used commercially available chemicals and processes, because the catalyst works well with these.

[0046] Optionally, the formed circuitry can be added another layer applying a conventional via hole formation technique. For instance, a dielectric material is deposited over the circuitry prepared substrate described in step 110. Via holes for Z-axis connections are formed in step 120 by abrasion technique with laser or mechanical drill, or by use of a photolithography technique to appropriately position the deposited dielectric material in a photolithographic image. After via hole formation, electroless metal is optionally deposited in step 125. For example, the first circuitry is made by copper, then the conventional electroless copper can be deposited over the exposed copper at via hole bottom using copper as the self-catalyst. When the via hole copper grows enough, same process cycle of optional step 130 can be used to add another circuitry. Further multilayer structure can be formed applying the same process cycle repeatedly via optional step 135. Contemplated electroless metal includes copper, nickel, palladium, platinum, tin, silver, and gold.

[0047] FIG. 2 illustrates a schematic diagram as cross-sectional drawing corresponding to FIG. 1 process. The first step 200 is the catalyst layer 202 preparation over the base material 201. The base material can be metal, plastic, or ceramic and also including polymers such as polyethylene terephthalate and thermoplastic film. On the prepared base material 211, a dielectric material 212 is placed over the catalyst layer with a negatively circuitry image at the step 210. Electroless metal 223 is deposited over the exposed portions of catalytic base material 221 in step 220. Because the dielectric material 222 is not active to the plating chemistry, then there is no metal deposition over the dielectric material at the step 220.

[0048] An optional step 230 makes via hole to connect two circuitry layers. As shown in step 230, dielectric material 233 is plated over the base circuitry 231 and either layered or filled metal is deposited onto a inner surface of a via hole 234, connecting to a part of base circuitry 232. The next optional step 240 is for another circuitry formation over the base 241 applying same sequence of the process from 200 to 220. The steps 230 to 240 may be repeatedly processed as necessary, and consequently the multilayer circuitry is developed.

[0049] Alternatively, instead of using the catalyst for the preliminary preparation of electroless metal deposition, a thin metal film can be applied. Appropriate thin metal films include copper, silver, nickel, iron, tin, zinc, cobalt, lead, or aluminum, but more preferably copper. A combination of these metals or an alloy can be used as well. The thin metal film can be the same as the base material. The thin metal film can be selected from workable electroless metal solution with it. The thin metal film may be settled over removable material to get enough rigidity for the process. Also thin metal film may include a sacrificial layer. Such foil is commercially available and it helps the base material removal process when it is no longer necessary. In thin metal film use for the metal deposition seed layer, it allows both electroless and electrolytic metal deposition.

[0050] FIG. 3 illustrates another preferred embodiment of method 300 of patterning of metals using plating technique. In this embodiment, the thin metal film can be settled over a base material to get enough rigidity for the further processes (step 305). Subsequently, the dielectric material is deposited over a thin metal film on a negative pattern of the final conductive circuitry pattern (step 310). Finally, the metal layer is applied to the thin metal film layer which is not covered by the dielectric material (step 310). The metal deposition can be used either electroless or electrolytic plating.

[0051] Optionally, dielectric material with via hole openings is placed over the base circuitry in step 315. Then metal is deposited onto via hole opening in step 320. Another circuitry layer is prepared by repeating processes 305 to 310 and followed by the processes of 315 to 320, generating a multilayer circuitry design in step 330.

[0052] Lastly, the base material is removed from thin metal film and the thin metal film is removed. Then the thin metal is removed and a chemical process such as etching or physical process peeling can be used for the removal process 335.

[0053] FIG. 4 illustrates a schematic diagram as cross-sectional drawing corresponding to FIG. 3. The first step 400 (optional) is the thin metal layer 402 preparation over the base material 401. On the top of the base material 410, a dielectric material 412 is placed over the thin metal film layer with negative circuitry image at the step 410. Metal 423 is deposited over the exposed thin metal layer, not covered by dielectric material, over the base material 421 in step 420.

[0054] An optional step 430 makes via hole to connect two circuitry layers. As shown in step 430, dielectric material 433 is plated over the base circuitry 431 and either layered or filled metal is deposited onto a inner layer of a via hole 434, connecting to a part of base circuitry 432. The next process 440 is for another circuitry formation over the base 441 applying same sequence of the process from 410 to 420. The steps 430 to 440 may be repeatedly processed as necessary, and consequently the multilayer circuitry is developed. Optional step 450 depicts the removal of base material 401 and thin metal layer 402 (collectively 411) forming circuitry 452.

[0055] The discussion herein provides example embodiments of the inventive subject matter. Although each embodiment represents a single combination of inventive elements, the inventive subject matter is considered to include all possible combinations of the disclosed elements. Thus if one embodiment comprises elements A, B, and C, and an intermediate embodiment comprises elements B and D, then the inventive subject matter is also considered to include other remaining combinations of A, B, C, or D, even if not explicitly disclosed

[0056] As used herein, and unless the context dictates otherwise, the term coupled to is intended to include both direct coupling (in which two elements that are coupled to each other contact each other) and indirect coupling (in which at least one additional element is located between the two elements). Therefore, the terms coupled to and coupled with are used synonymously.

[0057] Unless the context dictates the contrary, all ranges set forth herein should be interpreted as being inclusive of their endpoints, and open-ended ranges should be interpreted to include commercially practical values. Similarly, all lists of values should be considered as inclusive of intermediate values unless the context indicates the contrary.

[0058] It should be apparent to those skilled in the art that many more modifications besides those already described are possible without departing from the inventive concepts herein. The inventive subject matter, therefore, is not to be restricted except in the scope of the appended claims. Moreover, in interpreting both the specification and the claims, all terms should be interpreted in the broadest possible manner consistent with the context. In particular, the terms comprises and comprising should be interpreted as referring to elements, components, or steps in a non-exclusive manner, indicating that the referenced elements, components, or steps may be present, or utilized, or combined with other elements, components, or steps that are not expressly referenced. Where the specification claims refers to at least one of something selected from the group consisting of A, B, C . . . and N, the text should be interpreted as requiring only one element from the group, not A plus N, or B plus N, etc.