OPTICAL RECEIVER COMPRISING MONOLITHICALLY INTEGRATED PHOTODIODE AND TRANSIMPEDANCE AMPLIFIER

Abstract

An optical receiver comprises a monolithically integrated pin photodiode (PIN) and transimpedance amplifier (TIA). The TIA comprises InP heterojunction bipolar transistors (HBT) fabricated from a first plurality of layers of an epitaxial layer stack grown on a SI:InP substrate; the PIN is fabricated from a second plurality of layers of the epitaxial layer stack. The p-contact of the PIN is directly connected to the input of the TIA to reduce PIN capacitance CPIN. The TIA capacitance CTIA may be matched to CPIN. Device parameters comprising: a thickness of the absorption layer, window area, and an optional mirror thickness of the PIN; device capacitance CPIN+CTIA; and feedback resistance RF of the TIA; are optimized to performance specifications comprising a specified sensitivity and responsivity at an operational wavelength. This design approach enables cost-effective fabrication an integrated PIN-TIA, for applications such as a 1577 nm receiver for an ONU for 10G-PON.

Claims

1. An optical receiver comprising a monolithically integrated photodiode (PD) and transimpedance amplifier (TIA), wherein: an epitaxial layer stack is formed on a semi-insulating indium phosphide (SI:InP) substrate; the TIA comprises InP heterojunction bipolar transistors (HBT) formed by a first plurality of semiconductor layers of the epitaxial layer stack formed on a SI:InP substrate; the PD comprises a p-i-n diode (PIN) formed by a second plurality of semiconductor layers of the epitaxial layer stack, comprising an n-layer, an i-layer and a p-layer, the second plurality of semiconductor layers being formed on top of the first plurality of semiconductor layers of the epitaxial layer stack; a p-contact of the PIN diode is directly interconnected by a conductive trace to an input of the TIA, to provide a device capacitance C.sub.PIN of the PIN, and a capacitance C.sub.TIA of the TIA; and device parameters comprising values of: C.sub.PIN; C.sub.TIA; a thickness t.sub.i of the i-layer; an optical window diameter (Φ) or area A of the PIN; and a transimpedance feedback resistance R.sub.F of the TIA; are selected to provide an integrated PIN-TIA meeting performance specifications comprising a specified sensitivity and responsivity at an operational wavelength.

2. The optical receiver of claim 1 wherein the i-layer comprises InGaAs.

3. The optical receiver of claim 1, wherein the i-layer is selected from materials of the group comprising InGaAs and other absorption materials within the InGaAlAsP penternary system.

4. The optical receiver of claim 1, comprising a mirror (optical reflector) underlying the i-layer, to create a dual-pass through the i-layer.

5. The optical receiver of claim 4, wherein the mirror comprises a multi-layer quarter-wave stack of alternating high index and low index lattice matched materials.

6. The optical receiver of claim 4, wherein said device parameters comprise a mirror thickness t.sub.m of the multi-layer quarter wave stack, and wherein the thickness t.sub.i of the i-layer and the mirror thickness t.sub.m are selected to obtain a required Quantum Efficiency.

7. The optical receiver of claim 1, wherein values of C.sub.PIN and C.sub.TIA provide at least one of: a) C.sub.PIN is matched to C.sub.TIA; b) C.sub.PIN is approximately equal to C.sub.TIA; and c) a minimum combined capacitance (C.sub.PIN+C.sub.TIA).

8. The optical receiver of claim 1, wherein C.sub.PIN is ≤50 fF.

9. The optical receiver of claim 1, wherein C.sub.PIN is ≤30 fF.

10. The optical receiver of claim 1, wherein C.sub.PIN is ≤15 fF.

11. The optical receiver of claim 1, wherein the specified sensitivity and responsivity meet performance specifications for a receiver of an Optical Network Unit (ONU) for 10G PON.

12. The optical receiver of claim 11, wherein said device parameters are optimized for an operational wavelength of 1577 nm.

13. The optical receiver of claim 1, wherein the specified sensitivity and responsivity meet performance specifications for a receiver of an Optical Line Terminal (OLT) of a 10GPON.

14. The optical receiver of claim 13, wherein said device parameters are optimized for operation at 1270 nm.

15. The optical receiver of claim 1, wherein the specified sensitivity is equal to or better than −28 dBm.

16. The optical receiver of claim 1, wherein the specified sensitivity is equal to or better than −30 dBm.

17. The optical receiver of claim 1, wherein the specified responsivity is ≥0.6 A/W.

18. The optical receiver of claim 1, wherein the specified responsivity is ≥0.8 A/W.

19. The optical receiver of claim 1, wherein the specified responsivity is ≥1.0 A/W.

20. The optical receiver of claim 1, having a Quantum Efficiency ≥85% or more preferably ≥90%.

21. The optical receiver of claim 1, wherein the HBT are characterized by f.sub.r≥100 GHz, the TIA has a bandwidth (BW) of ≥7.5 GHz, C.sub.PIN is ≤50 fF, C.sub.TIA is ≤50 fF and R.sub.F≥1500Ω.

22. The optical receiver of claim 21, wherein C.sub.PIN is ≤30 fF, and C.sub.TIA is ≤30 fF.

23. The optical receiver of claim 21, wherein C.sub.PIN is <15 fF, and C.sub.TIA is <15 fF.

24. The optical receiver of claim 1, wherein: the p-layer comprises a single layer or a multilayer structure; and/or the i-layer (absorption layer) comprises a single layer or a multilayer structure; and/or the n-layer comprises a single layer or a multilayer structure.

25. The optical receiver of claim 1, comprising at least one of: a) the optical window (aperture) of the PIN comprises an anti-reflection coating optimized for the operational wavelength; b) a p+ cap layer of the PIN is selected to be substantially transparent at the operational wavelength; and c) the p+ cap layer is a material selected to have a thickness and optical properties that reduce or minimize optical losses rather than reducing or minimizing sheet resistance and contact resistance for the p-contact.

26. An optical receiver for an OLT (Optical Line Terminal) or ONU (Optical Network Unit) of a 10G Passive Optical Network (PON) comprising: a monolithically integrated photodiode (PD) and a transimpedance amplifier (TIA), wherein: the TIA comprises InP (indium phosphide) heterojunction bipolar transistors (HBT) formed by a first plurality of layers of an epitaxial layer stack grown on a SI (semi-insulating) InP substrate; the PD comprises a pin diode (PIN) formed by a second plurality of semiconductor layers of the epitaxial layer stack comprising an n-layer, an i-layer and a p-layer; a p-contact of the PIN diode is directly interconnected by a conductive trace to an input of the TIA; and the i-layer comprises absorption material selected for an operational wavelength of the OLT or the ONU.

27. The optical receiver of claim 26, for an ONU, wherein the i-layer comprises a single layer or a multi-layer structure comprising material that absorbs at 1577 nm.

28. The optical receiver of claim 26, for an OLT wherein the i-layer comprises a single layer or a multi-layer structure comprising material that absorbs at 1270 nm.

29. The optical receiver of claim 26, wherein the i-layer is selected from the group comprising InGaAs and other absorption materials of the InGaAlAsP materials system, which are lattice matched to InP.

30. The optoelectronic receiver of claim 26, comprising a mirror (optical reflector) underlying the i-layer, to create a dual-pass through the i-layer.

31-48. (canceled)

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0036] FIG. 1 (Prior Art) shows a schematic functional block diagram of an optical receiver comprising a hybrid photodiode detector PD and a TIA;

[0037] FIG. 2 shows two views of an example of a commercially available InGaAs pin PD;

[0038] FIG. 3 shows an example plot of device capacitance vs. device area for pin PDs of different device areas;

[0039] FIG. 4 shows a schematic cross-sectional view through layers of an example InGaAs pin PD to show design parameters comprising window diameter Φ and i-layer thickness t.sub.i;

[0040] FIG. 5A shows a schematic topology view (top plan view) of a monolithically integrated PIN-TIA of an example embodiment;

[0041] FIG. 5B shows a schematic cross-sectional view of an epitaxial layer structure for fabrication of the monolithically integrated PIN and a TIA of the example embodiment;

[0042] FIG. 6A shows a simplified equivalent circuit schematic for the PIN of a monolithically integrated PIN-TIA and FIG. 6B is a table listing some parameters;

[0043] FIG. 7A shows a schematic plot to illustrate dependence of sensitivity on PIN device capacitance C.sub.PIN and TIA capacitance C.sub.TIA;

[0044] FIG. 7B shows a schematic plot to illustrate dependence of PIN device capacitance C.sub.PIN and responsivity (A/W) and on the i-layer thickness t.sub.i;

[0045] FIG. 8 lists some equations showing relationships between the device parameters;

[0046] FIG. 9 shows a schematic plot to illustrate dependence of Quantum Efficiency on the i-layer thickness t.sub.i;

[0047] FIG. 10 shows a plot of computed data, based on a simplified model, for the −3 dB bandwidth f_−3 dB(GHz) as a function of the i-layer thickness t.sub.i. (μm) (labelled in the graph as t_InGaAs (um)) for hybrid PD-TIA (discrete) and integrated PIN-TIA (integrated) having three different aperture diameters;

[0048] FIG. 11 shows a schematic plot to illustrate dependence of noise on the feedback resistance R.sub.F of the TIA;

[0049] FIG. 12 shows a schematic plot to illustrate dependence of noise on the combined device capacitance of the PIN and capacitance of the TIA (C.sub.PIN+C.sub.TIA);

[0050] FIG. 13 shows a simplified equivalent circuit schematic for the PIN and TIA to illustrate key parameters for design of the monolithically integrated PIN-TIA design of the example embodiment;

[0051] FIG. 14 is a table with example device specifications for the monolithically integrated PIN-TIA of the example embodiment;

[0052] FIG. 15 shows a circuit design schematic for the monolithically integrated PIN-TIA of the example embodiment;

[0053] FIG. 16 shows a simplified equivalent circuit diagram the monolithically integrated PIN-TIA of the example embodiment showing device parameters of the PIN and of the first transistor Q1 of the TIA;

[0054] FIG. 17 shows a simplified schematic cross-sectional view of an integrated PIN-TIA of a first embodiment to illustrate direct interconnection of the PIN and TIA;

[0055] FIG. 18 shows a simplified schematic cross-sectional view of an integrated PIN-TIA of a second embodiment, comprising a multi-layer reflector (mirror);

[0056] FIG. 19 shows a plot of simulated data to illustrate the effect of including a reflector as illustrated schematically in FIG. 18;

[0057] FIG. 20 shows a Moore's law plot of transistor gate length (nm) over the last 50 years; and

[0058] FIG. 21 shows a plot of absorption coefficient vs. wavelength for example semiconductor materials.

DETAILED DESCRIPTION

[0059] A schematic functional block diagram of an optical receiver comprising a hybrid assembly 10 of a package substrate 12, a photodiode chip 20 comprising a photodiode (PD) 22 and a TIA chip 30 comprising a TIA 32 with feedback resistor R.sub.F, and a discrete post amplifier 36, is shown in FIG. 1. The photodiode chip 20 is interconnected to the TIA chip 30 with wirebonded interconnect 38, to feed photocurrent I.sub.PD to the TIA 322 to generate output voltage V.sub.out. The photodiode PD may be an APD, or a pin PD (PIN), or other type of photodiode, depending on the required performance specifications. Typically, for GPON and 10GPON, to provide the required sensitivity, e.g. better than −28.5 dBm, the photodiode is an APD. As mentioned in the background section, it would be desirable to replace a hybrid APD-TIA with a lower cost monolithically integrated PIN-TIA with comparable performance and sensitivity.

[0060] Conventional wire bonded interconnections of a hybrid PIN-TIA optical receiver add significant parasitics, which limit performance of a PIN-TIA. In particular, the bond pads add capacitance and bond-wires add inductance. It will also be appreciated that the consistency of wire-bonded interconnections of hybrid components tend to be dependent on the type of packaging used, and in practice, some variability or inconsistencies in wire-bonded interconnections for individual optical receiver units may be expected. These variabilities or inconsistencies in wire-bonding lead to corresponding variabilities or inconsistencies in parasitic capacitances and inductances of hybrid PIN-TIA.

[0061] Monolithically integrated PIN-TIA of embodiments of the present invention are disclosed, which offer an alternative to conventional hybrid APD-TIA for 10G-PON, with at least comparable performance, and potentially offer performance improvements and/or cost reductions relative to other hybrid PD-TIA.

[0062] An example top view A and side view B of a photodiode chip 20 comprising a 56 Gb/s InGaAs PIN 22 (GCS DO480_16 um_C3), which is suitable for a high speed optical receiver operating at 1577 nm, is shown in FIG. 2. The device has an optical window 24 of 16 μm diameter, and is reported to have a 36-40 GHz 3 dB bandwidth when operated with an optimized TIA. In a conventional hybrid arrangement of a PIN and a TIA, e.g. as shown in FIG. 1, two bond pads, i.e. an n-pad 26 and a p-pad 28, e.g. 75 μm 50Ω pads, are required to connect the PD to the TIA with wire bonds. Both pads of the PD add capacitance, which can be a significant fraction of the total capacitance of the device. The product datasheet reports a device capacitance in a range of 65 nF to 80 nF.

[0063] Taking some example InGaAs PIN devices of different areas, which have publicly available datasheets, and working backwards from information on the datasheets, it is estimated that the parasitic capacitance of the bond pads contributes roughly half of the total device capacitance. This estimate is derived, as illustrated schematically in the plot of capacitance C (pF) vs. device area (μm.sup.2) in FIG. 3, by extrapolation to zero device area based on typical capacitance and maximum capacitance data for devices of different device areas.

[0064] FIG. 4 shows a schematic cross-sectional view of an InGaAs PIN device structure 100 showing the p-i-n layer structure 110 comprising an n-layer 112, an i-layer 114 and a p-layer 116 formed on a semi-insulating (SI) indium phosphide (InP) substrate 102. The i-layer has a thickness t.sub.i. An annular p-contact 122 is formed on the p-layer with an optical aperture or window 124 having a diameter Φ. Bond pads comprise a p-contact pad 126 and a n-contact pad 128. The annular p-contact 122 extends to the p-contact pad 128. The n-layer 112 is formed on an n-contact layer 127, which is interconnected, e.g. by a conductive via through the dielectric layer 104, to the n-contact pad 126. The capacitance C.sub.PIN of the p-i-n junction itself is necessary for device operation. For a given device aperture window diameter Φ, if the junction capacitance were zero, the transit time would be infinite, and the bandwidth would be zero. A finite junction capacitance is necessary to balance off RC with carrier transit time. However, the bond pad capacitance adds no useful functionality, and ideally the bond pad capacitance would be zero.

[0065] Monolithic integration of the PIN and TIA eliminates the bond pad capacitance, and bond wire inductance, by design. For example, it is possible to integrate a InGaAs PIN with a TIA fabricated using InP heterojunction bipolar transistors (HBTs). This means there is a direct on-chip interconnection, i.e. a lithographically defined conductive trace, from the output of the PIN to the input of the TIA. Preferably the conductive trace between the PIN and TIA provides a short, low resistance, low inductance interconnection, eliminating the need for impedance matching. Thus, one of the 50Ω bond pads of the PIN is eliminated because there is a direct interconnection, instead of not a wire bond connection between the PIN and TIA. Since the conductive trace providing the direct interconnection between the PIN and TIA is lithographically defined, i.e. using one or more interconnect metallization layers, the PIN-TIA interconnection is more reproducibly and consistently defined, for each PIN-TIA on a wafer, and from wafer-to-wafer, and from batch-to-batch.

[0066] A schematic device topology (top plan view) for a monolithically integrated PIN-TIA of an example embodiment 200 is shown in FIG. 5A. The monolithically integrated PIN-TIA chip 210 comprises a PIN device structure 220 and TIA circuitry 230. There is a direct on-chip interconnection 240 between the p-contact of the PIN 220 and the TIA circuitry. A schematic cross-sectional view of the monolithically integrated PIN-TIA chip 210 comprising a substrate 202 is shown in FIG. 5B, to illustrate monolithic integration of HBT epitaxial layers 204 for the TIA and overlying epitaxial layers 206 to form the PIN is shown in FIG. 5B. Although the opposite terminal of the PIN is coupled to a bond pad (i.e. a ground pad), the capacitance of this pad is actually decoupled from device operation. Since the output of the PIN is directly coupled to a first stage amplifier of the TIA by a conductive trace providing a direct on-chip interconnection, in effect, the pad capacitance of the PIN does not figure into device operation. This has multiple useful consequences.

[0067] It is estimated that eliminating these parasitic capacitances would extend the RC-limited bandwidth by roughly a factor of 2. Monolithic integration of the PIN and TIA eliminates the bond pad of the PIN terminal connected to the TIA, which removes one of two bond pads, i.e. reduces the bond pad capacitance by half. Referring to the equivalent circuit diagram shown in FIG. 6A, the PIN is modelled as a device current source I.sub.PD and device capacitance C.sub.PIN, with pad capacitance C.sub.PAD in series with a wirebond inductance L.sub.Bondwire. The effect of this circuit is LC limited. For a 25 GHz LC limit (f=½π(LC).sup.1/2), this limit is roughly 2 nH (see table in FIG. 6B). The inductance of a typical gold wirebond, 1 mm in length is roughly 0.8 nH at 10 GHz or 25 GHz (i.e. 0.8 nH/mm). So, for all practical purposes, this LC limit is well beyond any important circuit considerations for this application, or up to 25 GHz. At 50 GHz, the inductance would need to be managed, e.g. by using multiple wirebonds, low inductance conductive interconnect tracks, or other techniques designed to reduce inductance. By elimination of the wirebond connection between the PIN to the TIA, the bond pad inductance for the remaining bond pad is half the inductance of a hybrid arrangement with two bond pads. Monolithic integration of the PIN-TIA reduces both parasitic device capacitance and inductance.

[0068] For example, more generally, assuming the capacitance of a single bond pad is approximately 15 fF, the inductance peak for 25 GHz is at 2.7 GHz, provided the bond wire is shorter than 3 mm or so, the resonance would be at a higher bandwidth than 25 GHz, and inconsequential for 10 GHz.

[0069] The frequency response of a pin PD is limited primarily by RC and transit time in parallel, i.e. the sum of squares of the associated response times. If the PIN capacitance C.sub.PIN is halved, this gives a higher bandwidth, or, for the original bandwidth, additional degrees of freedom to increase the thickness t.sub.i of the i-layer of the pin PD are available. Although a thicker i-layer increases the carrier transit time, which typically would not be desirable, a lower device capacitance C.sub.PIN allows a trade-off, because a thicker i-layer increases the responsivity, which is beneficial. This trade-off permits, for a given bandwidth, a higher responsivity for a circular geometry (i.e. normal incidence) PIN than would otherwise be the case.

[0070] Some schematic graphical representations of the interdependence of device parameters are shown in FIGS. 7A, 7B and FIGS. 9 to 12. The PIN-TIA sensitivity can be improved by reducing the capacitance of the PIN and reducing the capacitance of the TIA, as shown schematically in the plots of FIG. 7A. For example, referring to the equations shown in FIG. 8, as illustrated schematically in the plot shown in FIG. 7B, the capacitance of the PIN decreases with the thickness of t.sub.i, and the responsivity, in A/W, increases with thickness t.sub.i, The quantum efficiency of the PIN also increases with an exponential dependence on (1−γt.sub.i), as shown schematically in FIG. 9.

[0071] To provide improved performance, first, the effective device capacitance (C.sub.PIN+C.sub.TIA) is lowered by monolithic integration, i.e. by removing a bond pad and providing a direct interconnect between the PIN and TIA; and second, the device thickness t.sub.i is increased. The overall f_3 dB envelope of the PIN vs. device thickness is improved, as illustrated by the data shown in FIG. 10. These combined effects provide improved bandwidth for a PIN of a given diameter.

[0072] The 3 dB bandwidth (f_3 dB) is given by the sum of squares of the transit time limited response and the RC response. The plot shown in FIG. 10 is for generic pin PD structures, with certain assumptions about bond pad capacitance (approximately 30 fF), annular contact area (3 μm was used for this calculation), literature values for hole and electron velocity (which are approximate, perhaps within ±20%), and using the approximation that all holes and electrons originate from the average absorption location within a circular, i.e. normal incidence, pin photodiode. The diameters referenced in the plot refer to open optical aperture for coupling to an optical fiber, with some additional surrounding area for the annular metal contact. For the data shown in FIG. 10, f_3 dB has been calculated some examples of monolithically integrated PIN-TIA (labelled “integrated”) and hybrid PIN-TIA (labelled “discrete”), for pin PD having diameters of 20 μm, 16 μm and 12 μm diameter, using publicly available data, to extrapolate the bond pad capacitance.

[0073] Simplified Model for Transit Limit Derivation

[0074] In a simplified model for transit limit derivation the average absorption position was calculated for each InGaAs thickness t.sub.i and both carriers are assumed to be originating from this position.

[0075] The transit time limited bandwidth f.sub.tr is given by:

f.sub.tr*t.sub.i=0.443  (1)

where t.sub.i is the transit time of the intrinsic depletion layer of the InGaAs and a rectangular pulse single transit time approximation is assumed, leading to sinc(x) Fourier transform distribution. Let the transit direction be z, and let the thickness of the InGaAs be z.sub.i and the velocity assumed constant at v.sub.i. Simple rearrangement of equation (1) gives:

[00001]$\begin{array}{cc}{z}_i=\frac{0.443*v_i}{f_{tr}}& \left(2\right)\end{array}$

Equation (2) also gives the transit time limited thickness for a given frequency. Lecture notes and textbooks usually assume the sum of squares of electron and hole transit times, but also do extensive numerical work. In this work, it is elected to assume all carriers originate from the average absorption location to calculate the transit time, and the two transit times are averaged, so as to arrive at an algebraically understandable result which is a close approximation. Also, the absorption profile is given by Beer's Law as exp (−γz), where γ is the absorption coefficient. For light entering a normal-incidence geometry PD through the p-region, the average absorption location for electrons (which traverse to the p-contact) is given by:

[00002]$\begin{array}{cc}{z}_{e,\mathrm{avg}}=\frac{{\int }_0^{z\_i}{e}^{-\gamma z}\mathrm{dz}}{z_i}& \left(3\right)\end{array}$

which works out to:

[00003]$\begin{array}{cc}{z}_{e,\mathrm{avg}}=\frac{1-e^{-\gamma z_i}}{\gamma z_i}& \left(4\right)\end{array}$

and, therefore the average absorption for holes is given by

z.sub.h,avg=z.sub.i−z.sub.e,avg  (5)

[0076] Often these quantities are calculated numerically. These closed-form, approximate expressions are useful for simplified calculations.

[0077] Based on these assumptions, this simplified model provides for comparison of the f_−3 dB bandwidth of some examples of monolithically integrated PIN-TIA and hybrid PIN-TIA. While a more sophisticated modelling approach could be taken, the basic physics would remain the same.

[0078] Referring to the data in FIG. 10, the following observations are made: [0079] For the integrated set and for the discrete set, decreasing the diameter improves the frequency response at all values of t_InGaAs; [0080] For any given diameter, going from discrete (with bond pad capacitance) to integrated (no bond pad capacitance) improves the frequency response at all values of t_InGaAs; [0081] There is an optimum (i.e. peak) bandwidth for any given pin PD diameter, whether for integrated or discrete; [0082] This optimum (peak) is sharper for integrated because higher bandwidths are possible, limited only by the device size; [0083] For sufficiently thick t_InGaAs (t.sub.i), the value of decreasing the diameter is diminishing; but for greater thicknesses, there is still a clear, yet small, advantage in bandwidth in the integrated approach.

[0084] Considering these data, for example, if more bandwidth were needed, the device thickness could be reduced, giving back the capacitance to obtain improved transit time. Or, if more responsivity were needed, the device thickness could be increased, worsening the transit time frequency response, with some room to give, because of the decreased capacitance. If the i-InGaAs layer is thinned for optimum bandwidth, the responsivity would decrease. To achieve both increased bandwidth and increased responsivity (QE) together, a mirror or reflector can be added to the PD, to allow for two-passes of absorbed light, i.e. to increase the effective thickness of the InGaAs i-layer, as will be described below.

[0085] Next, the input referred noise (IRN) and the receiver sensitivity achievable is improved by monolithic integration of the PIN and TIA, because the first stage amplifier (TIA) can accommodate a higher transimpedance feedback resistance R.sub.F. That is, the TIA noise is inversely dependent on R.sub.F, as shown schematically in FIG. 11. Conversely, noise increases with the combined capacitance of the PIN and TIA, i.e. C.sub.PIN+C.sub.TIA, as shown schematically in FIG. 12, e.g. because higher device capacitance limits the feedback resistance R.sub.F.

[0086] FIG. 13 shows a simplified equivalent circuit schematic for the PIN and TIA to illustrate key parameters for a monolithically integrated PIN-TIA design, e.g. for an example device specification shown in the table in FIG. 14.

[0087] Putting together these two effects, i.e. reducing the PIN device capacitance, and increasing the value of the transimpedance feedback resistor R.sub.F, which reduces TIA noise, results in improved sensitivity. Thus, it becomes possible to design a PIN-TIA having improved sensitivity, e.g. better than −28 dBm at 1577 nm, to meet the requirements for an optical receiver for 10G-PON.

[0088] FIG. 15 is a circuit design schematic for an example embodiment of a monolithically integrated PIN-TIA, wherein the TIA comprises a three-stage amplifier with first, second and third HBTs, Q1, Q2 and Q3, and transimpedance feedback resistor R.sub.F. In the simplified equivalent circuit shown FIG. 16, the PIN is shown as a circuit equivalent current source I.sub.AC with capacitance C.sub.PIN. The first transistor Q1 of the TIA is modelled as a capacitance C.sub.TIA, input resistance r.sub.π, current source 62 i.sub.π, based on current received from the PIN being i.sub.π. Also shown are base, emitter and collector resistances r.sub.b, r.sub.e, and r.sub.c, and feedback resistor r.sub.F. The second and third stages of the TIA are represented schematically by amplifier 1.

[0089] An optimum noise reduction for a TIA first stage occurs when both the capacitance of the PD, C.sub.PIN, and the capacitance of the first stage HBT Q1 can be minimized, and are comparable to each other. In principle, the capacitance of the HBT can be reduced by design, i.e. a mask set adjustment to provide a smaller gate length HBT. But, in practice, the combined device capacitance C.sub.PIN+C.sub.TIA may be limited by how much C.sub.PIN can be reduced. Unless the PD capacitance can be comparably reduced, there may be limited benefit to reducing the capacitance of the HBT; and the cost and effort of design kit variations for a smaller gate length HBT may not make it worth attempting. In a hybrid PD-TIA, since the bond pad parasitics dominate, there may be limited benefit to reducing the device area of the PD to reduce C.sub.PIN, because of the associated increased difficulty in optical fiber alignment to a PD with a smaller aperture. On the other hand, since the PIN device capacitance C.sub.PIN can be reduced significantly by monolithic integration of the PIN-TIA, by selecting a PIN with a smaller aperture, if packaging logistical issues with fiber alignment to a smaller aperture PIN are overcome, then the size of the first stage HBT can be comparably reduced, to reduce capacitance of the first stage HBT. This arrangement would lead to further improvements in noise, and therefore in receiver sensitivity.

[0090] Considering these design principles, in a monolithically integrated PIN-TIA of an example embodiment, the PIN capacitance C.sub.PIN is 50 fF, and the PIN is operated with a reverse bias voltage of 3.3V. The TIA is designed to match the capacitance of the TIA, C.sub.TIA, to the PIN capacitance, i.e. C.sub.TIA is also 50 fF. The TIA comprises a three-stage transistor amplifier with a transimpedance feedback resistance R.sub.F of 1500Ω, calculated using the equation shown in FIG. 13, assuming the f.sub.T of InP HBT transistors is 100 GHz, and a bandwidth BW=7.5 GHz.

[0091] Design of the integrated PIN-TIA for improved sensitivity (i.e. a lower value, e.g. less than −28 dBm) and to achieve a specified responsivity, e.g. ≥0.7 A/W, requires recovering all photons possible, i.e. improving the quantum efficiency (QE) of the PIN. For a discrete PIN which is wire bonded to the TIA, this is not practical, because even if the thickness t.sub.i were increased towards infinity, i.e. to the point where transit time bandwidth dominates, the bond pad capacitance is a dominant factor in limiting the sensitivity. On the other hand, for a monolithically integrated PIN and TIA, where the sensitivity depends primarily on the PIN capacitance C.sub.PIN, and not on the bond pad capacitance of the PIN, then multiple design options become possible to increase the QE of the PIN, e.g.:

a) increase the device thickness t.sub.i until transit time dominates, because pad capacitance is not dominating;
b) decrease device area A (e.g. aperture diameter Φ) because pad capacitance is not dominating;
c) for a given wavelength, insert a mirror, e.g. a reflector comprising quarter-wave stacks of alternating high/low index material to create a dual pass through the thickness t.sub.i of the i-InGaAs layer, to preserve low transit time while increasing the QE;

[0092] A schematic cross-sectional view through layers of an integrated PIN-TIA of a first embodiment 300 is shown in FIG. 17. The device structure comprises a substrate 302, e.g. SI:InP, on which is formed an epitaxial layer stack for the TIA circuitry and for the PIN device structure. A first plurality of semiconductor layers of an epitaxial layer stack provides an HBT epilayer structure 304 for the TIA circuitry 330. A second plurality of layers of the epitaxial layer stack form a PIN epilayer structure 306 for the PIN 320, comprising the n contact layer 327, n-layer 312, i-layer 314, p-layer 316, annular p-contact 322 having window 324 of diameter Φ. The p-contact 320 of the PIN 320 is interconnected to the TIA circuitry by PIN-TIA interconnect 340, which extends through dielectric fill 308. The TIA circuitry 330 is formed on a first area of the substrate which is isolated by an isolation trench 350 from a second area of the substrate on which the PIN 320 is formed. For example, a monolithically integrated InGaAs PIN and TIA comprising InP HBTs may be fabricated using commercially available InP process technology.

[0093] For 10G PON, the i-layer of the PIN comprises InGaAs, to provide for absorption at the transmission wavelength of the OLT, i.e. 1577 nm. The n-layers and p-layers of the PIN may be any suitable lattice matched material compatible with InGaAs. To reduce unwanted absorption, the aperture is preferably a material that is substantially transparent at the transmission wavelength, and may include an anti-reflection coating.

[0094] Fabrication comprises providing an epitaxial layer structure in which an HBT epi-layer structure is provided on the substrate, with an overlying PIN epi-layer structure. That is the TIA circuitry comprising InP HBTs is fabricated on the SI InP substrate, for high speed operation of the HBT. The InGaAs PIN is formed by overlying epitaxial layers, so that conductivity of the layers of the PIN epi-layer structure does not degrade speed and performance of the underlying TIA circuitry. Also, since the HBT epi-layers of the epitaxial layer stack forming the HBT electronics are distinct from the PIN epi-layers of the epitaxial layer stack forming the PIN, each can be optimized separately. If required a spacer comprising one or more intermediate layers between the HBT epi-layers and the PIN epi-layers may be provided, e.g. to provide electrical isolation, to act as an etch stop to facilitate processing, etc. As illustrated schematically, the area of the TIA circuitry may be isolated from the area of the PIN by a dielectric filled trench. By integration of the HBT electronic circuitry for the TIA and the PIN detector as illustrated schematically, layers of the HBT epi-layer stack and layers of the PIN epi-layer stack may be independently structured and optimized for improved device performance. If required, materials of the epitaxial layer structure may be selected to be compatible with a single epitaxial growth, or alternatively, multiple epitaxial growths may be used, as appropriate. Different processes may be used for fabrication of the HBT epi-layers and PIN epi-layers. For example, in practice, MBE (Molecular Beam Epitaxy) may be used to provide the HBT epi-layers, and MOCVD (Metal Organic Chemical Vapor Deposition) may be used to provide the PIN epi-layers. A semi-insulating spacer may be provided between the HBT epi-layers and the PIN epi-layers. In other embodiments, it is preferred to select an epitaxial layer structure for the HBTs and the PIN which is compatible with single epitaxial layer growth.

[0095] A specific design issue for an optical receiver for a 1577 nm ONU is that 1577 nm is close to the InGaAs band edge, in a region where the absorption coefficient is already lower (see FIG. 21). One absorption length at this wavelength is roughly 1.4 μm, compared to well under 1 μm for a wavelength of 1300 nm. This means that it is more difficult to maximize the quantum efficiency. However, because 1577 nm is closer to the InGaAs band edge, then a high/low index lattice-matched dielectric stack has a larger possible contrast in this materials system, meaning that it becomes practical to make a mirror or reflector, to get effectively two passes through the i-InGaAs layer, i.e. effectively doubling the absorption length.

[0096] As an example, FIG. 18 shows a schematic cross-sectional view of an integrated PIN-TIA device structure 400 of second example embodiment, comprising a mirror 412 inserted between the n-contact layer 427 and the i-InGaAs layer 414 of the PIN. For example, the mirror 412 comprises a multi-layer stack of alternating high index (e.g. n-doped semiconductor)/low index quarter-wave lattice-matched layers. The n-doped materials of the multi-layer stack acts as the n-layer of the PIN. The other layers of the PIN and TIA are structured as described with reference to FIG. 17. Elements of the device structure 400 which are similar to device structure 300 of FIG. 17 are labelled with the same reference numerals incremented by 100. Thus, the HBT epitaxial layer structure 404 for the TIA circuitry 430, and PIN epitaxial layer structure 406 for the PIN 420 are formed on the substrate 402. The PIN epitaxial layer structure comprises a multilayer reflector structure 412 which acts as the n-layer, i-layer 414 and p-layer 416. Annular p-contact 422, with aperture window 424 is connected by PIN-TIA interconnect 440, through dielectric fill 408, to the TIA circuitry. The TIA circuitry 430 is formed on a first area of the substrate which is isolated by an isolation trench 450 from a second area of the substrate on which the PIN 420 is formed.

[0097] The graphical representation shown in FIG. 19 presents the results of some calculations to simulate the effect of adding a mirror. The starting point is the estimated nearly 3 dB QE loss from an existing state-of-the-art 56G or 28G PIN with a circular mesa and normal incidence, e.g. front entry geometry. By increasing the thickness of the i-InGaAs layer (labelled in FIG. 19 as t_InGaAs (μm)) along one horizontal axis of the plot), which becomes feasible because the parasitic capacitance of the bond pads of the PIN is no longer degrading the device performance, and adding a mirror having a mirror thickness (μm) (shown along the other horizontal axis of the plot), the simulation results show that the PIN can gain back somewhere between 1.5 to 2 dB in practical terms (see vertical axis for total QE loss for two-pass (dB)).

[0098] Thus, each of these design options, taken individually or in combination, enable fabrication of an optical receiver comprising a monolithically integrated PIN-TIA, with improved performance, e.g. to meet performance specifications for optical receivers for a 1577 nm ONU for 10G-PON. This design approach makes it feasible to replace a conventional hybrid APD and TIA with a monolithically integrated PIN-TIA of comparable sensitivity and responsivity. A monolithically integrated PIN-TIA implemented with commercially available InP process technology avoids the need for an APD and its high voltage power supply and control circuitry, and associated cost.

[0099] Since the example embodiments of monolithically integrated PIN-TIA herein has comparable sensitivity and responsivity to conventional/commercially available hybrid APD and TIA for 10G PON applications, the monolithically integrated PIN-TIA can be deployed in optical receivers for 1577 nm ONU for existing fiber networks, wherein the OLT use lasers providing a standard transmit power (e.g. DML 9 dBm or EML 4 dBm). Of course, use of higher transmit power lasers, which would relax required sensitivity specifications, may allow for further optimization of monolithically integrated PIN-TIA for next generation PON and other applications.

[0100] For some applications, it may be desirable to replace a discrete APD with a vertical PIN photodiode, as described above. Use of this design approach for monolithic integration of an APD and TIA using InP materials technology or monolithic integration of a waveguide PIN and a TIA based on InP materials technology is also contemplated as being feasible, and may have benefits for some high speed data applications. That is, reducing the photodetector capacitance may allow for optimization of other device parameters to provide for improved performance of optical receivers for other wavelengths covered by other types of InGaAs photodetector. In particular, elimination of pad capacitance for interconnection of the PIN and TIA allows for a higher transimpedance feedback resistance R.sub.F for higher transimpedance gain of the TIA.

[0101] In designing the TIA, reducing capacitance allows for a higher transimpedance feedback resistance R.sub.F, to increase gain, and the TIA noise is inversely proportional to the feedback resistance R.sub.F. It may be beneficial to match the capacitance of the TIA to the device capacitance of the PIN. Since there are a number of parameters that can be adjusted to achieve the required PIN-TIA performance, it may not be necessary to minimize the capacitance of the PIN. With respect to the ground pads of the PIN, it may be beneficial to use multiple pads, e.g. two pads will double capacitance, and halve inductance, e.g. use of multiple wire bonds for the ground pads reduces bond wire inductance (e.g. ˜1 nH/mm for 25 μm bond wires). In designing the PIN, if the responsivity, i.e. A/W, of the PIN is made high enough, so that the SNR in the PIN is higher, the PIN provides a higher input signal to the TIA. This means even if the TIA is noisier (e.g. from lower R.sub.F, from higher capacitance) the integrated PIN-TIA will provide improved SNR.

[0102] That is, for each of these examples, monolithic integration of the photodetector, whether the photodetector is a vertical InGaAs PIN, an InGaAs APD or an InGaAs waveguide PIN (e.g. lateral facet optical output), or other type of photodiode, elimination of bond pad capacitance of the PD has a significant effect on improving device performance, and enabling other parameters of the photodetector and the TIA to be modified or optimized, e.g. to improve quantum efficiency and other parameters to meet required specifications of sensitivity, responsivity, et al. for applications such as 10G PON and other high data rate applications requiring high performance modulation schemes. In the embodiments described above, the PIN may have an area (optical window), which is e.g. 16 μm to 20 μm in diameter. Since reducing the area of the PIN also reduces the capacitance, a smaller diameter PIN may be used in conjunction with a lens to match to the optical fiber spot size.

[0103] Monolithic integration of an InGaAs PIN using InP HBTs for the TIA provides a solution to a problem that is not easily solvable with silicon photonics comprising normal incidence, e.g. front-entry geometry, germanium (Ge) PINs. In the wavelength range of interest for 10G PON, Ge has a lower absorption coefficient then InGaAs (see FIG. 21), and 1577 nm is so close to the bandgap of Ge, that achieving high bandwidth and high responsivity simultaneously is quite difficult. In a Ge based system, it becomes necessary to use waveguide pin photodiodes or APDs to achieve both high responsivity and high bandwidth.

[0104] The monolithic integration approach described herein for reducing parasitic capacitances of the photodiode detector, and then adjusting other parameters of the PIN and TIA to improve quantum efficiency, e.g. to meet sensitivity and responsivity specification for high data rate applications may also be extendible to other types of photodiode detectors, e.g. unitary transit carrier (UTC) photodiode device structures and waveguide PIN geometries, et al.

[0105] Monolithic integration of the PIN-TIA eliminates hybrid integration parasitics such as, bond pad capacitances, wirebond resistance/inductance/etc., and direct interconnection of the PIN-TIA provides lower capacitance by eliminating bond pad capacitance, and provides a direct (short-length) lower inductance/lower resistance interconnection. Reduced bond pad capacitance provides associated degrees of freedom to provide improved bandwidth for a PIN of a given diameter and reduced noise.

[0106] The absorption layer thickness t.sub.i can be increased to improve responsivity. All else equal, an integrated pin-TIA will permit a greater overall bandwidth.

[0107] A semiconductor mirror can be inserted under the multiplication region to boost the reflectance. FIG. 19 shows the benefit of increasing either the absorption, the reflectance or both. Calculations for FIG. 19 were based on published data disclosed in an article by J. Brouckaert et al. (J. Lightwave Technology, Vol. 25, No. 4, April 2007). It is worth pointing out explicitly that at 1577 nm, a significantly greater contrast in refractive index is possible for the semiconductor mirror than, say, at 1.3 μm, or even for 1.50 μm. This is because a lower energy bandgap, and therefore higher refractive index, semiconductor can be used for the higher index transparent semiconductor, owing to the proximity between 1577 nm and the InGaAs bandgap wavelength of approximately 1650 nm. The mirror can be used either to supplement or replace lost (i.e. reduced) QE at 1577 nm. If C.sub.PIN is reduced, the highest bandwidth can be achieved for thinner t_InGaAs, (referred to as ti in other paragraphs), but at the cost of single-pass responsivity. A mirror, as described herein, can recover a significant amount of the non-absorbed light. In principle, the mirror can be made close to 100% reflecting, albeit at the cost of processing topography issues from a thick mirror. However. this issue has been addressed for standard VCSEL processing, which relies on the same principle. On the other hand, for application to ONU receivers operating at 1577 nm, the refractive index contrast possible in this application means that near 100% reflectivity could be achieved with fewer layers, and therefore less thickness (i.e. relative to that typically required for a VCSEL), which is a design-for-processing advantage.

[0108] Further Design Improvements

[0109] In a monolithically integrated PIN-TIA of a prototype embodiment, fabricated with an InGaAs PIN and TIA circuitry comprising InP HBTs, a responsivity of 0.69 A/W was achieved at 1550 nm. Based on the design methodology described herein, this responsivity can be improved by one or more of:

[0110] Increased absorption layer thickness: for an OLT application at 1557 nm there is room to increase the thickness t.sub.i without approaching the bandwidth limit. Based on empirical data combined with literature data and modeling, increasing the absorption layer thickness by just over 1.5× should give a 1 dB improvement.

[0111] Mirror provided below the absorption layer or RCE: If a mirror is provided, then we would expect >90% QE possible (and maybe 95%) for the OLT application. For 25 GHz operation, we would expect >85% QE (and maybe 90%) is possible.

[0112] Reduced absorption in other layers, e.g. p+ cap layer: a p+ cap layer provides reduced sheet resistance and contact resistance for the p-contact, but signal may be lost due to optical absorption. For example, thinning this layer or selecting a material, e.g. a lattice-matched InGaAlAsP composition (probably a quaternary, e.g. either InGaAlAs or InGaAsP) which transparent to 1.577 μm but close to the bandgap, may be a little worse for sheet and contact resistance but provide improved optical transmission. This same composition could probably be used for the higher refractive index layers of the mirror.

[0113] Anti-reflection coating: providing an antireflection coating optimized for the operating wavelength of 1.577 μm.

[0114] Monolithically Integrated PD-TIA of Other Embodiments

[0115] In other embodiments, the design principles disclosed herein for monolithic integration a PIN-TIA comprising an InGaAs PIN and a TIA circuitry fabricated with InP HBTs may be extended to monolithic integration of other types of photodiode with a TIA. Other types of photodiode detectors include, e.g. a Uni-Travelling Carrier (UTC) PD; a waveguide PIN; a resonance enhanced cavity PD; and an APD. To the Applicant's knowledge, monolithic integration of these types of PD with a TIA is not generally considered. However, to the extent that these device structures can be fabricated to be compatible with HBT technology, e.g. InP HBTs, or HBTs fabricated with other compatible semiconductor materials systems, other options for monolithically integrated PD-TIA with improved performance include the following types of PD:

[0116] UTC (uni-travelling carrier) PD. For further bandwidth improvement, a UTC PD design could be used. The benefits of UTC are well-understood. This design is likely to be compatible with HBT technology.

[0117] Waveguide pin. A waveguide pin can get as close to 100% responsivity as possible. For ultra-high speed and near-100% responsivity this may need to be accompanied by a traveling wave electrical signal. Traveling wave waveguide pins and modulators are well known in the literature.

[0118] Resonance enhanced cavity photodiode (or Resonant cavity enhanced (RCE) PD). This is an interesting option, because the basic idea is to use mirrors to get multiple, not just two, passes through the absorption region for maximum absorption for minimum absorption layer thickness. This device structure also provides a high selectivity of QE vs. wavelength, i.e. one wavelength of absorption is favored. This arrangement would work well for OLT having a well-defined specific wavelength, e.g. 1577 nm, or other applications for which the wavelength is well defined. The transit time is quite fast because the absorption layer is thin, and the performance is limited by capacitance. Eliminating bond pad capacitance through monolithic integration with a TIA, presents an attractive route to achieving a minimum, or at least substantially reduced, absorption thickness limit for a given bandwidth, to increase or maximize the advantage of resonant cavity enhancement.

[0119] APD. Currently available APDs struggle to get the bandwidth at 10 GHz and above. Monolithic integration of an APD and TIA reduces the device capacitance C.sub.APD of the APD, allowing, by an argument analogous to that above, a better chance of achieving a required bandwidth. Si APDs are known to be far superior to InP-based APDs in terms of excess noise, because of primarily electron injection into the multiplication region.

[0120] Although there are significant improvements to InP-based APDs, the carrier ratio at high gain implies that there is limited gain-bandwidth (GBW) product; further implying the need for additional improvements to make InP APDs practical for ultra-high speed use. For a monolithically integrated InP APD-TIA, a goal would be to try to reduce the carrier transit time. The transit time is multiplied by two for a SAGCM (Separate Absorption, Grading, Charge and Multiplication) APD, once to get the carriers to the multiplication region, and the other for the multiplied carriers to return to the opposite contact area. In this design, the PD capacitance would be increased, which would not usually be desirable, but this increase in capacitance is compensated for by the reduced capacitance of the monolithically integrated APD-TIA. The responsivity would decrease due to less absorption region, but the decreased absorption could be compensated for by a semiconductor mirror stack, e.g. as described with reference to FIG. 19.

[0121] Comparison with Silicon Photonics.

[0122] Silicon photonics (SiPh) is well known for integration of a PD with electronic circuitry; e.g. integration of circuitry with a PD that may be a pin PD or APD, waveguide or circular (i.e. normal incidence) geometry. Many of these applications for coherent communications require sufficiently fast PDs (usually pin photodiodes), e.g. for establishing the relative phase for QPSK and higher order QAM, high performance modulation schemes. For applications such as phase comparators, etc., implementing circuitry in silicon technology is straightforward. SiPh tends to use CMOS circuitry, with BJTs, e.g. for pads/macros, but not necessarily HBTs, which have a significant advantage over BJTs for f.sub.T, etc. To the Applicants knowledge, very few SiPh applications use a monolithically integrated PD with a TIA, which may be, for example, because effective CMOS circuitry requires smaller geometry (i.e. characterized by shorter transistor gate length) than would be economically effective.

[0123] The graph in FIG. 20 illustrates this from a Moore's Law perspective (the data comes from plotting data points available in Wikipedia a few years ago). Any technology below the photonic feature limit is suitable for silicon photonics. Gate length developments over the last half century will soon run into the atomic limit. Since the turn of the 21st century it has been possible to do silicon photonics, but at that time, it would have been expensive. What makes SiPh economical now is the march down the Moore's Law curve, making obsolete for silicon integrated circuits (ICs) what is perfectly fine for SiPh (e.g. 130 nm gate length technology), leaving existing fabs looking for business in gate length technologies no longer used by silicon ICs. The technologies needed to fabricate the best TIAs are expensive, or, to fabricate the TIAs in an obsolete technology for a cutting edge speed would either not be possible, or perhaps too costly due to the total die area needed for an obsolete technology. For example, a SiPh photonic integrated circuit having acceptable performance may be fabricated with lower cost Si process technology, e.g. 0.13-0.25 μm, on moderate diameter wafers (e.g. 8 inch), instead of more costly state-of-the-art, e.g. 5-14 nm technology. Consequently, TIAs are not generally fabricated using SiPh technology.

[0124] Optical Line Terminals (OLT) for PON Applications

[0125] For Optical Line Terminals (OLT) for PON applications, in particular, there is another reason relating to the PD itself why implementation using SiPh is difficult. 1577 nm is close to (or maybe even exceeding) the Ge bandgap energy. Ge is handicapped relative to InGaAs for absorption at this wavelength. If we translate absorption length (which represents 1-1/e, or 63% QE) to transit time requirement, even if the capacitance of the device were zero, the graph in FIG. 21 clearly illustrates the argument. The horizontal blue lines depict for the OLT 1577 nm application the hole (blue) and electron transit time limits (green) for 10 GHz and 100 GHz—above this line there is sufficient absorption and below the line there is not. The vertical line represents the target wavelength of interest for the OLT transmission wavelength of 1577 nm, and therefore the ONU reception wavelength, for this particular application. Since the Ge curve falls below the horizontal lines at 1577 nm, it is difficult to achieve good absorption in Ge for a normal-incidence geometry PD, whereas for InGaAs this is readily possible for 10 GHz and beyond, although not at 100 GHz. Also, there is increasing QE for a given InGaAs thickness for electron transport (see UTC argument below) than for hole transport (which dominates a normal incidence pin for which the absorption layer is not very thin relative to an absorption length. It is difficult to achieve good absorption in Ge for a circular i.e. normal incidence geometry PD, whereas for InGaAs this is readily possible. So, although 1577 nm stresses somewhat the QE vs bandwidth trade-off for InGaAs, this same wavelength makes circular, normal incidence, geometry Ge-based PDs with acceptable QE quite difficult. One would have to resort to a waveguide geometry for the Ge, if the absorption coefficient is high enough for that even to be done (1) without scattering, etc., by the usual imperfections in fabricated waveguides, and (2) to get the traveling wave of the electrical signal well enough matched for what would be a very long waveguide, which for high speed requires traveling wave.

[0126] Thus, implementation of a monolithically integrated PIN-TIA with a Ge PD in SiPh presents design and fabrication challenges and presents a “path of high resistance” to practical application. By comparison, monolithic integration of an InGaAs PIN and a TIA fabricated with InP HBTs as described herein, provides a path of “reduced resistance” to practical application, e.g. for OLT and ONU operating at 1.270 μm or 1.577 μm. Other absorption materials within the InGaAlAsP penternary system, lattice matched to InP can be used, but of all these, InGaAs lattice matched to InP has the lowest bandgap energy, is direct bandgap, and has the highest absorption coefficient near 1.3 μm or 1.5 μm, for the OLT and ONU or other typical applications at these wavelengths.

INDUSTRIAL APPLICABILITY

[0127] At the time of filing of U.S. 62/950,479, optical receivers for OLT and ONU for 10G PON and high speed data center interconnect use optical receivers comprising hybrid integrated APD and TIA, because APD have higher sensitivity than currently available pin PD at these operating wavelengths. For example, for a receiver for an ONU with an operating wavelength of 1577 nm, existing pin PDs do not have enough sensitivity to replace APDs for this application. This is, in part, because transmitted laser power is limited. In future, with higher power lasers, and a sufficiently sensitive pin PD and TIA, it would be possible to replace an avalanche photodiode and TIA with a pin photodiode and TIA. However, for 10G PON systems, operating at these wavelengths with available laser power, per current industry standards, another solution is needed.

[0128] In the approach described herein, a monolithically integrated PIN-TIA is disclosed, which has comparable sensitivity to a hybrid APD-TIA. A design methodology is presented for optimizing parameters of the monolithically integrated PIN-TIA to meet required specification for applications such as, optical receivers for ONU and OLT for 10G PON, operating at wavelengths in the ranges of ˜1.5 μm and ˜1.3 μm. Monolithic integration of a PIN and TIA with a direct on-chip interconnection of the PIN and TIA eliminates parasitics comprising bond pad capacitance and bondwire inductance, allowing for design improvements for enhanced performance. In particular, by reducing the device capacitance C.sub.PIN of the PIN, and correspondingly designing the TIA to reducing the capacitance C.sub.TIA of the TIA, reduces the combined device capacitance C.sub.PIN+C.sub.TIA, for increased sensitivity. Preferably the device capacitance is reduced sufficiently, so that other effects dominate, i.e. reduced device capacitance allows for associated degrees of freedom to select or optimize other device parameters for improved performance. For example, increasing the thickness t.sub.i of the i-layer, or including a reflector to create a dual-pass of absorbed light, to effectively double the absorption length to two times t.sub.i, increases QE and responsivity (A/W). In combination with selecting or optimizing other device parameters, e.g. the device area or diameter, a monolithically integrated PIN-TIA can be implemented, e.g. using an InGaAs PIN and TIA circuitry comprising InP HBTs, which provides sensitivity comparable to a hybrid APD-TIA currently used for this application.

[0129] In other embodiments, other types of PD are monolithically integrated with a TIA, using similar design principles, which reduce PD capacitance, and optimize other parameters comprising: the thickness t.sub.i of the i-layer, or effective absorption thickness of 2.Math.t.sub.1 if a mirror is included; an aperture diameter or device area; capacitance of the TIA and feedback resistance of the TIA; for improved performance of optical receivers for 10G PON, and for other high speed data applications, e.g. optical interconnect for datacentre and 5G applications.

[0130] Although embodiments of the invention have been described and illustrated in detail, it is to be clearly understood that the same is by way of illustration and example only and not to be taken by way of limitation, the scope of the present invention being limited only by the appended claims.