Signal processing arrangement for a transmitter

Abstract

A signal processing arrangement for a transmitter includes an in-phase modulator configured to receive an in-phase signal (I) and configured to modulate the in-phase signal (I); a quadrature modulator configured to receive a quadrature signal (Q) and configured to modulate the quadrature signal (Q); an in-phase demodulator configured to demodulate the modulated in-phase signal (I) and to output a demodulated in-phase signal (I); a quadrature demodulator configured to demodulate the modulated quadrature signal (Q) and to output a demodulated quadrature signal (Q); an in-phase harmonic filter configured to perform a filtering on harmonics in the demodulated in-phase signal (I) and to output an in-phase digital signal (I); and a quadrature harmonic filter configured to perform a filtering on harmonics in the demodulated quadrature signal (Q) and to output a quadrature digital signal (Q).

Claims

1. A signal processing apparatus for a transmitter, the signal processing apparatus comprising: an in-phase modulator configured to receive an in-phase signal (I) and configured to modulate the in-phase signal (I) to generate a modulated in-phase signal (I); a quadrature modulator configured to receive a quadrature signal (Q) and configured to modulate the quadrature signal (Q) to generate a modulated quadrature signal (Q); an in-phase demodulator coupled to the in-phase modulator and configured to: receive the modulated in-phase signal (I) from the in-phase modulator; demodulate the modulated in-phase signal (I) received from the in-phase modulator; and output a demodulated in-phase signal (I); a quadrature demodulator coupled to the quadrature modulator and configured to: receive the modulated quadrature signal (Q) from the quadrature modulator; demodulate the modulated quadrature signal (Q); and output a demodulated quadrature signal (Q); an in-phase harmonic filter coupled to the in-phase demodulator and comprising in-phase harmonic filters, wherein each of the in-phase harmonic filters is coupled to a corresponding in-phase demodulator, and wherein each of the in-phase harmonic filters is configured to perform filtering on harmonics in the demodulated in-phase signal (I) and to output a resulting in-phase digital signal (I); a quadrature harmonic filter coupled to the quadrature demodulator and comprising quadrature harmonic filters, wherein each of the quadrature harmonic filters is coupled to a corresponding quadrature demodulator, and wherein each of the quadrature harmonic filters is configured to perform filtering on harmonics in the demodulated quadrature signal (Q) and to output a resulting quadrature digital signal (Q).

2. The signal processing apparatus of claim 1, wherein the in-phase modulator and the quadrature modulator are configured to perform pulse code modulation or pulse width modulation.

3. The signal processing apparatus of claim 1, wherein the in-phase modulator comprises cascaded in-phase modulators, wherein the quadrature modulator comprises cascaded quadrature modulators, wherein each of the cascaded in-phase modulators is configured to provide a resulting modulated in-phase signal to the in-phase demodulator, and wherein each of the cascaded quadrature modulators is configured to provide a resulting modulated quadrature signal to the quadrature demodulator.

4. The signal processing apparatus of claim 3, wherein the in-phase demodulator comprises in-phase demodulators, wherein each of the in-phase demodulators is coupled to a corresponding in-phase modulator, wherein the quadrature demodulator comprises quadrature demodulators, and wherein each of the quadrature demodulators is coupled to a corresponding quadrature modulator.

5. The signal processing apparatus of claim 3, wherein at least one of the cascaded in-phase modulators is configured as a first pulse code modulator or a first pulse width modulator, and wherein at least one of the cascaded quadrature modulators is configured as a second pulse code modulator or a second pulse width modulator.

6. The signal processing apparatus of claim 5, wherein a last of the cascaded in-phase modulators and a last of the cascaded quadrature modulators are each configured as a sigma-delta modulator.

7. The signal processing apparatus of claim 3, wherein each cascaded in-phase modulator except a last of the cascaded in-phase modulators is configured to provide an in-phase error signal between an input signal and a resulting modulated in-phase signal to a succeeding cascaded in-phase modulator, and wherein each cascaded quadrature modulator except a last of the cascaded quadrature modulators, is configured to provide a quadrature error signal between an input signal and a resulting modulated quadrature signal to a succeeding cascaded quadrature modulator.

8. The signal processing apparatus of claim 7, wherein each cascaded in-phase modulator except the last of the cascaded in-phase modulators is configured to scale the in-phase error signal before providing the in-phase error signal to the succeeding cascaded in-phase modulator, and wherein each cascaded quadrature modulator except the last of the cascaded quadrature modulators is configured to scale the quadrature error signal before providing the quadrature error signal to the succeeding cascaded quadrature modulator.

9. The signal processing apparatus of claim 3, wherein the resulting modulated in-phase signal is a resulting modulated in-phase signal I.sub.SMn according to the following formula: $I_{\mathrm{SMn}}=\frac{\mathrm{Round}\left(I_{\mathrm{SSn}}.Math.0.5.Math.k_n\right)}{0.5.Math.k_n}$ where I.sub.SMn is the resulting modulated in-phase signal from an n:th cascaded in-phase modulator, k.sub.n is a predetermined n:th scale value, I.sub.SSn is an input signal to the n:th cascaded in-phase modulator and Round means rounding to a nearest integer value, and wherein the resulting modulated quadrature signal is a resulting modulated quadrature signal Q.sub.SMn according to the following formula: $Q_{\mathrm{SMn}}=\frac{\mathrm{Round}\left(Q_{\mathrm{SSn}}.Math.0.5.Math.k_n\right)}{0.5.Math.k_n}$ where Q.sub.SMn is the resulting modulated quadrature signal from the n :th cascaded quadrature modulator, k.sub.n is a predetermined n:th scale value, Q.sub.SSn is the input signal to the n:th cascaded quadrature modulator and Round means rounding to the nearest integer value.

10. The signal processing apparatus of claim 3, further comprising: a corresponding digital pre-distorter coupled to a corresponding in-phase modulator, wherein each digital pre-distorter is configured to compensate for non-linearity errors in an input signal to its corresponding in-phase modulator; and a digital pre-distorter coupled to a corresponding quadrature modulator, wherein each digital pre-distorter is configured to compensate for non-linearity errors in the input signal to its corresponding quadrature modulator.

11. The signal processing apparatus of claim 1, wherein each of the in-phase harmonic filters comprises an in-phase filter input configured to receive the demodulated in-phase signal and first two-phase data shifters for processing of the demodulated in-phase signal, wherein each of the first two-phase data shifters comprises a first phase data shifter and a second phase data shifter, wherein each quadrature harmonic filter block comprises a quadrature filter input configured to receive the demodulated quadrature signal and second two-phase data shifters for processing of the demodulated in-phase signal, and wherein each of the second two-phase data shifters comprises a first phase data shifter and a second phase data shifter.

12. The signal processing apparatus of claim 11, wherein the in-phase harmonic filters and the quadrature harmonic filters are configured to operate in at least a first mode, wherein in the first mode: in each of the in-phase harmonic filters, the first two-phase data shifters of the in-phase harmonic filter are cascaded, and the first two-phase data shifters of the in-phase harmonic filter are configured to receive the demodulated in-phase signal from the in-phase filter input; and in each of the quadrature harmonic filters, the second two-phase data shifters of the quadrature harmonic filter are cascaded, and the first two-phase data shifters of the quadrature harmonic filter are configured to receive the demodulated quadrature signal from the quadrature filter input.

13. The signal processing apparatus of claim 12, wherein in the first mode, the in-phase harmonic filters and the quadrature harmonic filters are configured to shift the demodulated in-phase signal from a first phase data shifter to a subsequent first phase data shifter based on a first reference clock signal (CLK1) and to shift data from a second phase data shifter to a subsequent second phase data shifter based on a second reference clock signal (CLK2), and wherein the first reference clock signal (CLK1) and the second reference clock signal (CLK2) both have a same frequency.

14. The signal processing apparatus of claim 12, wherein the in-phase harmonic filters and the quadrature harmonic filters are further configured to operate in a second mode, wherein in the second mode: in each of the in-phase harmonic filters, the first two-phase data shifters of the in-phase harmonic filter are configured in parallel and configured to receive the demodulated in-phase signal from the in-phase filter input; and in each of the quadrature harmonic filters, the first two-phase data shifters are coupled in parallel to the quadrature filter input.

15. The signal processing apparatus of claim 1, further comprising: an up-converter and mixer coupled to the in-phase harmonic filter and the quadrature harmonic filter, wherein the up-converter and mixer is configured to up-convert and mix the in-phase digital signal and the quadrature digital signal into an up-converted and mixed digital signal; a serializer coupled to the up-converter and mixer, wherein the serializer is configured to serialize the up-converted and mixed digital signal into serialized digital signals; and a power amplifier for each of the serialized digital signals, wherein each power amplifier is configured to power amplify a serialized digital signal and output a power amplified serialized digital signal.

16. The signal processing apparatus of claim 15, wherein the in-phase harmonic filters and the quadrature harmonic filters are configured to operate in at least a first mode and a second mode, wherein the in-phase modulator and the quadrature modulator are configured to operate at a modulation frequency (f.sub.s), wherein the serialized digital signals have a carrier frequency (f.sub.c), wherein the in-phase harmonic filter and the quadrature harmonic filter are configured to operate in the first mode when the modulation frequency (f.sub.s) is equal to the carrier frequency (f.sub.c), and wherein the in-phase harmonic filter and the quadrature harmonic filter are configured to operate in the second mode when the modulation frequency (f.sub.s) is different from the carrier frequency (f.sub.c).

17. The signal processing apparatus of claim 1, wherein the in-phase modulator, the quadrature modulator, the in-phase demodulator, the quadrature demodulator, the in-phase harmonic filter, and the quadrature harmonic filter are transmission components.

18. A signal processing method, comprising: receiving, by an in-phase modulator, an in-phase signal (I); modulating, by the in-phase modulator, the in-phase signal (I); receiving, by a quadrature modulator, a quadrature signal (Q); modulating, by the quadrature modulator, the quadrature signal (Q); receiving, by an in-phase demodulator from the in-phase modulator, a modulated in-phase signal (I); demodulating, by the in-phase demodulator, the modulated in-phase signal (I); outputting, by the in-phase demodulator, a demodulated in-phase signal (I); receiving, by a quadrature demodulator from the quadrature modulator, a modulated quadrature signal (Q); demodulating, by the quadrature demodulator, the modulated quadrature signal (Q); outputting, by the quadrature demodulator, a demodulated quadrature signal (Q); performing, by an in-phase harmonic filter comprising in-phase harmonic filters, filtering on harmonics in the demodulated in-phase signal (I), wherein each of the in-phase harmonic filters is coupled to a corresponding in-phase demodulator; outputting a resulting in-phase digital signal (I) based on performing the filtering on harmonics in the demodulated in-phase signal (I); performing, by a quadrature harmonic filer comprising quadrature harmonic filters, filtering on harmonics in the demodulated quadrature signal (Q), wherein each of the quadrature harmonic filters is coupled to a corresponding quadrature demodulator; and outputting a resulting quadrature digital signal (Q) based on performing the filtering on harmonics in the demodulated quadrature signal (Q).

19. The method of claim 18, wherein the in-phase modulator comprises cascaded in-phase modulators, wherein the quadrature modulator comprises cascaded quadrature modulators, and wherein the method further comprises: providing, by each of the cascaded in-phase modulators, a resulting modulated in-phase signal to the in-phase demodulator; and providing, by each of the cascaded quadrature modulators, a resulting modulated quadrature signal to the quadrature demodulator.

20. The method of claim 18, further comprising performing, by each of the in-phase modulator and the quadrature modulator, pulse code modulation or pulse width modulation.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 shows schematically a signal processing arrangement for a transmitter according to an embodiment of the present disclosure.

(2) FIG. 2 shows schematically a transmitter comprising a signal processing arrangement according to a second embodiment of the present disclosure.

(3) FIG. 3 shows schematically in more detail the transmitter in FIG. 2.

(4) FIG. 4 shows in more detail the in-phase digital harmonic filter and the quadrature digital harmonic filter of the signal processing arrangement in FIG. 1, FIG. 2 and FIG. 3.

(5) FIG. 5 shows in more detail the first in-phase harmonic filter block and the first quadrature harmonic filter block in the transmitter in FIG. 3.

(6) FIG. 6 shows schematically a transmitter device in a wireless communication system which transmitter device comprises a signal processing arrangement according to FIG. 2.

DETAILED DESCRIPTION

(7) In the following description embodiments of the disclosure the same reference numerals will be used for the same features in the different drawings.

(8) FIG. 1 shows schematically a signal processing arrangement 100 for a transmitter (not shown in FIG. 1) according to an embodiment of the present disclosure. The signal processing arrangement 100 comprises an in-phase modulator 102 configured to receive an in-phase signal I and configured to modulate the in-phase signal I, and a quadrature modulator 104 configured to receive a quadrature signal Q and configured to modulate the quadrature signal Q. The signal processing arrangement 100 also comprises an in-phase demodulator 140 configured to demodulate the modulated in-phase signal I.sub.M and to output a demodulated in-phase signal I.sub.DM, and a quadrature demodulator 142 configured to demodulate the modulated quadrature signal Q.sub.M and to output a demodulated quadrature signal Q.sub.DM. Furthermore, the signal processing arrangement 100 comprises an in-phase harmonic filter 106 configured to perform a filtering on harmonics in the demodulated in-phase signal I.sub.DM and to output an in-phase digital signal I.sub.D and a quadrature harmonic filter 108 configured to perform a filtering on harmonics in the demodulated quadrature signal Q.sub.DM and to output a quadrature digital signal Q.sub.D. Preferably, the in-phase modulator 102 and the quadrature modulator 104 are configured to perform pulse code modulation or pulse width modulation.

(9) In operation, an in-phase signal I (e.g. derived from an IQ signal) is input to the in-phase modulator 102 and a quadrature signal Q (e.g. derived from the IQ signal and synchronised to the in-phase signal I) is input to the quadrature modulator 104. The in-phase signal I and the quadrature signal Q are e.g. at least 12 bit digital signals. The in-phase modulator 102 modulates the in-phase signal I and outputs a modulated in-phase signal I.sub.M to the in-phase demodulator 140. The quadrature modulator 104 modulates the quadrature signal Q and outputs a modulated quadrature signal Q.sub.M to the quadrature demodulator 142. The in-phase demodulator 140 demodulates the modulated in-phase signal and outputs a demodulated in-phase signal I.sub.DM to the in-phase harmonic filter 106. The in-phase harmonic filter 106 performs a filtering on harmonics in the demodulated in-phase signal I.sub.DM and outputs an in-phase digital signal I.sub.D. The quadrature demodulator 142 demodulates the modulated quadrature signal and outputs a demodulated quadrature signal Q.sub.DM to the quadrature harmonic filter 108. The quadrature harmonic filter 108 performs a filtering on harmonics in the demodulated quadrature signal Q.sub.DM and outputs a quadrature digital signal Q.sub.D.

(10) FIG. 2 shows schematically a transmitter 200 comprising a signal processing arrangement 100 according to an embodiment of the present disclosure. Only the differences between the signal processing arrangement 100 of FIG. 1 and the signal processing arrangement 100 of FIG. 2 will be described. The transmitter 200 comprises a digital up-sampling device 150 comprising an input 152. The digital up-sampling device 150 does not form part of the signal processing arrangement 100. The digital up-sampling device 150 is configured to receive a digital input signal S.sub.IN on the input 152 and to up-sample and transform the digital input signal into an in-phase signal I and a quadrature signal Q. The in-phase signal I and the quadrature signal Q are inputs to the in-phase modulator 102 and the quadrature modulator 104 as has been described in connection with FIG. 1 above. Also the in-phase demodulator 140, the quadrature demodulator 142, the in-phase harmonic filter 106 and the quadrature harmonic filter 108 have been described in connection with FIG. 1.

(11) The signal processing arrangement 100 also comprises an up-conversion and mixing module 116 connected to the in-phase harmonic filter 106 and the quadrature harmonic filter 108. The up-conversion and mixing module 116 is configured to up-convert and mix the in-phase digital signal and the quadrature digital signal into an up-converted and mixed digital signal. The signal processing arrangement 100 also comprises a serializer 136 connected to the digital up-conversion and mixing module 116, and configured to serialize the up-converted and mixed digital signal into serialized digital signals. Furthermore, the signal processing arrangement 100 comprises a power amplifier 110 for each one of the serialized digital signals. Each power amplifier 110 is configured to power amplify a serialized digital signal and output the power amplified serialized digital signal. The signal processing arrangement 100 may be manufactured as an integrated circuit. The transmitter 200 comprises the above described digital up-sampling device 150. The transmitter 200 also comprises a power combination filter 112 which combines the power amplified serialized digital signals into a combined output signal which is output to a load in the form of an antenna 114. The power combination filter 112 may be realized in a large number of ways and its function is to combine the power amplified serialized digital signals from the power amplifiers 110.

(12) The digital up-sampling device 150 is driven by a first clock signal CLK1. Also the in-phase modulator 102 and the quadrature modulator 104 are driven by the first clock signal CLK1. The frequency of the first clock signal CLK1 is called the modulation frequency f.sub.s. The in-phase demodulator 140 and the quadrature demodulator 142 are driven by a second clock signal CLK2. The first clock signal CLK1 is equal to the second clock signal CLK2. I.e. the have the same frequency and phase. The in-phase harmonic filter 106 and the quadrature harmonic filter 108, are driven by a third clock signal CLK3 of a first phase PH1 and a second phase PH2. The frequency of the third clock signal CLK3 is called the carrier frequency f.sub.c. Depending on the working mode the carrier frequency f.sub.c may be equal to or different from the modulation frequency f.sub.s. The serializer 136 is driven by a fourth clock signal CLK4 having a frequency of 2 times the carrier frequency f.sub.c.

(13) The final signal processing steps are performed in the power combination filter 112. The in-phase harmonic filter 106 is configured to realize a part of the signal processing steps necessary for filtering out modulation harmonics in the demodulated in-phase signal I. Correspondingly, the quadrature harmonic filter 108 is configured to realize a part of the signal processing steps necessary for filtering out modulation harmonics in the demodulated quadrature phase signal Q. The remainder of the steps necessary for filtering out modulation harmonics in the demodulated in-phase signal and in the demodulated quadrature signal Q are performed in the power combination filter 112 after the up-conversion and mixing module 116, and after the serializer 136. An antenna 114 is connected to the power combination filter 112.

(14) FIG. 3 shows schematically in more detail the transmitter in FIG. 2. As can be seen in FIG. 3 the in-phase modulator 102 comprises cascaded in-phase modulator blocks 118, 118, 118, and the quadrature modulator 104 comprises cascaded quadrature modulator blocks 122, 122, 122. Furthermore, the in-phase demodulator 140 comprises in-phase demodulator blocks 146, 146, 146 and the quadrature demodulator 142 comprises quadrature demodulator blocks 148, 148, 148. Each in-phase demodulator block 146, 146, 146, is connected to a corresponding in-phase modulator block 118, 118, 118, and each quadrature demodulator blocks 148, 148, 148, is connected to a corresponding quadrature modulator block 122, 122, 122. Each one of the in-phase modulator blocks 118, 118, 118, is configured to provide a resulting modulated in-phase signal to the corresponding in-phase demodulator block 146, 146, 146 and each one of the quadrature modulator blocks 122, 122, 122 is configured to provide a resulting modulated quadrature signal to the corresponding quadrature demodulator block 148, 148, 148.

(15) The first and the second of the in-phase modulator blocks 118, 118, are configured as a pulse code modulator or a pulse width modulator. Correspondingly, the first and the second of the quadrature modulator blocks 122, 122, 122, are configured as a pulse code modulator or a pulse width modulator. The last of the cascaded in-phase modulator blocks 118, and the last of the cascaded quadrature modulator blocks 122 are configured as a sigma-delta modulator. Alternatively, both of the last of the cascaded modulator blocks 118 and 122 could be configured as a pulse width modulator PWM or a pulse code modulator PCM. Each in-phase modulator block 118, 118, except the last of the cascaded in-phase modulator blocks, is configured to provide an error signal between its input signal and its resulting modulated in-phase signal to the succeeding in-phase modulator block 118, 118. Each quadrature modulator block 122, 122, except the last of the cascaded quadrature modulator blocks, is configured to provide an error signal between its input signal and its resulting modulated quadrature signal to the succeeding quadrature modulator block 122, 122. Furthermore, each in-phase modulator block, except the last of the cascaded in-phase modulator blocks, is configured to scale its error signal before providing it to the succeeding in-phase modulator block, and each quadrature modulator block, except the last of the cascaded quadrature modulator blocks, is configured to scale its error signal before providing it to the succeeding quadrature modulator block. Thus, the modulation in the in-phase modulator 102 is as follows from the description of FIG. 4 below.

(16) Furthermore, the in-phase harmonic filter 106 comprises in-phase harmonic filter blocks 120, 120, 120, and the quadrature harmonic filter 108 comprises quadrature harmonic filter blocks 124, 124, 124, wherein each in-phase harmonic filter block 120, 120, 120 is connected to a corresponding in-phase modulator block 118, 118, 118 via a corresponding in-phase demodulator block 146, 146, 146, and each quadrature harmonic filter block 124, 124, 124 is connected to a corresponding quadrature modulator block 122, 122, 122 via a corresponding quadrature demodulator block 148, 148, 148. The in-phase harmonic filter blocks 120, 120, 120, and the quadrature harmonic filter blocks 124, 124, 124, will be described in more detail below with reference to FIG. 5.

(17) As is also shown in FIG. 3 the up-conversion and mixing module 116 comprises an in-phase up-conversion block 180, 180, 180, for each in-phase harmonic filter block 146, 146, 146, and a quadrature up-conversion block 182, 182, 182, for each quadrature harmonic filter block 148, 148, 148. The in-phase up-conversion blocks 180, 180, 180, and the quadrature up-conversion blocks 182, 182, 182 up-convert the filtered signals from the in-phase harmonic filter blocks 146, 146, 146, and the quadrature harmonic filter blocks 148, 148, 148. A mixer 184 is connected to the in-phase up-conversion blocks 180, 180, 180, and the quadrature up-conversion blocks 182, 182, 182. The mixer 184 performs mixing of the different signal from the in-phase up-conversion blocks 180, 180, 180, and the quadrature up-conversion blocks 182, 182, 182. The mixer is connected to a serializer 136, a power combination filter 112, and an antenna 114 as has been described in FIG. 2.

(18) FIG. 4 shows in more detail the in-phase modulator with cascaded in-phase modulator blocks. The in-phase signal I is input to the in-phase modulator 102. As can be seen in FIG. 4 the in-phase modulator 102 comprises four cascaded in-phase modulator blocks 118, 118, 118, 118. The in-phase modulator also comprises a corresponding digital pre-distorter 172, 172, 172, 172, for each in-phase modulator block, wherein each digital pre-distorter 172, 172, 172, 172, is configured to compensate for non-linearity errors in the input signal to its corresponding in-phase modulator block 118, 118, 118, 118. This requires knowledge on the non-linearity errors in the input signal. The quadrature modulator block is configured in a corresponding way and will not be described in detail herein. Each in-phase modulator block 118, 118, 118, 118, is configured to output a resulting modulated in-phase signal I.sub.SMn calculable according to the following formula:

(19) $I_{\mathrm{SMn}}=\frac{\mathrm{Round}\left(I_{\mathrm{SSn}}.Math.0.5.Math.k_n\right)}{0.5.Math.k_n}$
where I.sub.SMn is the resulting modulated in-phase signal from the n:th in-phase modulator block 118, 118, 118, k.sub.n is a predetermined n:th scale value, I.sub.SSn is the input signal to the n:th in-phase modulator block and Round means that the value is rounded to the nearest integer value. Furthermore, the n:th in-phase modulator block 118, 118, 118, except the last in-phase modulator block 118 is configured to calculate the input signal I.sub.SSn+1 to the following in-phase modulator block 118, 118, 118 according to the following formula:
I.sub.SSn+1=(I.sub.SSnI.sub.SMn).Math.k.sub.n.
As mentioned above the quadrature modulator is configured in the corresponding way. As an example we assume that the input signal I is 0.3 and that all k.sub.n are equal to 8. This means that the first modulated in-phase signal ISM1 from the first in-phase modulator block 118 is equal to:

(20) $I_{\mathrm{SMn}}=\frac{\mathrm{Round}\left(0.3.Math.0.5.Math.8\right)}{0.5.Math.8}$
i.e., I.sub.SM1=0.25. Furthermore, the second input signal I.sub.SS2 to the second modulator block is (0.30.25).Math.8=0.4.

(21) FIG. 5 shows in more detail the first in-phase harmonic filter block 120. Each in-phase harmonic filter block 120, 120, 120, comprises an in-phase filter input 138, 138, 138, (FIG. 3), configured to receive the demodulated in-phase signal. In FIG. 5 only the first in-phase harmonic filter block 120 is shown. The other in-phase harmonic filter blocks have the same layout. The first in-phase harmonic filter block 120 shown in FIG. 5 comprises two-phase data shifters 126, 126, 126, for processing of the demodulated in-phase signal. Each two-phase data shifter 126, 126, 126, comprises a first phase data shifter 128, 128, 128, and a second phase data shifter 130, 130, 130. Correspondingly, each quadrature harmonic filter block 124, 124, 124, comprises a quadrature filter input 164, 164, 164 configured to receive the demodulated quadrature signal. In FIG. 5 only the first quadrature harmonic filter block 124 is shown. The first quadrature harmonic filter block 124 comprises two-phase data shifters for processing of the demodulated in-phase signal. Each two-phase data shifter 166, 166, 166, comprises a first phase data shifter 168, 168, 168, and a second phase data shifter 170, 170, 170. A separate multiplexer unit MUX is arranged between the in-phase filter input 138 and each two-phase data shifter 126, 126 except the first two-phase data shifter 126, 126, 126. Each multiplexer unit MUX is also arranged between a two-phase data shifter and the previous two-phase data shifter 126, 126, and a previous two-phase data shifter 126, 126. A separate multiplexer unit MUX is arranged between the quadrature filter input 164 and each two-phase data shifter 166, 166 except the first two-phase data shifter 166. Each multiplexer unit MUX is also arranged between a two-phase data shifter 166, 166 and a previous two-phase data shifter 166, 166.

(22) The in-phase harmonic filter blocks 120, 120, 120, and the quadrature harmonic filter blocks 124, 124, 124, are configured to operate in at least a first mode. In the first mode, two-phase data shifters 126, 126, 126 of the first in-phase harmonic filter blocks 120, are configured cascaded, and the first two-phase data shifter 126 is configured to receive the demodulated in-phase signal from the in-phase filter input 138. The multiplexer units MUX are configured to connect the data shifters 126, 126, 126, to provide the data shifter cascaded in this first mode. Thus, the in-phase filter input 138 is connected only to the first two-phase data shifter 126 in this first mode. The other in-phase harmonic filter blocks 120, 120 (FIG. 3) are configured in the same way. In the first mode the two-phase data shifters 166, 166, 166 of the first quadrature harmonic filter block 124, 124, 124, are configured cascaded and the first two-phase data shifter 166 is configured to receive the demodulated quadrature signal from the quadrature filter input 164. The other quadrature harmonic filter blocks 124, 124 (FIG. 3), are configured in the same way.

(23) In the first mode, the in-phase harmonic filter blocks 120, 120, 120, and the quadrature harmonic filter blocks 124, 124, 124, are configured to shift the demodulated in-phase signal from a first phase data shifter 126, 126; 168, 168, to the subsequent first phase data shifter 126, 126; 168, 168, based on a first reference clock signal CLK3 PH1, and to shift data from a second phase data shifter 130, 130; 170, 170, to the subsequent second phase data shifter 130, 130; 170, 170, based on a second reference clock signal CLK3 PH2, wherein the first reference clock signal CLK3 PH1 and the second reference clock signal CLK3 PH2 both have the same frequency.

(24) In the embodiment described with reference to FIG. 5, the in-phase harmonic filter blocks 120, 120, 120, and the quadrature harmonic filter blocks 124, 124, 124, are configured to operate also in a second mode. This second mode is optional. In the second mode, in each in-phase harmonic filter block 120, 120, 120, the two-phase data shifters 126, 126, 126, are configured in parallel and configured to receive the demodulated in-phase signal from the in-phase filter input 138, and, in the quadrature harmonic filter blocks 124, 124, 124, the two-phase data shifters 166, 166, 166, are connected in parallel to the quadrature filter input 164. This is achieved by the multiplexer units MUX being configured to connect the in-phase filter input 138 with each one of the two-phase data shifters 126, 126, 126.

(25) FIG. 6 shows schematically a transmitter device 300 in a wireless communication system 400. The transmitter device 300 comprises a transmitter 100 according to FIG. 2 or FIG. 3. The wireless communication system 400 also comprises a base station 500 which may also comprise a quadrature digital power amplifier system 100 according to any one of the embodiments described above. The dotted arrow A1 represents transmissions from the transmitter device 300 to the base station 500, which are usually called up-link transmissions. The full arrow A2 represents transmissions from the base station 500 to the transmitter device 300, which are usually called down-link transmissions.

(26) The present transmitter device 300 may be any of a User Equipment (UE) in Long Term Evolution (LTE), mobile station (MS), wireless terminal or mobile terminal which is enabled to communicate wirelessly in a wireless communication system, sometimes also referred to as a cellular radio system. The UE may further be referred to as mobile telephones, cellular telephones, computer tablets or laptops with wireless capability. The UEs in the present context may be, for example, portable, pocket-storable, hand-held, computer-comprised, or vehicle-mounted mobile devices, enabled to communicate voice or data, via the radio access network, with another entity, such as another receiver or a server. The UE can be a Station (STA), which is any device that contains an IEEE 802.11-conformant Media Access Control (MAC) and Physical Layer (PHY) interface to the Wireless Medium (WM).

(27) The present transmitter device 300 may also be a base station a (radio) network node or an access node or an access point or a base station, e.g., a Radio Base Station (RBS), which in some networks may be referred to as transmitter, eNB, eNodeB, NodeB or B node, depending on the technology and terminology used. The radio network nodes may be of different classes such as, e.g., macro eNodeB, home eNodeB or pica base station, based on transmission power and thereby also cell size. The radio network node can be a Station (STA), which is any device that contains an IEEE 802.11-conformant Media Access Control (MAC) and Physical Layer (PHY) interface to the Wireless Medium (WM).