Three arm rectifier and inverter circuit

Abstract

A three arm rectifier and inverter circuit is provided. The three arm rectifier and inverter circuit includes an input end, a rectifier circuit and an inverter circuit. The input end is utilized for inputting an input voltage and an input current. The rectifier circuit includes a low frequency switching arm. The low frequency switching arm is coupled to the input end for receiving the input voltage and the input current and generating a trigger signal. The inverter circuit includes a full bridge switch. The full bridge switch is coupled to the low frequency switching arm for receiving the trigger signal and adjusting an output voltage.

Claims

1. A three arm rectifier and inverter circuit, comprising: an input end for inputting an input voltage and an input current; a rectifier circuit comprising a low frequency switching arm, wherein the low frequency switching arm is coupled to the input end for receiving the input voltage and the input current and generating a trigger signal; and an inverter circuit comprising a full bridge switch, wherein the full bridge switch is coupled to the low frequency switching arm for receiving the trigger signal and adjusting an output voltage, wherein the inverter circuit further comprises: a first current control circuit comprising a feed forward voltage signal and a feed forward current signal, wherein the feed forward voltage signal utilizes an output voltage command, a normal value of the input voltage and a disturbance value of the input voltage to eliminate a first disturbance of the full bridge switch, and the feed forward current signal is produced by multiplying an input current amplitude command with a synchronous sinusoidal signal and passed through an inductor with an angular frequency to eliminate a second disturbance of in the full bridge switch.

2. The three arm rectifier and inverter circuit of claim 1, wherein the full bridge switch comprises: a rectifier arm, wherein the rectifier arm is coupled to the low frequency switching arm for receiving the trigger signal and adjusting the input voltage and the input current; and an inverter arm, wherein a first terminal of the inverter arm is coupled to the rectifier arm and a second terminal of the inverter arm is coupled to a load, for adjusting the output voltage.

3. The three arm rectifier and inverter circuit of claim 1, further comprising: a first inductor, wherein a first terminal of the first inductor is coupled to the input end and a second terminal of the first inductor is coupled to the low frequency switching arm; and a second inductor, wherein a first terminal of the second inductor is coupled to a full bridge switch and a second terminal of the second inductor is coupled to a load.

4. The three arm rectifier and inverter circuit of claim 1, wherein after receiving the input voltage and the input current, the low frequency switching arm performs an upper arm trigger operation during a positive half cycle and performs a lower arm trigger operation during a negative half cycle.

5. The three arm rectifier and inverter circuit of claim 1, wherein the rectifier circuit comprises: a second current control circuit, wherein the second current control circuit comprises a feed forward control signal, the feed forward control signal utilizes a normal value and the disturbance value of the input voltage to eliminate a third disturbance of the low frequency switching arm; and a first voltage control circuit, wherein the first voltage control circuit utilizes a first direct current voltage controller to receive a difference between a direct current voltage command and a direct current voltage feedback value to generate an input current amplitude command, wherein first voltage control circuit generates an input current command by multiplying the input current amplitude command with a synchronous sinusoidal signal.

6. The three arm rectifier inverter circuit of claim 1, wherein the inverter circuit comprises: a second voltage control circuit, wherein the second cur voltage control circuit comprises a root mean square value control circuit, and the root mean square value control circuit 315 calculates a root mean square value of the output voltage.

7. The three arm rectifier inverter circuit of claim 6, wherein the root mean square value is compared to a root mean square value command and the comparison result is provided to a second direct current voltage controller, the second direct current voltage controller receives the comparison result and accordingly generates an amplitude correction command for correcting an original amplitude command to obtain a voltage amplitude command, and the voltage amplitude command is multiplied with a synchronous sinusoidal signal to obtain an instantaneous voltage command.

8. The three arm rectifier and inverter circuit of claim 1, wherein the inverter circuit comprises: a third direct current voltage controller, where the third direct current voltage controller receives a difference between an instantaneous voltage command and a direct current feedback value and accordingly generates an output current compensation command.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a schematic diagram of a conventional rectifier and inverter with half-bridge scheme according to the prior art.

(2) FIG. 2 is a schematic diagram of a conventional rectifier and inverter with no-bridge scheme according to the prior art.

(3) FIG. 3 is a schematic diagram of a three arm rectifier and inverter circuit according to an embodiment of the present invention.

(4) FIG. 4 is a schematic diagram illustrating the control circuit of the rectifier circuit shown in FIG. 3 according to an embodiment of the present invention.

(5) FIG. 5 is a schematic diagram illustrating the control circuit of the inverter circuit shown in FIG. 3 according to an embodiment of the present invention.

(6) FIG. 6 is a waveform diagram illustrating response waveform of the three arm rectifier and inverter circuit shown in FIG. 3 with the resistive load varying from 500 W to 1 kW according to an embodiment of the present invention.

(7) FIG. 7 is a waveform diagram illustrating response waveform of the three arm rectifier and inverter circuit shown in FIG. 3 with the R-C-D load (100 +68 uF) according to an embodiment of the present invention.

DETAILED DESCRIPTION

(8) The following illustrates specific embodiments of the present invention, and those skilled in the art can readily understand advantages and efficacy of the present invention accordingly.

(9) Please refer to FIG. 3, which is a schematic diagram of a three arm rectifier and inverter circuit according to an embodiment of the present invention. The three arm rectifier and inverter circuit includes an input end 1, a rectifier circuit 2 and an inverter circuit 3. The input end 1 is utilized for inputting an input voltage and an input current. The rectifier circuit 2 includes a low frequency switching arm 21. The low frequency switching arm 21 is coupled to the input end 1 for receiving the input voltage and the input current and generating a trigger signal. The inverter circuit 3 includes a full bridge switch 31. The full bridge switch 31 is coupled to the low frequency switching arm 21 for receiving the trigger signal and adjusting an output voltage according to the trigger signal.

(10) In a preferred embodiment, the full bridge switch 31 includes a rectifier arm 311 and an inverter arm 312. A combination of the rectifier arm 311 and the inverter arm 312 employs sinusoidal pulse width modulation (PWM) switching technique. The rectifier arm 311 is coupled to the low frequency switching arm 21 for receiving the trigger signal and accordingly adjusting the input voltage and the input current. A first terminal of the inverter arm 312 is coupled to the rectifier arm 311 and a second terminal of the inverter arm 312 is coupled to a load 4. The inverter arm 312 is utilized for adjusting the output voltage. In an alternative preferred embodiment, the three arm rectifier and inverter circuit further includes a first inductor 5 and a second inductor 6. A first terminal of the first inductor 5 is coupled to the input end 1 and a second terminal of the first inductor 5 is coupled to the low frequency switching arm 21. A first terminal of the second inductor 6 is coupled to the full bridge switch 21 and a second terminal of the second inductor 6 is coupled to the load 4.

(11) As shown in FIG. 3, the three arm rectifier and inverter circuit can be described as the following equation:

(12) $\begin{array}{cc}L\frac{d{I}_s}{dt}=V_s-V_{\mathrm{DN}}+V_{\mathrm{RN}}& \left(1\right)\\ L\frac{d{I}_o}{dt}=V_{\mathrm{IN}}-V_{\mathrm{RN}}-V_o& \left(2\right)\end{array}$

(13) Where L represents inductance, I.sub.s represents the input current, I.sub.o represents the output current, V.sub.s represents the input voltage, V.sub.o represents the output voltage. Suppose a voltage V.sub.DN between nodes D and N of the low frequency switching arm 21 is decided based on the conducting state of the low frequency switch. The conducting state of the low frequency switch is synchronized with the voltage of the mains power (also called grid power) voltage. After the low frequency switching arm 21 receives the input voltage and the input current, the low frequency switching arm 21 performs an upper arm trigger operation during a positive half cycle and performs a lower arm trigger operation during a negative half cycle. Equation (1) can be rewritten as follows:

(14) $\begin{array}{cc}L\frac{d{I}_s}{dt}=V_s-\left[\frac{1}{2}+\frac{\mathrm{sign}\left(V_s\right)}{2}\right]V_d+V_{\mathrm{RN}}& \left(3\right)\end{array}$

(15) Where sign( ) is a function, when the input voltage V.sub.s is positive, sign (V.sub.s)=+1, and when the input voltage V.sub.s is negative, sign (V.sub.s)=1. The full bridge switch 31 employs the sinusoidal PWM switching technique. An output voltage V.sub.RN of the rectifier arm 311 and an output voltage V.sub.IN of the inverter arm 312 can be expressed as follows:

(16) $\begin{array}{cc}{V}_{\mathrm{RN}}=\left(\frac{1}{2}+\frac{v_{\mathrm{conR}}}{2v_{\mathrm{tm}}}\right)V_d& \left(4\text{-}1\right)\\ V_{\mathrm{IN}}=\left(\frac{1}{2}+\frac{v_{\mathrm{conI}}}{2v_{\mathrm{tm}}}\right)V_d& \left(4\text{-}2\right)\end{array}$

(17) Where v.sub.tm represents the amplitude of a PWM triangle wave, v.sub.conR and v.sub.conI represent the control voltage of the rectifier arm 311 and the inverter arm 312 respectively. By substituting equation (4-1) and equation (4-2) into equation (2), the following equation is obtained:

(18) $\begin{array}{cc}L\frac{d{I}_s}{dt}=V_s-\left[\frac{1}{2}+\frac{\mathrm{sign}\left(V_s\right)}{2}\right]V_d+k_{\mathrm{pwm}}{v}_{\mathrm{conR}}& \left(5\right)\\ \mathrm{Where}& \\ k_{\mathrm{pwm}}=\frac{V_d}{v_{\mathrm{tm}}}& \left(6\right)\end{array}$

(19) k.sub.pwm can be regarded as a gain of PWM converter. Further, by adding equation (2) to equation (5) and substituting the control voltages of equation (4-1) and equation (4-2), the following equation is obtained:

(20) $\begin{array}{cc}L\left(\frac{d{I}_s}{dt}+\frac{d{I}_o}{dt}\right)=k_{\mathrm{pwm}}{v}_{\mathrm{conI}}-\frac{\mathrm{sign}\left(V_s\right)}{2}{V}_d-V_o+V_s& \left(7\right)\end{array}$

(21) Further, please refer to FIG. 4. FIG. 4 is a schematic diagram illustrating the control circuit of the rectifier circuit 2 shown in FIG. 3 according to an embodiment of the present invention. As shown in FIG. 4, the rectifier circuit 2 includes a low frequency switching arm 21, a first current control circuit 22 and a first voltage control circuit 23. The low frequency switching arm 21 is drawn according to equation (5). The first current control circuit 22 and the first voltage control circuit 23 are the control circuit of the rectifier circuit 2. The first current control circuit 22 employs both a feed forward control and a feedback control. The first current control circuit includes a feed forward control signal v.sub.fR and the feed forward control signal feed v.sub.fR utilizes a normal value v.sub.sn of the input voltage and a disturbance value sign(V.sub.s)v.sub.d*/2 of the input voltage to eliminate a first disturbance of V.sub.s and sign(V.sub.s)v.sub.d/2 in the low frequency switching arm 21. Since the feed forward control signal v.sub.fR can eliminate the first disturbance of V.sub.s and sign(V.sub.s)v.sub.d/2 of the low frequency switching arm 21, a current feedback controller k.sub.1 merely employs a proportional control. According to FIG. 4, a response of that the first input current tracks the current command can be derived as follows:

(22) $\begin{array}{cc}\frac{i_s}{i_s^{*}}=\frac{\frac{k_{\mathrm{pwm}}{k}_s{k}_1}{L}}{s+\frac{k_{\mathrm{pwm}}{k}_s{k}_1}{L}}=\frac{u_R}{s+u_R}& \left(8\right)\end{array}$

(23) Where k.sub.s and k.sub.v represent a current sensing proportion and a voltage sensing proportion respectively, i.sub.s represents an input current feedback value, the input current feedback value i.sub.s is produced by passing the input current I.sub.s through the current sensing proportion k.sub.s, u.sub.R (rad/s) is equivalent to the bandwidth of the current control loop and u.sub.R can be set by using a control gain k.sub.1.

(24) The first voltage control circuit 23 employs a feedback control. The first voltage control circuit 23 utilizes a first direct current voltage controller G.sub.d to receive an error (difference) between a direct current voltage command v.sub.d* and a direct current voltage feedback value v.sub.d to generate an input current amplitude command is i.sub.sm*. A synchronous sinusoidal signal sin t is obtained by passing the input voltage V.sub.s through a phase locked loop. An input current command i.sub.s* value is produced by multiplying the input current amplitude command i.sub.sm* with the synchronous sinusoidal signal sin t. Since the DC voltage may include secondary ripple (2f.sub.0), the first direct current voltage controller (Gd) can be designed to make the voltage loop bandwidth much lower than the secondary frequency for attenuating the secondary voltage ripple and achieving low input current distortion.

(25) Moreover, please refer to FIG. 5. FIG. 5 is a schematic diagram illustrating the control circuit of the inverter circuit 3 shown in FIG. 3 according to an embodiment of the present invention. As sown in FIG. 5, the inverter circuit 3 includes a full bridge switch 31, a second current control circuit 313 and a second voltage control circuit 314. As shown in FIG. 3, an output capacitor C can be described as the following equation:

(26) $\begin{array}{cc}C\frac{d{V}_o}{dt}=I_o-I_L& \left(9\right)\end{array}$

(27) Therefore, equation (7) can be rewritten as follows:

(28) $\begin{array}{cc}L\frac{d{I}_o}{dt}=k_{\mathrm{pwm}}{v}_{\mathrm{conI}}-\frac{\mathrm{sign}\left(V_s\right)}{2}{V}_d-V_o+V_s-L\frac{d{I}_s}{dt}& \left(10\right)\end{array}$

(29) Under operating with unity power factor control, the input current I.sub.s is a pure sine wave. Therefore, equation (10) can be rewritten as follows: (10)

(30) $\begin{array}{cc}L\frac{d{I}_o}{dt}=k_{\mathrm{pwm}}{v}_{\mathrm{conI}}-\frac{\mathrm{sign}\left(V_s\right)}{2}{V}_d-V_o+V_s-L{I}_{\mathrm{sm}}\cos t& \left(11\right)\end{array}$

(31) Where I.sub.sm represents the amplitude of the input current, represents the angular frequency of the input voltage. A circuit model of the full bridge switch 31 can be drawn according to equation (9) and equation (10). The inverter circuit 3 employs double loop control. The outer loop is the second voltage control circuit 314. The inner loop is the second current control circuit 313.

(32) The second current control circuit 313 employs both the feed forward control and the feedback control. The second current control circuit 313 includes a feed forward voltage signal v.sub.fv and a feed forward current signal v.sub.fi. The feed forward voltage signal v.sub.fv utilizes an output voltage command v.sub.o, a normal value v.sub.sn of the input voltage and a disturbance value sign(V.sub.s)v.sub.d*/2 of the input voltage to eliminate a second disturbance of V.sub.o, V.sub.s and sign (V.sub.s) V.sub.d/2 in the full bridge switch 31. The feed forward current signal v.sub.fi is produced by multiplying the input current amplitude command i.sub.sm* with the synchronous sinusoidal signal sin t and passing through an inductor with an angular frequency L to eliminate a third disturbance of LI.sub.sm cos t in the full bridge switch 31. By using above feed forward control, a current feedback controller k.sub.2 can merely employ a proportional control k.sub.2. According to FIG. 5, a response of that the second input current tracks the current command can be derived as follows:

(33) 0$\begin{array}{cc}\frac{i_o}{i_o^{*}}=\frac{\frac{k_{\mathrm{pwm}}{k}_s{k}_2}{L}}{s+\frac{k_{\mathrm{pwm}}{k}_s{k}_2}{L}}=\frac{u_I}{s+u_I}& \left(12\right)\end{array}$

(34) Where i.sub.o* represents an output current command, the output current command i.sub.o* is produced by adding an output current compensation command i.sub.fb* generated by the voltage loop to an inductor current feedback value i.sub.L, the inductor current feedback value i.sub.L is produced by passing an inductor current I.sub.L through the current sensing proportion k.sub.s, i.sub.o represents an output current feedback value, the output current feedback value i.sub.o is produced by passing the output current I.sub.o through the current sensing proportion k.sub.s, and u.sub.I can be regards as the bandwidth of the current control loop.

(35) The second voltage control circuit 314 employs a feedback control. For improving the voltage regulation rate, the second voltage control circuit 314 includes a root mean square value control circuit 315. The root mean square value control circuit 315 calculates a root mean square value v.sub.om. The root mean square value v.sub.om is compared to a root mean square value command v.sub.om*, and the comparison result is provided to a second direct current voltage controller G.sub.m. The second direct current voltage controller G.sub.m receives the comparison result and accordingly generates an amplitude correction command A.sub.mr for correcting an original amplitude command A.sub.m0 to obtain a voltage amplitude command A.sub.m. The voltage amplitude command A.sub.m is multiplied with the synchronous sinusoidal signal sin t to obtain an instantaneous voltage command v.sub.o*. The inverter circuit 3 includes a third direct current voltage controller G.sub.v. The third direct current voltage controller G.sub.v receives an error (difference) between an instantaneous voltage command v.sub.o* and the direct current feedback value v.sub.o and generates the output current compensation command i.sub.fb*.

(36) Moreover, please refer to FIG. 6 and FIG. 7. FIG. 6 is a waveform diagram illustrating response waveform of the three arm rectifier and inverter circuit shown in FIG. 3 with the resistive load varying from 500 W to 1 kW according to an embodiment of the present invention. FIG. 7 is a waveform diagram illustrating response waveform of the three arm rectifier and inverter circuit shown in FIG. 3 with the R-C-D load (100 +68 uF) according to an embodiment of the present invention. As shown in FIG. 6, FIG. 6 shows the waveform while the resistive load varies from 500 W to 1 kW. The input current I.sub.s inputted to the rectifier circuit 2 can close track the response of the command I.sub.sc so as to verify the effectiveness of the current controller. The direct current voltage V.sub.d can also maintain at 400V accurately and quickly return to 400V under the load change, thus achieving excellent dynamic response and verifying the effectiveness of the direct current voltage control loop. Besides, the input current I.sub.o inputted to the inverter circuit 3 can close track the response of the command I.sub.oc so as to verify the effectiveness of the current controller. Further, the output voltage V.sub.o can close track the response of the command V.sub.oc, and the waveforms almost overlap to the same waveform, thus achieving low output impedance purpose.

(37) As shown in FIG. 7, FIG. 7 shows the response waveform under the R-C-D load (100 +68 uF). Although the current distortion is severe under the influence of the R-C-D load, the input current is quite close to the sine wave after being compensated by the current of the rectifier arm 311, thus verifying the function of active filter for the rectifier arm 311. The direct current voltage V.sub.d can also maintain at 400V accurately. Similarly, the waveforms almost overlap to the same waveform, thus achieving low output impedance purpose.

(38) In summary, since the input voltage and the output voltage of the invention structure employ the same common neutral, the invention can merely use a single capacitor and the direct current voltage merely needs to be higher than the peak value of the input voltage. When the input voltage is interrupted and the direct current link is connected to the direct current power supply, the full bridge can continue to provide the load voltage. In addition, the current of the rectifier arm 311 is a difference between the input current and the load current. Under the condition of PFC (power factor correction), it is only necessary to retain the reactive power of the load, the harmonic current and the small amount of real power component of the compensation inverter, such that the conduction loss of the invention is less than the conventional architecture. Moreover, the embodiments of the invention employ the low frequency switching control method synchronized with the mains power so as to reduce the switching loss.

(39) Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.