Coupled quantum dot memristor

Abstract

The present disclosure relates to novel memristive devices, uses thereof, and processes for their preparation. In a first aspect, the disclosure provides a quantum memristor, including a first quantum dot (QD1) which is capacitively coupled to a second quantum dot (QD2), a source electrode, a drain electrode, and a bath electrode, wherein the source electrode and the drain electrode are coupled via quantum tunneling to QD1 and the bath electrode is coupled via quantum tunneling to QD2, and wherein QD2 is capacitively coupled to either the source electrode or the drain electrode.

Claims

1. A quantum memristor, comprising: a first quantum dot (QD1) which is capacitively coupled to a second quantum dot (QD2), a source electrode, a drain electrode, and a bath electrode, wherein said source electrode and said drain electrode are coupled via quantum tunneling to QD1 and said bath electrode is coupled via quantum tunneling to QD2, and wherein QD2 is capacitively coupled to either the source electrode or the drain electrode.

2. A quantum memristor according to claim 1, wherein QD1 and QD2 are of the same material as one another.

3. A quantum memristor according to claim 1, wherein QD1 and QD2 are of different materials to one another.

4. A quantum memristor according to claim 1, wherein QD1 and QD2 are the same size and/or shape as one another.

5. A quantum memristor according to claim 1, wherein QD1, the source electrode and the drain electrode are formed from a single piece of material and wherein QD1 is defined by a first constriction and a second constriction in said single piece of material, said first constriction being located between QD1 and the source electrode and said second constriction being located between QD1 and the drain electrode; and wherein QD2 and the bath electrode are formed from a single piece of material and wherein QD2 is defined by a constriction in said single piece of material located between QD2 and the bath electrode; wherein said constrictions between QD1 and the source and drain electrodes and between QD2 and the bath electrode act as tunnel barriers.

6. A quantum memristor according to claim 5, wherein said constrictions are produced lithographically.

7. A quantum memristor according to claim 1, wherein QD1 and QD2 are in lithographically-defined channels and wherein tunneling barriers between QD1, the source electrode and the drain electrode, and between QD2 and the bath electrode, are provided by gate electrodes.

8. A quantum memristor according to claim 1, wherein QD1 and QD2 are regions in a two-dimensional electron/hole gas which are defined by barrier gates and plunger gates and wherein QD1 is separated from the drain and reservoir electrode by electrode gates.

9. A quantum memristor according to claim 8 wherein said two-dimensional electron/hole gas is a patterned semiconductor material.

10. A quantum memristor according to claim 9 wherein said two-dimensional electron/hole gas is a semiconductor heterostructure.

11. A quantum memristor according to claim 1, wherein QD1 and QD2 are each independently a single atom, molecule or nanoparticle.

12. A quantum memristor according to claim 1, wherein the bath electrode has a nonzero energy gap.

13. A multiple quantum-dot memristor comprising two or more quantum memristors as defined in claim 1, wherein said two or more quantum memristors are arranged in parallel.

14. A computer-readable storage medium comprising at least one quantum memristor according to claim 1.

15. A method for the storage of information in a quantum memristor, the method comprising: providing a quantum memristor as defined in claim 1 wherein QD2 has a first occupancy level; and applying a voltage across the first and second electrodes to cause the occupancy level of QD2 to change to a second occupancy level; wherein changing the occupancy level of QD2 from the first to the second occupancy level corresponds to the storage of at least one bit of information.

16. A method according to claim 15 wherein said information is binary information.

17. A method according to claim 16 wherein one of said first and said second occupancy levels of QD2 corresponds to a 1 in binary language and the other of said first and said second occupancy levels of QD2 corresponds to a 0 in binary language.

18. A method according to claim 15 wherein said information is quantum information.

19. A method according to claim 18 wherein changing the occupancy level of QD2 from the first to the second occupancy level corresponds to the storage of at least one qubit.

20. A method according to claim 15 wherein said storage of information is in a computer system.

21. A method according to claim 20 wherein said computer system comprises a quantum computer.

22. A computer-readable storage medium comprising at least one multiple quantum dot memristor according to claim 13.

Description

(1) The invention will now be described in more detail in the following non-limiting Examples and Figures, in which:

(2) FIG. 1 illustrates a quantum-dot memristive system according to the invention. FIG. 1(a) shows a schematic of the structure of the device and FIG. 1(b) shows an SEM image of one experimental embodiment of such a device. FIG. 1(c) shows the relationship between the energies of electrodes L and R and quantum dot QD1 when a voltage is applied. FIG. 1(d) shows the relationship between the energy levels of the electrode B and of quantum dot QD2, assuming a nonzero energy gap.

(3) FIGS. 2A and 2B illustrate simulated current-voltage curves of a quantum-dot memristive system according to the invention derived from a periodic voltage.

(4) FIG. 3 illustrates quantum trajectory simulations of the instantaneous current in a quantum-dot memristive system according to the invention (FIGS. 3(a), (b) and (c)) and experimental data (FIG. 3(d)).

(5) FIG. 4 illustrates quantum trajectory simulations of electron tunnelings in a quantum-dot memristive system according to the invention.

(6) FIG. 5 illustrates a lithographically-defined quantum memristive device according to the invention.

(7) FIG. 6 illustrates an electrostatically-defined quantum memristive device according to the invention.

(8) FIG. 7 illustrates a further electrostatically-defined quantum memristive device according to the invention.

(9) FIG. 8 illustrates a quantum memristive device according to the invention in which the QDs are formed by individual atoms, molecules or nanoparticles.

(10) FIG. 9 illustrates simulated and experimental I-V curves showing current hysteresis in the Si double dot system which is the subject of FIG. 1(b).

EXAMPLE 1

(11) FIG. 1 illustrates a schematic of a quantum-dot memristive system according to the invention. As shown in FIG. 1(a), the device has two terminals: electrode-L and electrode-R. When a voltage V is applied on the device, electrochemical potentials in these two electrodes are respectively .sub.L=|e|V/2 and R=|e|V/2. The two terminals are coupled to the quantum dot QD1 via tunneling with the strength .sub.1, hence current can go through the device via QD1. The quantum dot QD2 is capacitively coupled to QD1 and to the electrode-L and is coupled to electrode-B via tunneling with the strength .sub.2. The electrochemical potential in the electrode-B is .sub.B=0.

(12) FIG. 1(b) is an SEM image showing an experimental embodiment of a memristive system according to the invention. Three layers of aluminium gates were used to define a capacitively coupled pair of quantum dots in undoped silicon. The center-to-center distance between the two dots was 140 nm. Labels LA.sub.1, LD.sub.1, P.sub.1, RD.sub.1, RA.sub.1, LA.sub.2, LD.sub.2, P.sub.2, RD.sub.2, RA.sub.2 label the different gates. Labels L, R and B (superimposed on the image) indicate the leads accumulated in the Si. For each dot there were two accumulation gates (LA, RA), two depletion gates (LD, RD), and a plunger gate (P). A dot was formed under each plunger gate where it intersected the two accumulation gates. In this particular embodiment, electrode-L was connected to a local gate of QD2 (i.e. LD2) rather than to a capacitively coupled lead as shown in FIG. 1(a).

(13) The current of a memristive system according to FIG. 1(a) or 1(b) is switched on when the energy level of QD1 is between .sub.L and R and off when the energy level of QD1 is above max{.sub.L,R} or below min {.sub.L, R}. This is shown in FIG. 1(c).

(14) If there is an energy gap around the Fermi energy in the spectrum of the electrode-B of a memristive system according to FIG. 1(a) or 1(b), as shown in FIG. 1(d), QD2 can be loaded with an electron only when the energy level is lower than the gap and unloaded only when the energy level is above the gap.

EXAMPLE 2

(15) FIG. 2 illustrates simulated current-voltage curves of a quantum-dot memristive system according to the invention derived from a periodic voltage.

(16) In the simulations shown in FIGS. 2A(a) and 2A(b), the voltage is in the form V(t)=V.sub.A cos t, where V.sub.A=2 meV and =21 MHz. The temperature is T=0.3 K, the capacitive coupling between the two quantum dots QD1 and QD2 is E.sub.C=10 meV, the tunneling coupling of QD1 is .sub.1=1 meV, and the lever arm of the electrode-L gating QD2 is 1. (The lever arm is the ratio between the shift of energy level E.sub.2 and the applied voltage, multiplied by the charge of an electron).

(17) In the simulation shown in FIG. 2A(a), the electrode-B has an energy gap E=1 meV centered at the energy 0, and the tunneling coupling of QD2 is {tilde over ()}.sub.2=1 eV. When the energy level of QD2 is within the energy gap, i.e. V[1 meV, 1 meV], QD2 is empty (|0.sub.2) when the voltage is decreasing and occupied (|1.sub.2) when the voltage is increasing.

(18) In the simulation shown in FIG. 2A(b), the electrode-B has a closed energy gap, i.e. E=0, and the tunneling coupling of QD2 is {tilde over ()}.sub.2=0.1 eV. QD2 is likely empty when the voltage is decreasing but still positive, occupied when the voltage is increasing but still negative and in a mixed state in other cases. Currents are obtained by numerically solving the master equation as described herein.

(19) In the simulations shown in FIGS. 2B(a) and 2B(b), the voltage is in the form V(t)=V.sub.A cos t, where V.sub.A=1 meV and =21 MHz. The temperature is T=0.3 K, the capacitive coupling between the two quantum dots QD1 and QD2 is E.sub.C=1 meV, the tunneling coupling of QD1 is .sub.1=2 GHz, and the lever arm of the electrode-L gating QD2 is 1. Average current through QD1 is obtained by solving the master equation.

(20) In the simulation shown in FIG. 2B(a), the electrode-B has a closed energy gap, i.e. E=0, and the tunneling coupling of QD2 is {tilde over ()}.sub.2=10 Hz. QD2 is likely empty (|0.sub.2) when the voltage is decreasing but still positive, occupied (|1.sub.2) when the voltage is increasing but still negative and in a mixed state in other cases.

(21) In the simulation shown in FIG. 2B(b), the electrode-B has an energy gap E=0.5 meV centered at the energy 0, and the tunneling coupling of QD2 is {tilde over ()}.sub.2=100 Hz. When the energy level of QD2 is within the energy gap, i.e. V[0.5 meV, 0.5 meV], QD2 is empty (|0.sub.2) when the voltage is decreasing and occupied (|1.sub.2) when the voltage is increasing.

EXAMPLE 3

(22) FIG. 3 illustrates quantum trajectory simulations of the instantaneous current in a quantum-dot memristive system according to the invention. Parameters are the same as described in Example 2.

(23) FIG. 3(a) illustrates the voltage applied on the two terminals as a function of time.

(24) FIGS. 3 (b) and (c) illustrate the current which is produced by the voltage illustrated in (a). The energy gap in the electrode-B is open (i.e. non-zero) in (b) and closed (i.e. zero) in (c). The instantaneous current (solid curve) is different from the average current (dashed curve) due to quantum jumps, which correspond to sudden changes of the instantaneous current.

(25) FIG. 3(d) shows experimental data which was recorded for a working embodiment (as shown in FIG. 1(d) and described in further detail in Example 9). The solid curve is the instantaneous current and the dashed curve is the current averaged over 10 sweeps. Arrows indicate the position of abrupt current jumps. The jump positions varied stochastically from sweep to sweep, consistent with the expected behaviour of quantum jumps.

EXAMPLE 4

(26) FIG. 4 illustrates quantum trajectory simulations of electron tunnelings in a quantum-dot memristive system according to the invention. The tunneling coupling of QD1 is .sub.1=1 eV, and other parameters are the same as described in Example 2. The energy gap in the electrode-B is open in (a) and (b) and closed in (c) and (d).

(27) FIGS. 4(a) and 4(c) illustrate the count of electrons tunneling from QD1 to electrode-R in a single trial.

(28) FIGS. 4(b) and 4(d) illustrate the averaged current obtained from 1000 trials (solid curve) which converges to the dashed curve when the number of trials goes to infinity.

EXAMPLE 5

(29) FIG. 5 illustrates a lithographically defined quantum memristive device in which barriers to QD1 and QD2 are formed by lithographically defined notches (constrictions) in the material, which may be a metal or a semiconductor material such as silicon or gallium-arsenide, or a two-dimensional material such as graphene.

(30) Devices are lithographically defined using electron beam or optical lithography and wet chemical etching, reactive ion etching or plasma etching. The QDs are formed between tunnel barriers formed by constrictions (notches) in the channel. The devices can be fabricated from metal or semiconductor material such as silicon, or gallium-arsenide, or two-dimensional materials such as graphene.

EXAMPLE 6

(31) FIG. 6 illustrates an electrostatically defined quantum memristive device. Devices of this type are defined by tunnel barriers which are electrostatically induced by gate electrodes. In the embodiment shown, QDs are formed in lithographically defined channels defined by tunnel barriers which are electrostatically induced by gate electrodes.

(32) Gates L1, L2 and R1, R2 define tunnel-barriers to QD1 and QD2 which are formed in the channel between source and drain/reservoir electrodes. The device can be formed in patterned semiconductor materials or semiconductor heterostructures.

EXAMPLE 7

(33) FIG. 7 illustrates a further example of an electrostatically defined quantum memristive device. Devices of this type are defined by tunnel barriers which are electrostatically induced by gate electrodes. In the embodiment shown, QDs are formed in a two-dimensional electron/hole gas. Barrier gates BG L1, BG L2, BG R1 and BG R2, and plunger gates PG1 and PG2 define QD1 and QD2 in a two-dimensional electron gas (2DEG). Electrode gates EG L and EG R form the barrier between the drain and reservoir electrode. The device can be formed in patterned semiconductor materials or semiconductor heterostructures.

EXAMPLE 8

(34) FIG. 8 illustrates a quantum memristive device according to the invention in which the QDs are formed by individual atoms, molecules or nanoparticles. Atoms can be placed using ion-implantation or STM lithography. Molecules and nanoparticles can be anchored to the source, drain and reservoir electrode using linker groups.

EXAMPLE 9

(35) Devices according to the invention were fabricated and an example of such a device is shown in FIG. 1(b). This device employed a capacitively coupled pair of silicon metal-oxide-semiconductor (MOS) quantum dots. The two terminals of the memristive system were electrodes L and R, which were formed beneath aluminium accumulation gates LA.sub.1 and LA.sub.2. These terminals were coupled to the quantum dot QD1 with tunneling strengths that were determined by the depletion gates LD.sub.1 and RD.sub.1.

(36) In this device the energy gap in electrode-B was zero. To form QD2, both depletion gates LD.sub.2 and RD.sub.2 were lowered to 0.1 V, forming high tunnel barriers. Since direct transport through QD2 cannot be measured with such high barriers, the hysteresis in the QD1 current was used to estimate the tunnel rate at 10 Hz. In this gate range, it was observed that LD.sub.2 was able to modulate the tunnel rate, whereas RD.sub.2 was not. From this it was concluded that QD.sub.2 was formed closer to the left side and tunneling from the right lead was absent (hence electrode-B is indicated to the left of QD2 in FIG. 1(b)). To control the QD2 level E.sub.2 during the AC voltage sweep, gate LD.sub.2 was also used, since it was strongly coupled to the dot. While LD.sub.2 was used for both the AC sweep and for tuning the tunnel rate .sub.2, it was noted that the tunnel rate was practically insensitive to LD.sub.2 over the AC sweep range of millivolts. It is important to note that in this particular experimental embodiment, a voltage divider was used to increase the magnitude of the AC voltage on LD.sub.2 by a factor of 10 compared to electrode-L. That is, a 10 mV AC signal was applied to LD.sub.2 but was reduced to V.sub.A=1 mV on electrode-L by the divider. This was because the lever arm between LD.sub.2 and QD2 was of the order of 0.2, but the hysteresis effect is more evident when the potential felt by both dots is comparable.

(37) These devices were fabricated using undoped silicon with a thermal oxide of 300 nm, which was etched down to a thickness of 12 nm in the area where the dots were patterned. Ion implantation of phosphorus with an energy of 12 keV was performed through a photomask to create degenerately doped source/drain contacts. Following implantation, the resist mask was stripped, and the chip was annealed at 950 C. in N.sub.2 to remove damage from the implantation process, and to activate the dopants. To prevent shorts between these ion implanted regions and subsequent metal gates, a 6 nm layer of Al.sub.2O.sub.3 was deposited by atomic layer deposition. Gates to define the quantum dots were then fabricated on the substrate using three layers of Al gates. Each layer was patterned using electron beam lithography with a PMMA mask, and Al deposited using an electron beam evaporator with a deposition rate of 1 /s. Following liftoff of the excess metal, the devices were exposed to a 25 W O.sub.2 plasma at 150 C. for two minutes to form an oxide layer at the metal surface. This oxide provided electrical insulation between gate layers, and it was found that this process resulted in gate-gate breakdown voltage greater than 4 V. The first gate layer was a screening layer which controlled where subsequent gates would form an accumulation layer at the Si/SiO.sub.2 interface. The screening gates defined two horizontal channels with a separation of 140 nm. Layer two were the accumulation gates used to form the conducting channel between the dots and the source/drain contacts, as well as the plunger gates which controlled the chemical potentials of the dots. A further layer was deposited last and was used to form tunnel barriers. After all gate layers were deposited, the chip was annealed in forming gas at 220 C. for 1 hour, which was found to be critical for obtaining clean and reproducible device characteristics in this particular embodiment.

(38) Measurements of device performance were performed. These measurements were carried out in a dilution refrigerator with a lattice temperature of 25 mK. DC voltages were applied to the device using a multi-channel custom voltage source based on the Texas Instruments 1220 20-bit digital to analog converter. To form dots, the screening gates were grounded, a voltage of 2.8 V was applied to the accumulation gates (L/RA.sub.1/2), and the plunger gates (P.sub.1/2) were set to 2:1 V. For QD1, the depletion gates (L/RD.sub.1) were set to 0.8 V to realize relatively low tunnel barriers and a device current on the order of 100 pA. In contrast, the tunnel barriers for QD2 were made larger by applying a voltage of 0.1 V, giving a tunnel rate 10 Hz for QD2 to the left electrode and no tunneling to the right electrode, as described in the text. The plunger gates P.sub.1/2 were then tuned on the mV scale to modulate the chemical potentials of the dots relative to the source and drain electrodes. For QD1, an attempt was made to align the chemical potential to the electrodes by maximizing the observed DC current at a finite bias. To measure the current hysteresis, a sinusoidal AC voltage with a frequency of 1 Hz was applied to the source of QD1 (L) and one of the depletion gates of QD2 (LD.sub.2). AC and DC voltages were applied simultaneously to LD2 using a custom-built voltage adder based on an AD797B ultralow-noise operational amplifier. The circuit bandwidth was 2 Hz due to RC filters on the lines connecting the external sources to the device, which limited the frequency of the applied voltage to <2 Hz. The 10 mV AC signal was applied directly to LD.sub.2, but reduced by a factor of 10 using a voltage divider before being applied to L. The current through QD1 was amplified using a DL Instruments 1211 current-voltage preamplifier and then input to a Tektronix DPO 7104 oscilloscope. The oscilloscope recorded traces of length 10 s, with a sampling rate of 1 kS/s.

(39) FIG. 9 shows simulated and experimental I-V curves showing current hysteresis in this Si double dot system. FIG. 9(a) shows a simulated I-V curve of QD1 for one sinusoidal voltage cycle with V.sub.A=1 mV. The suppression of current near zero bias is due to a weak, unintentional potential barrier in series with QD1. The arrows relate the curves to the voltage sweep direction. |0.sub.2 and |1.sub.2 indicate the charge state of QD2. FIGS. 9(b-d) show the measured current through QD1 for one voltage cycle with =21 Hz. FIG. 9(b) shows the measured two-looped hysteresis showing similar behavior as in FIG. 9(a). FIG. 9(c) shows that the position of the hysteresis was shifted to negative bias by lowering V.sub.P2 which changed the energy level E.sub.2 in QD2._V.sub.P2 denotes the difference in voltage applied to V.sub.P2, relative to when the hysteresis was symmetric about zero bias. FIG. 9(d) shows that raising the DC voltage on LD.sub.2 lowered the tunnel barrier and increased .sub.2, causing the hysteresis width to narrow. The estimated tunnel rates .sub.2 for FIGS. 9(c) and 9(d) were 8 Hz and 33 Hz, respectively.

(40) FIG. 9 shows the I-V responses for a single voltage cycle (in contrast to the average current presented in FIG. 2 that would correspond to an average over many cycles). For all results shown in FIG. 9, a sweep rate of w=21 Hz and sweep amplitude V.sub.A=1 mV were used, and the current through QD1 is displayed. FIG. 9(b) shows hysteresis that is symmetrical about V=0, indicating that energy E.sub.2 of QD2 was aligned with p at zero bias. FIG. 9(a) is a simulated trace using Equations (7) and (8) with instantaneous switching of the charge state of QD2 chosen to match the data in FIG. 9(b). For a single cycle, sharp jumps in current occur when the charge state of QD2 changes. While these jumps are perfectly sharp in simulation (FIG. 9(a)), they were slightly rounded in the experiment (FIGS. 9(b)(c)(d)) due to the limited bandwidth of the RC filtering employed in the experimental circuit.

(41) Tuning the DC voltages applied to QD2 varied the hysteresis shape in two distinct ways. The plunger gate P.sub.2 controlled the value of E.sub.2. This changed the position of the dot level relative to .sub.B so that a different value of .sub.L was required to change the charge state of QD2. The position of the hysteresis loop was thus shifted along the I-V curve, as shown in FIG. 9(c). This confirmed that the current jumps in the current of QD1 were due to charge transitions on QD2. If QD2 is detuned far enough, the voltage V would no longer be sufficient to cause the dot level to cross .sub.B and no hysteresis would be observed.

(42) Current was suppressed at low bias due to a weak unintentional barrier in series with QD1. This device imperfection was included in the model by considering the dot and tunnel barrier as two voltage dependent resistors in series. The I-V curve was calculated from the total resistance, which changed as a function of V depending on how the voltage was dropped across the two resistors. The resistance of the dot R.sub.d(V.sub.d) was calculated from Equations (7) and (8) using R=1/G. For the tunnel barrier, resistance R.sub.b(V.sub.b) was calculated for transmission through a square barrier with a height of 0.3 meV and a width of 40 nm (which were the best fit parameters). V.sub.d and V.sub.b (the voltages dropped across the dot and barrier, respectively), were related to the bias voltage by V=V.sub.d+V.sub.b. Comparison of FIGS. 9(a) and 9(b) showed that this model reproduced the experimental data well. If the effect of the tunnel barrier resistance is removed and the I-V response of the double dot system is plotted instead, a curve similar to FIG. 2B(a) was obtained, but with stochastic jumps rather than an average current.

(43) As electrode-B did not have an energy gap in this device, it was required that the tunneling rate .sub.2 must be in the correct frequency range in order to observe the memristive hysteresis effect, i.e. roughly comparable to sweep rate . The width of the hysteresis loop was modulated by adjusting .sub.2, using the DC voltage on the depletion gate LD.sub.2. This can be seen in FIGS. 9(c) and 9(d), where a more positive voltage in (d) increased the tunneling rate and the charge transitions occurred closer together. If the tunnel rate were further increased the hysteresis would eventually disappear. The rate .sub.2 can be estimated for a given I-V curve as the ratio of the average voltage sweep rate to the distance between the two charge transitions: .sub.2=2V.sub.a/(V.sub.hyst), where V.sub.hyst is the hysteresis width. For the curves in FIGS. 9(c)(d), tunneling rates of 8 Hz and 33 Hz were estimated, respectively.

EXAMPLE 10

(44) As described in Example 9, a device imperfection led to a small tunnel barrier in series with QD1. To properly match the experimental results it was necessary to calculate the barrier resistance as a function of the voltage across it. The resistance was found using Ohm's law: R.sub.b(V.sub.b)=M.sub.b, where R.sub.b is the resistance, I.sub.b is the current, and V.sub.b is the voltage. Current was calculated using the equation for transport between two thermally populated reservoirs:

(45) $I_b=\frac{.Math.e.Math.}{h}{}_{-}^{}D\left(E\right).Math.f\left(E-\frac{V_b}{2}\right)-f\left(E+\frac{V_b}{2}\right).Math.\mathrm{dE}$
where E is the energy and D(E) is the transmission coefficient. For simplicity, current was calculated for a square barrier, which has a transmission coefficient of:

(46) $D\left(E\right)=\exp \left(-\frac{4s}{h}\sqrt{2m^{*}\left(-E\right)}\right)$
where s is the width of the barrier, m* is the effective mass of the electron in Si, and is the height of the barrier in eV. The best match to the experimental data was found for s=40 nm and =0.3 meV.