METHOD AND DEVICE FOR ATTENUATING OSCILLATIONS ON BUS LINES OF A BUS SYSTEM BASED ON DIFFERENTIAL VOLTAGE SIGNALS

Abstract

An attenuating device for a bus of a controller area network bus system based on differential voltage signals. The bus has first and second bus lines, having an attenuating circuit that provides a variable electrical resistance value between the first and second bus lines and that is operable in at least three circuit states. In a first circuit state, the first and second bus lines are connected via an attenuating resistor having a first resistance value. In a second circuit state, the first and second bus lines are connected via an attenuating resistor having a second resistance value. In a third circuit state, the first and second bus lines are connected via an attenuating resistor having a third resistance value. The first resistance value is lower than the second resistance value. The second resistance value is lower than the third resistance value.

Claims

1-17. (canceled)

18. An attenuation device for a controller area network bus of a bus system based on differential voltage signals, the bus including a first bus line and a second bus line, the attenuation device comprising: an attenuating circuit that provides a variable electrical resistance value between the first bus line and the second bus line and that is operable in at least three circuit states, wherein in a first circuit state, the first bus line and the second bus line are connected by an attenuation resistor having a first resistance value, in a second circuit state the first bus line and the second bus line are connected by an attenuation resistor having a second resistance value, and in a third circuit state the first bus line and the second bus line are connected by an attenuation resistor having a third resistance value, wherein the first resistance value is less than the second resistance value, and the second resistance value is less than the third resistance value.

19. The attenuation device of claim 18, wherein the second resistance value increases with time.

20. The attenuation device of claim 18, wherein the attenuation resistor having the first resistance value and/or the attenuation resistor having the second resistance value and/or the attenuation resistor having the third resistance value is implemented as a circuit including at least one semiconductor switch.

21. The attenuation device according to claim 18, further comprising: a control circuit having at least one control terminal that switches the attenuating circuit back and forth between the circuit states according to control signals on the at least one control terminal.

22. The attenuation device according to claim 21, further comprising a first field effect transistor (FET) having a predetermined gate source capacitance, a second FET having a predetermined gate source capacitance and a resistor element having a predetermined resistance value, wherein a drain terminal of the first FET is connected to a terminal for the first bus line and a drain terminal of the second FET is connected to a terminal for the second bus line, wherein a source terminal of the first FET and a source terminal of the second FET are connected to a common source terminal point, wherein a gate terminal of the first FET and a gate terminal of the second FET are connected to a common gate terminal point, and wherein the resistor element is connected to the source terminal point and the common gate terminal point.

23. The attenuation device of claim 22, wherein the control circuit is connected to the common gate terminal point and the source terminal point of the attenuating circuit and includes a voltage terminal and a reference potential terminal; wherein the control circuit is adapted to do as follows when a voltage is applied to the voltage terminal and a reference potential is applied to the reference potential terminal: connect the source terminal point to the voltage terminal and connect the common gate terminal point to the reference potential terminal when at least one voltage that signals the first circuit state is applied to the at least one control terminal; switch the source terminal point and the common gate terminal point open in the control circuit when at least one voltage that signals the second circuit state is applied to the at least one control terminal; make a low-resistance connection between the source terminal point and the common gate terminal point when at least one voltage that signals the third circuit state is applied to the at least one control terminal.

24. The attenuation device of claim 23, wherein the at least one control terminal includes a first control terminal and a second control terminal, wherein the first circuit state is signaled by a high level voltage signal applied to the first control terminal and a voltage signal is not applied to the second control terminal; wherein the second circuit state is signaled when no voltage signals are applied to the first control terminal and the second control terminal; and wherein the third circuit state is signaled when a high-level voltage signal is applied to the second control terminal and a voltage signal is not applied to the first control terminal.

25. The attenuation device according to claim 25, wherein the control circuit includes first switching elements that are adapted to switch a connection between the voltage terminal and the source terminal point and a connection between the reference potential terminal and the gate terminal point to a conductive state when a high-level voltage signal is applied to the first control terminal, and to switch said connections to a non-conductive state when no voltage signal is applied to the first control terminal; wherein the first switching elements include a third FET and a fourth FET, wherein gate terminals of the third FET and the fourth FET are connected to the first control terminal; wherein a source terminal of the third FET is connected to the voltage terminal and a drain terminal of the third FET is connected to the source terminal point, and a source terminal of the fourth FET is connected to the reference potential terminal and a drain terminal of the fourth FET is connected to the gate terminal point.

26. The attenuation device according to claim 24, wherein the control circuit includes second switching elements adapted to switch a connection between the source terminal point and the gate terminal point to a conductive state when a high-level voltage signal is applied to the second control terminal, and to switch said connections to a non-conductive state when a voltage signal is not applied to the second control terminal; wherein the second switching elements include fifth and sixth FETs connected in series, wherein gate terminals of the fifth and sixth FETs are connected to the second control terminal; wherein a source terminal of the fifth FET is connected to a source terminal of the sixth FET, and a drain terminal of the fifth FET is connected to the source terminal point and a drain terminal of the sixth FET is connected to the gate terminal point.

27. A method for attenuating oscillations on bus lines of a controller area network bus system based on differential voltage signals, using an attenuation device, the attenuation device including: an attenuating circuit that provides a variable electrical resistance value between a first bus line of the bus and a second bus line of the bus, and that is operable in at least three circuit states, wherein in a first circuit state, the first bus line and the second bus line are connected by an attenuation resistor having a first resistance value, in a second circuit state the first bus line and the second bus line are connected by an attenuation resistor having a second resistance value, and in a third circuit state the first bus line and the second bus line are connected by an attenuation resistor having a third resistance value, wherein the first resistance value is less than the second resistance value, and the second resistance value is less than the third resistance value; wherein the method comprises: detecting an edge in a differential voltage signal; when the edge is detected, providing at least one voltage to the at least one control terminal, wherein: in a first time period, the at least one voltage is provided corresponding to the first circuit state, in a second time period that follows the first time period, the at least one voltage is provided corresponding to the second circuit state, and in a third time period that is outside of the first and the second time period, the at least one voltage is provided corresponding to the third circuit state.

28. The method of claim 27, wherein the edge is a falling edge of the differential voltage signal.

29. The method according to claim 27, wherein the attenuating circuit further includes a control circuit having at least one control terminal that switches the attenuating circuit back and forth between the circuit states according to control signals on the at least one control terminal, wherein the control circuit is connected to the common gate terminal point and the source terminal point of the attenuating circuit and includes a voltage terminal and a reference potential terminal; wherein the attenuation device further includes; a first field effect transistor (FET) having a predetermined gate source capacitance, a second FET having a predetermined gate source capacitance and a resistor element having a predetermined resistance value, wherein a drain terminal of the first FET is connected to a terminal for the first bus line and a drain terminal of the second FET is connected to a terminal for the second bus line, wherein a source terminal of the first FET and a source terminal of the second FET are connected to a common source terminal point, wherein a gate terminal of the first FET and a gate terminal of the second FET are connected to a common gate terminal point, and wherein the resistor element is connected to the source terminal point and the common gate terminal point; wherein the control circuit is adapted to do as follows when a voltage is applied to the voltage terminal and a reference potential is applied to the reference potential terminal: connect the source terminal point to the voltage terminal and connect the common gate terminal point to the reference potential terminal when at least one voltage that signals the first circuit state is applied to the at least one control terminal; switch the source terminal point and the common gate terminal point open in the control circuit when at least one voltage that signals the second circuit state is applied to the at least one control terminal; make a low-resistance connection between the source terminal point and the common gate terminal point when at least one voltage that signals the third circuit state is applied to the at least one control terminal, wherein the at least one control terminal includes a first control terminal and a second control terminal, wherein the first circuit state is signaled by a high level voltage signal applied to the first control terminal and a voltage signal is not applied to the second control terminal; wherein the second circuit state is signaled when no voltage signals are applied to the first control terminal and the second control terminal; and wherein the third circuit state is signaled when a high-level voltage signal is applied to the second control terminal and a voltage signal is not applied to the first control terminal; and wherein, when the edge is detected, in the first period of time, a high-level voltage signal is provided at the first control terminal and a voltage signal is not provided at the second control terminal, in a second period of time, no voltage signals are provided at the first and at the second control terminal, and in the third period of time, no voltage signal is provided at the first control terminal and a high-level voltage signal is provided at the second control terminal.

30. The method according to claim 27, further comprising providing a voltage to the voltage terminal and a reference potential to the reference potential terminal.

31. A control apparatus for an attenuation device for a controller area network bus of a bus system based on differential voltage signals, the bus including a first bus line and a second bus line, the attenuation device including: an attenuating circuit that provides a variable electrical resistance value between the first bus line and the second bus line and that is operable in at least three circuit states, wherein in a first circuit state, the first bus line and the second bus line are connected by an attenuation resistor having a first resistance value, in a second circuit state the first bus line and the second bus line are connected by an attenuation resistor having a second resistance value, and in a third circuit state the first bus line and the second bus line are connected by an attenuation resistor having a third resistance value, wherein the first resistance value is less than the second resistance value, and the second resistance value is less than the third resistance value; and a control circuit having at least one control terminal that switches the attenuating circuit back and forth between the circuit states according to control signals on the at least one control terminal; the control apparatus comprising: terminal elements for connecting to the first and the second bus lines and at least one output, for connecting to the at least one control terminal, and that is configured to: detect an edge in a differential voltage signal; when the edge is detected, provide at least one voltage to the at least one control terminal, wherein: in a first time period, the at least one voltage is provided corresponding to the first circuit state, and in a second time period that follows the first time period, the at least one voltage is provided corresponding to the second circuit state; wherein the edge is a falling edge of the differential voltage signal.

32. An attenuation apparatus comprising a plurality of attenuation devices, each of the attenuation devices being configured for a controller area network bus of a bus system based on differential voltage signals, the bus including a first bus line and a second bus line, each of the attenuation devices including: an attenuating circuit that provides a variable electrical resistance value between the first bus line and the second bus line and that is operable in at least three circuit states, wherein in a first circuit state, the first bus line and the second bus line are connected by an attenuation resistor having a first resistance value, in a second circuit state the first bus line and the second bus line are connected by an attenuation resistor having a second resistance value, and in a third circuit state the first bus line and the second bus line are connected by an attenuation resistor having a third resistance value, wherein the first resistance value is less than the second resistance value, and the second resistance value is less than the third resistance value; wherein the attenuation devices are connected in parallel on the first and second bus lines.

33. The attenuation apparatus of claim 31, wherein the attenuating circuit further includes a control circuit having at least one control terminal that switches the attenuating circuit back and forth between the circuit states according to control signals on the at least one control terminal, wherein the control circuit is connected to the common gate terminal point and the source terminal point of the attenuating circuit and includes a voltage terminal and a reference potential terminal; wherein each of the attenuation devices further includes; a first field effect transistor (FET) having a predetermined gate source capacitance, a second FET having a predetermined gate source capacitance and a resistor element having a predetermined resistance value, wherein a drain terminal of the first FET is connected to a terminal for the first bus line and a drain terminal of the second FET is connected to a terminal for the second bus line, wherein a source terminal of the first FET and a source terminal of the second FET are connected to a common source terminal point, wherein a gate terminal of the first FET and a gate terminal of the second FET are connected to a common gate terminal point, and wherein the resistor element is connected to the source terminal point and the common gate terminal point; wherein the control circuit is adapted to do as follows when a voltage is applied to the voltage terminal and a reference potential is applied to the reference potential terminal: connect the source terminal point to the voltage terminal and connect the common gate terminal point to the reference potential terminal when at least one voltage that signals the first circuit state is applied to the at least one control terminal; switch the source terminal point and the common gate terminal point open in the control circuit when at least one voltage that signals the second circuit state is applied to the at least one control terminal; make a low-resistance connection between the source terminal point and the common gate terminal point when at least one voltage that signals the third circuit state is applied to the at least one control terminal, wherein the predetermined gate source capacitance and/or the predetermined resistance value of different ones of the attenuation devices have different values.

34. The attenuation apparatus according to claim 22, further comprising a plurality of control apparatuses including, each including: terminal elements for connecting to the first and the second bus lines and at least one output, for connecting to the at least one control terminal, and that is configured to: detect an edge in a differential voltage signal; when the edge is detected, provide at least one voltage to the at least one control terminal, wherein: in a first time period, the at least one voltage is provided corresponding to the first circuit state, and in a second time period that follows the first time period, the at least one voltage is provided corresponding to the second circuit state; wherein the edge is a falling edge of the differential voltage signal wherein each of the control apparatus is connected to one of the plurality of attenuation devices, wherein the first and/or second predetermined time period of at least two different control apparatuses is different for each of the control apparatuses.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0032] FIG. 1 shows the schematic construction of a bus system according to an example embodiment of the present invention.

[0033] FIG. 2 shows a block diagram with an attenuation device connected to bus lines.

[0034] FIG. 3 shows the circuit diagram of an attenuating device according to a preferred example embodiment of the present invention.

[0035] FIGS. 4A-4C show the effect of an attenuating device, according to an example embodiment of the present invention, on the differential voltage and the resistance between the bus lines.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

[0036] FIG. 1 shows the structure of a bus system 2 based on differential voltage signals, in particular a CAN bus system. Bus system 2 comprises a plurality of bus subscribers 4_1, 4_2, . . . , 4_m connected to two bus lines 6, 8 of a bus 10 of the bus system and communicating with each other over the bus lines. For this purpose, the bus subscribers use differential voltages between the two bus lines that are generated and read by means of transceivers. In the figure, one of the bus subscribers 4_1, more precisely its transceiver 12, comprises an attenuating device 30 according to the present invention; in general several or all of the bus subscribers can comprise such an attenuating device 30. The bus lines 6, 8 are connected to each other by terminating resistors 14a, 14b, which represent the central impedance of the bus system.

[0037] FIG. 2 is a block diagram showing a simplified representation of an inventive attenuating device 30 connected to the bus lines 6, 8. The attenuating device 30 comprises connections 32, 34 to a first bus line 6 and to a second bus line 8, respectively. In the CAN bus, the first bus line 6 corresponds to CAN_H and the second bus line 8 corresponds to CAN_L. As further connections, the attenuating device comprises control terminals 36, 38, by which the function of the attenuating device is controlled, a voltage terminal 40 and a reference potential terminal 42, for connecting to a reference potential, in particular to ground or earth. The voltage terminal 40 is connected to an (ideal) voltage source 16 that provides a constant voltage and is also connected to the bus lines by resistors 18. In the case of a CAN bus, the voltage supplied by the voltage source is nominally 2.5 V, and is the voltage applied to both bus lines in the recessive state (when no bus user generates a difference voltage) or the common mode voltage (i.e., the average value of the two voltages on the first and second bus lines) in the dominant state, respectively.

[0038] FIG. 2 also shows a control apparatus 20 connected to the two bus lines 6, 8 and to the two control terminals 36, 38 of the attenuating device 30 and that is adapted to control the attenuating device 30 by providing suitable voltage signals to the control terminals 36, 38 of the attenuating device 30. The control apparatus 20 is adapted to detect an edge in the differential voltage signal on the bus lines, in particular, a falling edge is to be detected, i.e. an edge that occurs when transitioning from the state in which a voltage difference exists to the state in which no voltage difference exists. On the CAN bus, the control apparatus is thus adapted to detect the edge in the differential voltage signal on the transition from the dominant to the recessive state. The control apparatus 30 is further adapted to provide control voltages for the attenuating device 30 at corresponding outputs 22, 24 that are to be connected to the two control terminals 36, 38 of the attenuating device 30. Voltages corresponding to three different configurations and states are in this case applied to the outputs 22, 24. Voltages corresponding to a first state are applied during a first phase extending over a first time period directly after detecting a falling edge, voltages corresponding to a second state are applied during a second phase extending over a second period of time following the first time period, and voltages corresponding to a third state are applied during the remaining time, i.e., outside of the first and the second time period. The third state signals that the attenuating effect of the attenuation device is to be switched off.

[0039] FIG. 3 shows a preferred embodiment of an inventive attenuating device 30. The attenuating device includes an attenuating circuit 44 and a control circuit 46.

[0040] The attenuating circuit 44 includes a first terminal 32 for a first bus line 6 of the bus and a second terminal 34 for a second bus line 8 of the bus. The attenuating circuit 44 further comprises a resistor element 48, hereinafter also referred to as a resistor 48, a first field effect transistor (FET) 50, and a second field effect transistor 52. Preferably, the two field effect transistors (FETs) 50, 52 are metal oxide field effect transistors (MOSFETs), further preferably p channel MOSFETs of the enrichment type (i.e., normally off). These elements are connected to each other by means of lines such that source terminals of the first and second FETs 50, 52 are connected to a source terminal point 54, gate terminals of first and second FETs 50, 52 are connected to a gate terminal point 56, the source terminal point 54 is connected to the gate terminal point 56 by the resistor 48, the drain terminal of the first FET 50 is connected to the first terminal 32 and the drain terminal of the second FET 52 is connected to the second terminal 34. The first and second FETs 50, 52 each have a predetermined gate source capacitance. Bulk drain diodes 68, 70 of the first and second FETs 50, 52 are also shown for the sake of completeness.

[0041] The control circuit 46 comprises a voltage terminal 40, a reference potential terminal 42, and a first and second control terminal 36, 38. The control circuit 46 comprises a third and a fourth FET 58, 60, the gate terminals of which are connected to the first control terminal 36 and which are preferably MOSFETs, further preferably n-channel MOSFETs of the enrichment type (i.e., normally off). The third and fourth FETs represent first switching elements. The third FET 58 is arranged to switch a connection from the voltage terminal 40 to the source terminal point 54 back and forth between a conductive and a non-conductive state. The fourth FET 60 is arranged to switch a connection from the reference potential terminal 42 to the gate terminal point 56 back and forth between a conductive and a non-conductive state. More specifically, the source terminal of the third FET 58 is connected to the voltage terminal 40 and the drain terminal of the third FET 58 is connected to the source terminal point 54, and the source terminal of the fourth FET 60 is connected to the reference potential terminal 42 and the drain terminal of the fourth FET 60 is connected to the gate terminal point 56. Thus, when a high-level voltage is applied to the first control terminal 36, the third and fourth FETs 58, 60 are switched on. High-level voltage is to be understood herein to be sufficiently high relative to voltages on voltage terminal 40 and on reference potential terminal 42 to switch on the third and fourth FETs 58, 60. The expressions “switched on” or “switched through” are to be understood as indicating that the FET is operated in the saturation range.

[0042] Further, the control circuit 46 comprises fifth and sixth FETs 62, 64, the gate terminals of which are connected to the second control terminal 38 and which are preferably MOSFETs, further preferably n-channel MOSFETs of the enrichment type (i.e., normally off). The fifth and sixth FETs represent second switching elements. The fifth and sixth FETs 62, 64 are arranged in series such that a connection between the source terminal point 54 and the gate terminal point 56 can be switched between a conductive and a non-conductive state. Thus, when a high-level voltage is applied to the second control terminal 38, the fifth and sixth FETs 62, 64 control through. More specifically, the drain terminal of the fifth FET 62 is connected to the source terminal point 54, the drain terminal of the sixth FET 64 is connected to the gate terminal point 56, and the source terminals of the fifth and sixth FETs 62, 64 are connected to each other. The bulk drain diodes 72, 74 of the fifth and sixth FETs 62, 64 are again shown for the sake of completeness. It should be emphasized, however, that any controllable short-circuit can be used at this point.

[0043] All FETs, i.e. the first to sixth FETs, are preferably adapted or embodied as high-voltage transistors according to maximum rated voltages of the bus, or from −27 V to +40 V on the CAN bus, e.g. CAN_H, CAN_L.

[0044] By referencing the configurations or states of the control voltages introduced above, the following describes the operating principles of the attenuating circuit shown in FIG. 3, wherein it is implied that voltage terminal 40 is connected to a suitable voltage source that provides a voltage preferably corresponding to the common mode voltage of the two bus lines and that the reference potential terminal 42 is connected to a suitable reference potential, in particular a ground potential.

[0045] First state (or first phase): When a high-level voltage signal is applied to the first control terminal 36 and no voltage is applied to the second control terminal 38, the third and fourth FETs 58, 60 are switched on such that the source terminal point 54 is brought to the potential applied to the voltage terminal 40, and the gate terminal point 56 is brought to the potential at the reference potential point 42 (which are given according to the aforementioned condition). At the same time, the fifth and sixth FETs 62, 64 are latched. This results in a gate source voltage being applied to the first and second FETs 50, 52, respectively, so that the two FETs 50, 52 are switched through, i.e. have only a very low or no resistance over the drain source paths. Accordingly, the two bus lines 6, 8 are short-circuited by the FETs connected in series, wherein the short-circuit resistor forming the attenuation resistor is determined by the sizing of the first and second FETs 50, 52. Oscillations are strongly attenuated, i.e., the ringing is suppressed by the low resistance between the bus lines.

[0046] Second state (or second phase): When voltages are not applied on the first control terminal 36 and the second control terminal 38, the drain source paths of the third, fourth, fifth and sixth FETs 58, 60, 62, 64 are non-conductive. There is then no conductive connection made by control circuit 46 between source terminal point 54 and gate terminal point 56, and they are also disconnected from the voltage terminal 40 and reference potential terminal 42 (and due to circuit layout, are disconnected from control terminals 36, 38), i.e., the source terminal point 54 and gate terminal point 56 are open in control circuit 46. The charges of the capacitors formed by the gate source capacitances of the first and second FETs 50, 52 are then discharged over the resistor 48 such that the voltage between the gate terminal point 56 and the source terminal point 54 decreases. Due to the decreasing gate source voltage at the first and second FETs 50, 52, the latter are no longer in the saturation range but in the linear or ohmic range, so that the drain source paths determining the attenuation resistance between the bus lines have a resistance dependent on the gate source voltage. Accordingly, the time characteristic of the resulting attenuation resistance is determined by the RC time constant resulting from the values C of the gate source capacitances of the first and second FETs 50, 52 and the value R of the resistance 48.

[0047] Third state (or third phase): When voltage is not applied to the first control terminal 36 and a high-level voltage signal is applied to the second control terminal 38, the fifth and sixth FETs 62, 64 are switched through, wherein the third and fourth FETs 58, 60 are at the same time latched. This results in the source terminal point 54 and the gate terminal point 56 being connected with low or no resistance. This connection has a low resistance connection in the sense that the resistance of this connection is small compared to the resistance value of the resistor 48; the charges at the gate source capacitances of the first and second FETs 50, 52 thus discharge over this connection such that the first and second FETs 50, 52 are latched. The bus lines are thus only connected at high resistance over the attenuating device, i.e. with high resistance or non-conducting.

[0048] Obviously, a high-level voltage signal should not be applied to the first and second control terminals 36, 38 at the same time, since the voltage terminal 40 would then be directly connected to the reference potential terminal 42. A control apparatus 20 should be adapted accordingly.

[0049] FIGS. 4A-4C illustrate the effect of an inventive attenuating circuit. FIG. 4A firstly shows the behavior when no attenuating circuit is used, wherein the difference voltage V.sub.diff between the bus lines is plotted over time t. Both the ideal curve 82 and the real curve 84 of the differential stress are plotted in the figure. The ideal curve 82 follows a stepwise course in which the differential voltage transitions from a positive value (e.g. 2 V in the CAN bus) to a value of 0 V. The real curve 84, on the other hand, has oscillations (ringing) generated at the edge of the ideal curve that are attenuated to a negligible value only after a few oscillation periods.

[0050] FIG. 4B shows the attenuated curve 86, i.e., the curve of the real differential voltage signal when an attenuation circuit is used. Here, the oscillation is substantially attenuated to relatively small amplitudes after only one oscillation period. For a receiver on the bus, the state of 0 V is therefore already unambiguously distinguishable much earlier.

[0051] FIG. 4C shows the curve 90 of the resistance adjusted by the attenuation circuit (according to the present invention) between the two bus lines, wherein only the basic curve, i.e. whether the resistance in a phase is greater than or less than in another, is outlined and no information can be read from the figure about the absolute magnitude. Likewise, the resistances may not be constant during a phase; this is particularly the case during the second phase, in which the first and second transistors act as voltage-controlled resistors and the gate source voltage decreases according to the RC time constant defined by the gate source capacitances and the resistor element. During the first phase 92 (first state or time period, i.e. first and second transistor are switched on), the bus lines are connected to one another or short-circuited by a very low resistance of the attenuating circuit, thus greatly attenuating the oscillations (because the resistance R also results in a correspondingly small time constant RC). During the second phase 94 (second state or time period, i.e. the first and second transistors act as voltage-controlled resistors), the resistance is increased by the attenuating circuit, so that weaker bus subscribers can also generate a differential voltage on the bus, wherein the resistance is at the same time still small enough to further attenuate the oscillation. In the further course or during the third phase 96 (third state or time period, i.e., first and second transistors are latched), the bus lines are no longer connected to each other by the attenuating circuit, or only connected at a very high resistance. The first to third phase corresponds to the first to third state of the control voltages introduced above.