METHOD FOR STRUCTURING AN INSULATING LAYER ON A SEMICONDUCTOR WAFER

Abstract

A method for structuring an insulating layer on a semiconductor wafer includes providing a semiconductor wafer with a top, a bottom and includes multiple solar cell stacks, wherein each solar cell stack is a Ge substrate, which forms the bottom of the semiconductor wafer, a Ge subcell and at least two III-V subcells, in the above order, and at least one passage opening, which extends from the top to the bottom of the semiconductor wafer and has a connected side wall, an insulating layer two-dimensionally deposited on the top of the semiconductor wafer, on the side wall of the passage opening and/or on the bottom of the semiconductor wafer, and the deposition of an etch-resistant filling material by means of a printing process on an area of the top which include the passage opening, and into the passage opening.

Claims

1. A method of patterning an insulating layer on a semiconductor wafer having a through hole on a semiconductor wafer, the method comprising: providing a semiconductor wafer having a top side, a bottom side, and at least one through-opening extending from the top side to the bottom side of the semiconductor wafer, the at least one through-opening having a continuous side wall; applying an insulation layer applied over a surface on the top side of the semiconductor wafer and over the continuous side wall of the at least one through opening; and applying an etch-resistant filling material via a pressure process to a region of the top side comprising the at least one through opening and into the at least one through opening.

2. The method according to claim 1, wherein the semiconductor wafer comprises at least two solar cell stacks.

3. The method according to claim 1, wherein the bottom side of the semiconductor wafer is formed by a Ge substrate.

4. The method according to claim 2, wherein each solar cell stack has a Ge subcell and at least two III-V subcells in the order mentioned.

5. The method according to claim 1, wherein the insulating layer applied to the semiconductor wafer, the side wall of the through opening and/or the bottom side of the semiconductor wafer.

6. The method according to claim 1, wherein the insulation layer is removed in areas not covered by the etch-resistant filling material via a wet chemical etching process or via an RIE (reactive ion etching) etching process.

7. The method according to claim 1, wherein the insulating layer is removed in all areas not printed with the etch-resistant filling material on the top side and/or on the bottom side of the semiconductor wafer.

8. The method according to claim 1, wherein the etch-resistant filling material is applied to the semiconductor wafer exclusively in regions comprising the at least one through-opening.

9. The method according to claim 1, wherein a diameter of the at least one through-opening decreases from the top side towards the bottom side.

10. The method according to claim 1, wherein the through-opening has at least one step.

11. The method according to claim 1, wherein a step is formed on the top side of the semiconductor wafer at an interface between the metal structure and a top side of an uppermost III-V subcell.

12. The method according to claim 11, wherein exactly two completely circumferential steps are formed, wherein a first step is formed at an interface between a Ge subcell and an overlying III-V subcells, and a second step is formed between the Ge subcell and a Ge substrate.

13. The method according to claim 1, wherein a part of the insulation layer is formed on a metal structure, the metal structure being formed exclusively formed on the top side of the semiconductor wafer.

14. The method according to claim 13, wherein the through-opening is completely enclosed by a two-dimensional region of the metal structure formed below the insulation layer.

15. The method according to claim 13, wherein the metal structure comprises finger structures for connecting the multi-junction solar cell on the top side.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus, are not limitive of the present invention, and wherein:

[0042] FIGS. 1a, 1 b, and 1c are, in each case, a sequence of the filling of a passage opening with a subsequent etching step in cross-section,

[0043] FIG. 2 is a cross-section of a structured insulating layer with an exposed passage opening, and

[0044] FIG. 3 is a view of a semiconductor wafer with a plurality of solar cell stacks.

DETAILED DESCRIPTION

[0045] The illustrations of FIGS. 1a, b and c show a method for structuring an insulating layer 24 on a semiconductor wafer 10 with the filling of a passage opening 22 with subsequent structuring of an insulating layer 24 on a semiconductor wafer 10.

[0046] FIG. 1a shows a cut through the unfilled passage opening 22 of the semiconductor wafer 10. The semiconductor wafer 10 has a top 10.1, a bottom 10.2 and the passage opening 22 extending from the top 10.1 to the bottom 10.2 with a connected side wall 22.1.

[0047] The top 10.1 and the side wall 22.1 and the bottom 10.2 are completely covered with the insulating layer 24, wherein the insulating layer 24 covers the upper surfaces completely. It is understood that the insulating layer 24 is preferably formed as a layer system with multiple layers.

[0048] The semiconductor wafer 10 comprises at least one, although generally multiple, not-yet isolated solar cell stacks 12, each with a layer sequence formed of a Ge substrate 14 forming the bottom 10.2, a Ge subcell 16, a first III-V subcell 18 and a second III-V subcell 20 which forms the top 10.1.

[0049] In a plan view, not shown, the passage opening 22 has a nearly circular cross-section, wherein the layers shown are circumferential, both at the top 10.1 and in the passage opening 22 as well as on the bottom 10.2.

[0050] At the top 10.1, the passage opening 22 has a first diameter D1, and at the bottom 10.2, a second diameter D2. The first diameter D1 is larger than the second diameter D2. The tapering of the passage opening 22 from the top 10.1 to the bottom 10.2 takes place in several fully circumferential stages. In the present embodiment, the tapering comprises exactly two stages.

[0051] In one embodiment, not shown, the first diameter D1 is smaller than the second diameter D2.

[0052] Seen from the direction of the top 10.1, the first stage is at a boundary between the lowest III-V subcell 18 and the Ge subcell 16. The second stage is formed between the Ge subcell 16 and the Ge-substrate 14.

[0053] Preferably, the passage opening 22 also tapers within the Ge substrate 14. The step-shaped or conical embodiment of the passage opening has the advantage that in particular in the case of a preferably conformal deposition of the insulating layer 10 and/or other layers to be deposited, in the context of metallization, it is possible to sufficiently form the thickness of the layers on the side surfaces.

[0054] In a further method step, shown in the illustration of FIG. 1b, a filling material 32, which is etch-resistant as compared to the insulating layer, is deposited by means of a printing process on an area of the top 10.1 of the passage opening 22 which comprises the passage opening 22.

[0055] The filling material not only fully fills the passage opening 22 up to the top 10.1 of the semiconductor wafer, but also forms in each case a projecting elevation on the top 10.1 as well as on the bottom 10.2. On the bottom 10.2, the filling material 32 covers a larger edge region than on the top 10.1.

[0056] By means of a subsequent etching step, the insulating layer 24 is etched away in the areas not covered with the filling material 32, as shown in the result in FIG. 1c.

[0057] The illustration of FIG. 2 shows the cross-section of an insulating layer structured by means of the inventive method on a semiconductor wafer with a passage opening. In the following, only the differences to the illustrations of FIG. 1 are explained.

[0058] In a further method step, the filling material 32 is completely removed.

[0059] FIG. 3 shows a view of a semiconductor wafer 10 with multiple solar cell stacks 12. It is understood that in each area of each solar cell stack at least one hole is formed, which is processed by means of the method.

[0060] The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are to be included within the scope of the following claims.