III-nitride power semiconductor based heterojunction device

Abstract

An integrated circuit is provided which can sense the drain voltage of an active heterojunction transistor under different conditions and can adjust a driving signal of a gate terminal of the active heterojunction transistor in order to limit conduction losses and/or switching losses.

Claims

1. A III-nitride power semiconductor based heterojunction device comprising a first terminal, a second terminal and a control terminal and further comprising a substrate and an active heterojunction transistor formed on a substrate, the active heterojunction transistor comprising: a III-nitride semiconductor region comprising a heterojunction comprising an active two dimensional carrier gas; a source terminal operatively connected to the III-nitride semiconductor region and further connected to the first terminal; a drain terminal laterally spaced from the first terminal and operatively connected to the III-nitride semiconductor region, and further connected to the second terminal; an active gate region formed over the III-nitride semiconductor region and between the first terminal and the second terminal; and an internal gate terminal operatively connected to the active gate region; the III-nitride power semiconductor based heterojunction device further comprising: a gate drive circuit connected to the control terminal and further connected to the internal gate terminal of the active heterojunction transistor, the gate drive circuit being configured to provide a driving signal to the internal gate terminal of the active heterojunction transistor; a sensing circuit connected to the drain terminal of the active heterojunction transistor, and further connected to the first terminal, the sensing circuit being configured to sense a current and/or voltage at the drain terminal of the active heterojunction transistor and to generate an output signal; and an active stage circuit connected to the sensing circuit, and further connected to the gate drive circuit and to the source terminal of the active heterojunction transistor, the active stage circuit being configured to receive the output signal from the sensing circuit, and further configured to cause the gate drive circuit to adjust the driving signal based on the output signal from the sensing circuit; wherein, in use, when the active heterojunction transistor is in a forward conducting state, the first terminal is a low voltage terminal and the second terminal is a high voltage terminal; and wherein, when the active heterojunction transistor is in a reverse conducting state, the first terminal is a high voltage terminal and the second terminal is a low voltage terminal.

2. A III-nitride power semiconductor based heterojunction device according to claim 1, wherein the gate drive circuit is further configured to actively drive the internal gate terminal of the active heterojunction transistor when the sensing circuit senses a voltage at the drain terminal of the active heterojunction transistor relative to the source terminal of the active heterojunction transistor that is below a zero signal voltage.

3. A III-nitride power semiconductor based heterojunction device according to claim 2, wherein the active heterojunction transistor has an associated device breakdown rating voltage, and wherein the zero signal voltage has a maximum value of about 2% of the device breakdown rating voltage.

4. A III-nitride power semiconductor based heterojunction device according to claim 1, wherein, the active heterojunction transistor has an associated threshold voltage; and wherein: when the sensing circuit senses a reverse current between the first terminal and second terminal, the output signal from the sensing circuit is configured to cause the active stage circuit to adjust the driving signal of the gate drive circuit to increase an internal gate terminal voltage above a threshold voltage of the active heterojunction transistor.

5. A III-nitride power semiconductor based heterojunction device according to claim 1, wherein the sensing circuit comprises: a sensing high voltage, low power enhancement mode heterojunction transistor in series with a resistive or non-linear element; and wherein the drain terminal of the sensing high voltage, low power enhancement mode heterojunction transistor is operatively connected to the second terminal of the III-nitride power semiconductor based heterojunction device; and wherein the resistive or non-linear element comprises one or more resistors, capacitors, current sources and/or diodes.

6. A III-nitride power semiconductor based heterojunction device according to claim 5, wherein the sensing circuit further comprises one or more additional transistors, the one or more additional transistors configured as an active enable/disable function.

7. A III-nitride power semiconductor based heterojunction device according to claim 5, wherein the sensing circuit further comprises an output stage, wherein the output signal is output via the output stage of the sensing circuit; and wherein a further enhancement mode transistor is configured between the output stage and the first terminal; wherein a gate of the further enhancement mode transistor is operable via an enable/disable signal.

8. A III-nitride power semiconductor based heterojunction device according to claim 1, wherein the sensing circuit comprises a sensing high voltage, low power depletion mode heterojunction transistor; and wherein the drain terminal of the sensing high voltage, low power depletion mode heterojunction transistor is operatively connected to the second terminal of the III-nitride power semiconductor based heterojunction device.

9. A III-nitride power semiconductor based heterojunction device according to claim 1, wherein an output stage of the sensing circuit, or input or output stages of the active stage circuit, comprises additional functional or signal conditioning blocks; and wherein the functional or signal conditioning blocks are configured to operate as one or more of: an amplifier, a buffer, a Schmitt trigger, a latching circuit, a voltage follower, a logic gate, an inverter, a level shifter, and/or a filter.

10. A III-nitride power semiconductor based heterojunction device according to claim 1, wherein the active stage circuit comprises: at least one depletion mode HEMT and/or enhancement mode HEMT; or a plurality of depletion mode and/or enhancement mode HEMTs in series or in parallel.

11. A III-nitride power semiconductor based heterojunction device according to claim 1, wherein the active stage circuit comprises a differential amplifier, comparator or an amplifier in a common source arrangement or in a common gate arrangement.

12. A III-nitride power semiconductor based heterojunction device according to claim 1, wherein the signal from the active stage circuit is applied as an input to a controller, a gate drive and/or a gate drive interface, and wherein the signal is in the form of current or voltage.

13. A III-nitride power semiconductor based heterojunction device according to claim 1, wherein the active stage circuit is configured to have an input offset voltage; and wherein the active stage circuit comprises an additional input, and wherein the input offset voltage is configurable by adjustment of parameters of internal or external passive components connected to the additional input.

14. A III-nitride power semiconductor based heterojunction device according to claim 13, further comprising a comparator, wherein the comparator comprises at least a reference voltage node and an input voltage node; and wherein the input offset voltage is configurable as a reference voltage to said comparator; and wherein the output signal from the sensing circuit is configured as an input voltage to said comparator; and wherein the adjustable input off-set voltage is configured to avoid false triggering of the active stage circuit when noise or undesirable oscillations are detected at the input of the active stage circuit.

15. A III-nitride power semiconductor based heterojunction device according to claim 13, further comprising a comparator, and a signal conditioning block, wherein the comparator comprises at least a reference voltage node and an input voltage node; and wherein the input offset voltage is configurable as a reference voltage to said comparator; and wherein the output signal from the sensing circuit is configured as an input voltage to said comparator; and wherein the signal conditioning block is configured to avoid false triggering of the active stage circuit when noise or undesirable oscillations by filtering and/or level shifting the output signal from the sensing circuit.

16. A III-nitride power semiconductor based heterojunction device according to claim 1, wherein the active stage circuit is configured to output a voltage signal between 0V and a fixed voltage, wherein said fixed voltage is either internally generated or externally applied, and wherein said voltage signal is configured to cause the gate drive circuit to adjust the driving signal.

17. A III-nitride power semiconductor based heterojunction device according to claim 1, wherein the active stage circuit is configured to provide an input to an external controller.

18. A III-nitride power semiconductor based heterojunction device according to claim 1, wherein the gate drive circuit comprises a MOSFET Totem pole driver.

19. A III-nitride power semiconductor based heterojunction device according to claim 1, wherein a gate drive interface circuit is connected between the gate drive circuit and the active heterojunction transistor.

20. A III-nitride power semiconductor based heterojunction device according to claim 1, wherein a gate drive interface circuit is disposed between a controller and the gate drive circuit.

21. A III-nitride power semiconductor based heterojunction device according to claim 1, wherein two or more of the active heterojunction transistor, the gate drive circuit, the sensing circuit, and the active stage circuit are monolithically integrated with one another.

22. A III-nitride power semiconductor based heterojunction device comprising a first terminal, a second terminal and a control terminal and further comprising a substrate and an active heterojunction transistor formed on a substrate, the active heterojunction transistor comprising: a III-nitride semiconductor region comprising a heterojunction comprising an active two dimensional carrier gas; a source terminal operatively connected to the III-nitride semiconductor region and further connected to the first terminal; a drain terminal laterally spaced from the first terminal and operatively connected to the III-nitride semiconductor region, and further connected to the second terminal; an active gate region formed over the III-nitride semiconductor region and between the first terminal and the second terminal; and an internal gate terminal operatively connected to the active gate region; the III-nitride power semiconductor based heterojunction device further comprising: a gate drive interface circuit connected to the control terminal and further connected to the internal gate terminal of the active heterojunction transistor, the gate drive interface circuit being configured to provide a driving signal to the internal gate terminal of the active heterojunction transistor; a sensing circuit connected to the drain terminal of the active heterojunction transistor, and further connected to the first terminal, the sensing circuit being configured to sense a current and/or voltage at the drain terminal of the active heterojunction transistor and to generate an output signal; and an active stage circuit connected to the sensing circuit, and further connected to the gate drive interface circuit and to the source terminal of the active heterojunction transistor, the active stage circuit being configured to receive the output signal from the sensing circuit, and further configured to cause the gate drive interface circuit to adjust the driving signal based on the output signal from the sensing circuit; wherein, in use, when the active heterojunction transistor is in a forward conducting state, the first terminal is a low voltage terminal and the second terminal is a high voltage terminal; and wherein, when the active heterojunction transistor is in a reverse conducting state, the first terminal is a high voltage terminal and the second terminal is a low voltage terminal.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a graph illustrating a typical reverse conduction I-V characteristic of a GaN HEMT;

(2) FIG. 2 is a schematic illustration of a power semiconductor device according to the present disclosure;

(3) FIGS. 3 to 6 are schematic illustrations of example sensing circuits according to the present disclosure;

(4) FIG. 7 is a schematic illustration of a circuit in which a gate drive circuit is co-packaged or included in a module arrangement, or included at system level;

(5) FIG. 8 is a schematic illustration of an example of a MOSFET Totem-pole driver;

(6) FIG. 9 is a schematic illustration of a gate drive circuit according to the present disclosure;

(7) FIG. 10 is a schematic illustration of an active stage circuit according to the present disclosure;

(8) FIGS. 11 to 13 are schematic illustrations of further gate drive circuits according to the present disclosure;

(9) FIG. 14 is a schematic illustration of a gate drive interface circuit according to the present disclosure;

(10) FIG. 15 is a schematic illustration of an active stage circuit according to the present disclosure;

(11) FIG. 16 is a schematic illustration of a further active stage circuit according to the present disclosure;

(12) FIG. 17 is a schematic illustration of an alternative arrangement of a power semiconductor device according to the present disclosure;

(13) FIG. 18 is a schematic illustration of an example active stage circuit suitable for the power semiconductor device illustrated in FIG. 17;

(14) FIGS. 19 to 21 are schematic illustrations of further active stage circuits according to the present disclosure;

(15) FIG. 22 is a schematic illustration of a gate drive circuit according to the present disclosure;

(16) FIG. 23 is a schematic illustration of an active stage circuit according to the present disclosure;

(17) FIG. 24 illustrates a graph of a voltage change with time in a switching event for a sense circuit output, VDS, a GaN HEMT gate, and a gate signal;

(18) FIGS. 25 and 26 are schematic illustrations of gate drive circuits according to the present disclosure;

(19) FIG. 27 is a schematic illustration of an active stage circuit according to the present disclosure;

(20) FIGS. 28 and 29 are schematic illustrations of gate drive circuits according to the present disclosure;

(21) FIG. 30 is a schematic illustration of a gate drive circuit/active stage circuit combination according to the present disclosure;

(22) FIGS. 31 and 32 are schematic illustrations of active stage circuits according to the present disclosure;

(23) FIG. 33 is a schematic illustration of the various circuit blocks of a gate drive interface according to the present disclosure;

(24) FIG. 34 is a schematic illustration of an example gate drive interface circuit according to the present disclosure;

(25) FIG. 35 is a schematic illustration of an active stage circuit according to the present disclosure; and

(26) FIG. 36 is a schematic illustration of an example gate drive interface circuit according to the present disclosure.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

(27) FIG. 2 shows a circuit schematic representation of one embodiment of the proposed disclosure. This embodiment illustrates a power semiconductor heterojunction device 110a (which may be a GaN chip or GaN power integrated circuit, and is hereafter referred to as a GaN chip) comprising an active heterojunction transistor 101, (referred to herein as a high voltage heterojunction transistor, such as a high voltage HEMT, or high voltage transistor), a sensing circuit 102, an active stage circuit 104 and a gate drive circuit 105.

(28) In general, the active heterojunction transistor comprises: a first III-nitride semiconductor region comprising a first heterojunction comprising an active two dimensional carrier gas; a source terminal operatively connected to the III-nitride semiconductor region and further connected to the first terminal; a drain terminal laterally spaced from the first terminal and operatively connected to the III-nitride semiconductor region and further connected to the second terminal; an active gate region formed over the III-nitride semiconductor region and between the first terminal and the second terminal; and an internal gate terminal operatively connected to an the active gate region.

(29) The GaN chip illustrated comprises at least four terminals: a high voltage terminal, a low voltage terminal, a control terminal and a voltage supply terminal (VDD).

(30) In some examples, further DC voltage rails may be present in the chip, labelled in the example of FIG. 2 as VS and VDD1. These may either be applied externally or may be generated on the GaN chip from VDD.

(31) The GaN chip in this embodiment can sense the voltage on the drain terminal of transistor 101 through the sensing circuit 102 and provide a signal to the active stage circuit 104 which can adjust the driving pattern of transistor 101.

(32) In one example sensing circuit 102a, such as the one illustrated in FIG. 3, the output of the sensing circuit may be configured to have the following characteristics:

(33) When the main HEMT pGaN gate is driven on (e.g. Vgs=6V) and the potential on the drain terminal of transistor 101 is low positive (e.g. 10V>Vds>0).fwdarw.sensing circuit output is 0V or positive.

(34) When the main HEMT pGaN gate is driven off (e.g. Vgs=0V) and the potential on the drain terminal of transistor 101 is high positive (e.g. Vds>10V).fwdarw.sensing circuit output is VS Vth (where Vth is the threshold voltage of the sensing transistor 1021).

(35) When the main HEMT pGaN gate is driven off (e.g. Vgs=0V) and the potential on the drain terminal of transistor 101 is negative (i.e. Vds<0).fwdarw.sensing circuit output <0.

(36) The sensing circuit 102a in FIG. 3 comprises a sensing enhancement mode high voltage transistor 1021, a capacitor 1022, a resistor 1024 and a source-gate connected transistor 1023.

(37) In one example mode of operation, the GaN Chip 110a can sense when the power device operates in reverse conduction and actively drive the gate terminal which can lead to a significant reduction in conduction losses.

(38) In this mode of operation, the active stage circuit will receive a negative input signal from the sensing circuit when the main HEMT is in reverse conduction mode. The active stage should therefore be designed to enable or allow an increase in the main HEMT gate voltage potential when it receives the aforementioned negative input signal from the sensing circuit.

(39) The required function is as follows:

(40) Sensing output signal positive or 0.fwdarw.gate of transistor 101 should correspond to gate control signal

(41) Sensing output signal negative.fwdarw.gate of transistor 101 should rise (Vgs>0V) irrespective of gate control signal

(42) In another example as illustrated in FIG. 4 an example sensing circuit 102b comprises an Enable and Disable function by connecting an actively controlled E-HEMT 1026 as illustrated. An Enable/Disable pin may receive a signal generated on the IC or may be an external terminal. E-HEMT 1026 may be replaced by a D-HEMT. A current source, comprised by depletion mode HEMT 1027 and resistor 1028, is placed between the source of the high voltage transistor 1021 and the actively controlled E-HEMT 1026. The current source may limit the power consumption through the sensing circuit during the Disable mode of operation.

(43) In another example sensing circuit 102c illustrated in FIG. 5 the Enable/Disable function is implemented using actively controlled E-HEMTs 1029 and 10201. E-HEMT 1029 can short the output signal 1025 to ground during Disable mode. E-HEMT 10201 can turn-off high voltage transistor 1021 during Disable mode. Resistor 10202 can limit the power consumption from VS by limiting the current to ground during Disable mode.

(44) In another example sensing circuit 102d illustrated in FIG. 6 the Enable/Disable function is implemented using actively controlled E-HEMTs 1029, 10204 and inverter 10203. E-HEMT 1029 can short the output signal 1025 to ground during Disable mode. E-HEMT 10204 which is a high voltage transistor can limit the power consumption of the sensing circuit during Disable mode as it would in the off-state during this mode of operation.

(45) Depending on the gate drive circuit used in the GaN chip, an appositely designed active stage circuit can be used.

(46) In some embodiments, the output signal from the active stage circuit may be a voltage signal. In some embodiments, the output signal from the active stage circuit may be a current signal. In some embodiments the output signal from the active stage circuit may be defined as the offering or lack of offering of a low resistance path to source to the node where the output of the active stage circuit is connected. In some embodiments, the offering or lack of offering of a low resistance path may be understood as a current signal.

(47) Note that in the examples presented here the gate drive circuit 105 may not be monolithically integrated (see FIG. 7) but rather co-packaged or included in a GaN module arrangement or included at system level.

(48) In some examples, the gate drive circuit 105 may comprise a MOSFET Totem-pole driver. An example of MOSFET Totem-pole driver 105a common in prior art is shown in FIG. 8. The example gate drive circuit 105a given in FIG. 8 comprises an inverter 1056, an enhancement mode NMOS device 1058 and an enhancement mode PMOS device 1057. The gate node 200 of the two MOSFET devices is an inverted signal compared to the signal 1059 that is applied to the gate terminal of the high voltage device 101.

(49) One example of a gate drive circuit/active stage circuit combination according to this invention is given in FIG. 9 and FIG. 10.

(50) The gate drive circuit 105 given in FIG. 9 is a MOSFET Totem-pole driver design which comprises a NOR gate 10501, an enhancement mode NMOS device 1058 and an enhancement mode PMOS device 1057.

(51) The active stage circuit illustrated in FIG. 10 comprises a depletion mode n-channel transistor 1047, a resistor 10403, two signal conditioning circuit blocks 10404 and a voltage rail VDD1. Voltage VDD1 may be generated on the GaN IC or may be applied externally. The active stage circuit generates a voltage signal 1048.

(52) The resistor 10403 may be replaced by a current source or an active pull-up circuit.

(53) In some embodiments the signal conditioning circuits may be optional. In some embodiments, the signal conditioning circuit may contain functional blocks such as a buffer, Schmitt trigger, latching circuit, voltage follower, logic gate, inverter, level shifter or similar.

(54) Signal 1025 is provided by the sensing circuit illustrated in FIG. 3.

(55) Transistor 1047 is in the on-state when signal 1025 is zero or positive. It turns-off as signal 1025 becomes more negative than the depletion mode transistor 1047 threshold voltage.

(56) If the high voltage device 101 is reverse conducting the active stage outputs a high signal (close to VDD1) and therefore one of the inputs to the NOR gate 10501 is high. This results in the output of the gate drive signal 1059 being high (close to VDD). This gate drive signal allows the gate terminal of device 101 to rise, reducing the resistance of device 101 and therefore leading to a reduction in the conduction losses during reverse conducting operation.

(57) The output of the active stage circuit is low (close to ground) in other modes of operation other than reverse conduction.

(58) The second input of the NOR gate 10501 is the control signal from the controller. When the active stage signal 1048 is low the output of the gate driver signal 1059 is dependent only on the control signal.

(59) The different conditions of operation are captured in Table 1.

(60) TABLE-US-00001 TABLE 1 Gate Driver input signal Active Heterojunction Sensing Circuit signal Active Stage signal Active Heterojunction from Controller Transistor V.sub.DS to Active Circuit to Gate Driver Transistor V.sub.gs Low High positive High Low Low Low Negative Negative (<Vth) High High High Low positive Low Low High

(61) It may be necessary for correct operation of the example presented that an element of hysteresis or latching is included on either signal 1025 or 1048. This may be implanted using a Schmitt trigger, latching circuit or other similar circuits in the signal conditioning blocks 10404, 10405. This is to avoid oscillations of the gate voltage during reverse conduction.

(62) In another embodiment the circuit in FIG. 11 can be combined with the active stage circuit in FIG. 10. The operation of this combination can also be summarized by Table 1. In this embodiment the gate driver 105 is identical to the gate driver presented in FIG. 8. In this embodiment an OR gate 1071 is placed between the gate driver and the controller and the active stage circuit output is an input in this OR gate. Other combinational logic circuits can be used in other embodiments.

(63) In another embodiment, illustrated in FIG. 12, the active stage circuit output 1048 is applied to the controller 106.

(64) Another example of a gate drive circuit/active stage circuit combination is given in FIG. 13, FIG. 14, FIG. 15.

(65) The gate drive circuit 105 in FIG. 13 comprises a gate drive interface circuit 103, inverters 10502, 10503, 10504, 10505 and a DC/DC regulator 1054. The gate drive circuit 105 further comprises a disable/turn-off block 10506.

(66) The function of the turn-off block 10506 is to provide a turn-off path for the main gate of transistor 101. In one embodiment the turn-off path comprises an enhancement mode transistor acting as a Miller clamp, that is connected between the gate and source of transistor 101. The control signal for this Miller clamp transistor could be provided by one of the inverted signal inputs of the turn-off circuit block.

(67) The function of a disable circuit block 10506 is to enable or disable the functionality of the active reverse conduction circuit.

(68) Signal 1051 is connected to the main gate terminal of the high voltage GaN HEMT 101. Signals 1052 and 1053 act as inputs to the active stage circuit in FIG. 15.

(69) The gate drive interface circuit 103 comprises an auxiliary gate circuit 1033, current control circuit 1032 and pull-down circuit 1031 as illustrated in FIG. 14. The gate drive interface circuit has two input signals from the active stage circuit or disable/turn-off circuit 10506, signal 1044 and signal 1043.

(70) The gate drive circuit given here as an example is outlined in detail in patent application US patent publication no. US 2021/0335781 A1.

(71) The active stage circuit in FIG. 15 comprises two branches of a depletion mode HEMT and an enhancement mode HEMT in series.

(72) Input signal 1025 is the output signal from the sensing circuit and is applied to the gate terminals of depletion mode transistors 1041 and 1042. As outlined above the output signal of the sensing circuit is negative when the potential on the drain terminal of transistor 101 is negative (i.e. Vds<0) during reverse conduction. When the gate potential of the depletion mode HEMTs is biased negatively (<Vth) the transistors can be in the off-state. This can therefore allow the potential on the terminals where 1043 and 1044 are connected to rise. The potentials on the nodes where signals 1043 and 1044 are provided (as illustrated in FIG. 14) need to increase in order for the potential on the gate terminal of the high voltage device to increase.

(73) In the mode of operation where the external control signal (or GaN IC gate signal) is high, the enhancement mode transistors 10410, 10411 in the active stage circuit, which receive an inverted signal, are off. This allows the gate terminal of the main HEMT 101 to rise irrespective of whether depletion mode HEMTs 1041 and 1042 are on or off.

(74) The output signals 1043 and 1044 by the active stage circuit are in this example defined as the absence or presence of a low resistance path to ground. Alternatively, this signal can be defined as a current signal.

(75) Signal conditioning circuit blocks may be included in the input or output paths of the active stage circuit.

(76) The different conditions of operation are captured in Table 2:

(77) TABLE-US-00002 TABLE 2 Gate Driver input signal Active Heterojunction Sensing Circuit signal Active Stage Active Heterojunction from Controller Transistor V.sub.DS to Active Circuit resistance Transistor V.sub.gs Low High positive High Low Low Low Negative Negative (<Vth) High High High Low positive Low Low High

(78) In another embodiment, the active stage circuit may be implemented within the gate drive circuit block. In this embodiment, some of the components of the active stage circuit and the disable/turn-off circuit may be common, for example the active stage 104b may replace the turn-off/disable block 10506.

(79) In an additional embodiment the active stage circuit could comprise an E-HEMT 10401 in common gate arrangement as illustrated in FIG. 16. The operation of this embodiment is as follows:

(80) Sensing circuit signal 1025 positive or 0.fwdarw.E-HEMT 10401 blocking.fwdarw.Node 10412 is high

(81) Sensing circuit signal 1025 negative 4.fwdarw.E-HEMT 10401 is conducting (gate>source).fwdarw.Node 10412 falls.

(82) The active stage circuit in this example may be used in combination with gate drive circuit examples in FIG. 9, FIG. 11, FIG. 12 if the output of the common gate amplifier is inverted by inverter 10413. In another example, this active stage (node 10412) may control a second active stage. This second active stage may be similar to the one shown in FIG. 15 but comprising enhancement HEMTs instead of depletion HEMTs 1041 and 1042.

(83) In another embodiment the proposed invention could operate as a smart rectifier. In this embodiment there is no external control terminal and therefore no external gate signal is applied. This can be done by setting the gate signal input to a fixed voltage. A simplified alternative embodiment is shown in FIG. 17. The sensing circuit in this embodiment may be identical to the example illustrated in FIG. 3. The gate drive interface in this embodiment may be identical to the example illustrated in FIG. 14. An example of a suitable active stage circuit in this embodiment is illustrated in FIG. 18.

(84) The different conditions of operation for this embodiment are captured in Table 3. As explained above, in this and in all the other examples the gate voltage of the high voltage device may rise as a result of the disclosed invention when the drain to source voltage is negative. Note that this gate voltage may reach the same level as when the device is turned on in forward direction or that it may reach a different level and that this voltage level may depend on the drain voltage or drain current of the active device.

(85) TABLE-US-00003 TABLE 3 Gate Driver input signal Active Heterojunction Sensing Circuit signal Active Stage Active Heterojunction from Controller Transistor V.sub.DS to Active Circuit resistance Transistor V.sub.gs N/A High positive High Low Low N/A Negative Negative High High N/A Low positive Low Low Low

(86) Another embodiment of the active stage circuit comprises a comparator 10417, a resistor 10418 and two signal conditioning blocks 10404, 10405.

(87) The comparator provides a high output when the input voltage (minus signal) node is lower than the reference voltage (plus signal) node and a low output vice versa. In the embodiment illustrated in FIG. 19 the reference voltage is the source bias. When the main HEMT 101 is in reverse conduction mode the sensing circuit will output a negative signal 1025 and therefore the comparator will output a high signal. The active stage output 1048 is similar to the signal provided by the active stage circuit in FIG. 10. As such the active stage in this embodiment may be paired with the gate drive circuits in FIG. 9, FIG. 11, FIG. 12.

(88) Additionally, the active stage circuit 104e may be paired with the gate drive circuit in FIG. 13.

(89) The signal conditioning block 10404 may be used in this embodiment of the active stage circuit to filter or level shift signal 1025 from the sensing circuit. This may be useful in order to avoid false triggering of the active stage circuit when noise or undesirable oscillations are detected at the input of the active stage circuit.

(90) A negative reference voltage may be another option to avoid false triggering. The shift of the reference voltage may be described as an input off-set voltage. This may be done by circuit design within the active stage circuit and based on the implementation of the comparator circuit used. An embodiment with an input off-set voltage is illustrated in FIG. 20.

(91) In the embodiment of FIG. 21 the input off-set voltage may be adjusted externally based on the value of a passive component connected to an additional external input. In exemplar embodiments the passive component may be a resistor or a capacitor.

(92) In a second exemplar mode of operation, the GaN chip 110a can sense the voltage on the drain terminal of the GaN HEMT which can be of use in zero voltage switching (ZVS) applications. In this example, sensing the drain to source voltage of a GaN HEMT and using the sense signal such that the potential on the gate terminal of the GaN HEMT is only permitted to rise to the on-state bias range (Vgs=4V and 7V as described above) when the drain to source voltage is low (e.g. zero or 2% of device breakdown rating), allows the designer to simplify the control and increase the efficiency of a system using the device in a ZVS mode.

(93) The embodiment of the sensing circuit illustrated in FIG. 3 may also be suitable for use in this mode of operation of the GaN chip.

(94) However, in the following examples, the active stage circuit of the GaN chip may differ compared to the active stage circuit embodiments used in the first mode of operation. The active stage circuit in this mode of operation will receive a zero signal from the sensing circuit when the voltage across the drain-source of the main HEMT is zero. Zero signal (or low voltage e.g. 2% of device breakdown rating, or negative) across the main HEMT is important as it is at this condition where gate of the main HEMT should be permitted to be actively driven high according to the gate control signal. The active stage should therefore be designed to allow an increase in the main HEMT gate voltage potential when it receives the aforementioned input signal from the sensing circuit.

(95) The required function is as follows: Sensing output signal high positive.fwdarw.gate of transistor 101 should remain low (e.g. Vgs=0V) irrespective of gate control signal. Sensing output signal low positive (<Vth), zero or negative.fwdarw.gate of transistor 101 should rise (Vgs>0V) according to gate control signal.

(96) Depending on the gate drive circuit used in the GaN chip an appositely designed active stage circuit can be used.

(97) In some embodiments, the output signal from the active stage circuit may be a voltage signal. In some embodiments, the output signal from the active stage circuit may be a current signal. In some embodiments the output signal from the active stage circuit may be defined as the offering or lack of offering of a low resistance path to ground to the node where the output of the active stage circuit is connected. In some embodiments, the offering or lack of offering of a low resistance path may be understood as a current signal.

(98) One example of a gate drive circuit/active stage circuit combination is given in FIG. 22 and FIG. 23. Note that the gate drive circuit presented in this example may not be monolithically integrated but rather co-packaged or included in a GaN module arrangement or included at system level (see FIG. 7).

(99) The gate drive circuit 205 given in this example is a MOSFET Totem-pole driver design which comprises an inverter 2056, an enhancement mode NMOS device 1058 and an enhancement mode PMOS device 2057. The gate node 201 of the two MOSFET devices is an inverted signal compared to the signal 2059 that is applied to the gate terminal of the high voltage device 101.

(100) The block circuit illustrated in FIG. 2, FIG. 7 can be used to achieve zero voltage switching when the gate drive and active stage combination is used as illustrated in FIG. 22, FIG. 23.

(101) The active stage circuit in this example comprises an enhancement mode transistor 20401 and signal conditioning circuit blocks 20406, 20407.

(102) In some embodiments the signal conditioning circuits may be optional. In some embodiments, the signal conditioning circuit may contain functional blocks such as a buffer, Schmitt trigger, latching circuit, voltage follower, logic gate, inverter, level shifter or similar.

(103) The gate terminal of this transistor receives the signal 1025 from the sensing circuit 102. This transistor can only turn-off (and thus allow the gate drive circuit to provide a high signal) when the signal from the sensing circuit is lower than its threshold voltage (for example <1.5V). The high voltage HEMT can therefore only turn-on when the output signal from the sensing circuit is low, i.e. when the high voltage across HEMT 101 is low. Operation in this manner can therefore create a short or negligible overlap of voltage and current through device 101 during a switching event. This is illustrated in FIG. 24. Despite the gate control signal going high, the GaN HEMT gate potential is only allowed to rise when VDS reduces to a voltage close to 0V. The output of the sense circuit and how it relates to VDS is also shown in FIG. 24.

(104) The different conditions of operation are captured in Table 4:

(105) TABLE-US-00004 TABLE 4 Gate Driver input signal Active Heterojunction Sensing Circuit signal Active Stage Active Heterojunction from Controller Transistor V.sub.DS to Active Circuit resistance Transistor V.sub.gs Low High positive High Low Low High High positive High Low Low High Low positive Low High High

(106) In another embodiment illustrated in FIG. 25 the active stage circuit is connected to the input of the gate driver rather than the output of the gate driver. The active stage circuit in FIG. 23 may still be paired with the gate drive circuit illustrated in this embodiment.

(107) Embodiments shown in FIG. 22 and FIG. 25 may result in significant losses in the drive circuit as the gate driver current (FIG. 22) or controller output current (FIG. 25) is sunk to ground when the active stage circuit provides a low resistance path under certain conditions.

(108) In another embodiment, not illustrated here, signal 20402 could be connected to the control terminal of a transistor switch circuit placed in series with the input or output of the gate driver. This may result in reduced gate driver losses compared to the examples shown in FIG. 22 and FIG. 25.

(109) Another combination of a gate drive circuit and an active stage circuit which enables zero voltage switching, is illustrated in FIG. 26, FIG. 27. The active stage circuit in FIG. 27 comprises an enhancement mode HEMT 20403, a resistor 20405, two optional signal conditioning circuit blocks 20406, 20407 and a voltage rail VDD1. The voltage rail may be applied externally or generated on the GaN chip IC. The resistor 10405 may be replaced by a current source or an active pull-up circuit.

(110) In another embodiment, the common source amplifier configuration illustrated in FIG. 27 could be replaced with a common gate amplifier configuration.

(111) The gate drive circuit comprises a NAND gate 20501 with two inputs. One input is the control signal and the second input is the voltage signal 20404 from the active stage circuit.

(112) In another embodiment the configuration in FIG. 26 could be replaced with the configuration in FIG. 28. In this embodiment an AND gate outside the gate drive circuit 205a is included. This AND gate is placed between the controller and the gate drive circuit. The AND gate has two inputs, the control signal from the controller and the signal 20404 from the active stage circuit in FIG. 27.

(113) In another embodiment, the active stage circuit signal 20404 could be applied to the controller as illustrated in FIG. 29.

(114) Another example of a gate drive circuit/active stage circuit combination is given in FIG. 30, FIG. 31, FIG. 33.

(115) The example in FIG. 30 illustrates an additional example of how the setup can be utilized to allow zero voltage switching. In this example the device 120 can comprise a gate drive interface 103 rather than an integrated gate driver. The gate drive interface described in this example is outlined in detail in patent application US patent publication no. US 2021/0335781 A1 and International Patent publication no. WO 2020/225362 A1, both of which are hereby incorporated by reference. The building blocks of the gate drive interface are illustrated in FIG. 33. The gate drive interface comprises an auxiliary gate circuit block 2033, a current control block 2032, a pull-down circuit block 2031, a DC/DC converter 2035, a Miller clamp 2037, a logic inverter 2036 and a Vg to Vlogic circuit block 2034.

(116) The active stage in this example comprises two enhancement mode transistors 2045 and 2046, and three optional signal conditioning circuit blocks 20413, 20414, 20415.

(117) The gate terminal of these transistors receives the signal 1025 from the sensing circuit 102. These transistors can only turn-off (and thus allow the high voltage HEMT to turn-on) when the signal from the sensing circuit is lower than the enhancement mode transistor threshold voltage. The high voltage HEMT can therefore only turn-on when the output signal from the sensing circuit is low i.e. when the high voltage across HEMT 101 is low creating a short or negligible overlap of voltage and current through device 101 during a switching event.

(118) The different conditions of operation are equivalent therefore to those captured in Table 4.

(119) In another embodiment, the active stage/gate drive interface circuit in FIG. 34, FIG. 35 may be used.

(120) The gate drive interface circuit 203b in FIG. 34 is similar to the gate drive interface illustrated in FIG. 33 but contains a NAND gate 2038 rather than an inverter circuit 2036. One of the inputs of the NAND gate is a voltage signal form the active stage circuit 20412.

(121) The active stage circuit 204d in FIG. 35 comprises two enhancement mode transistors 1045, 1046, three optional signal conditioning blocks 20409, 20410, 20411, a resistor 20408 and a voltage rail VDD1. The voltage VDD1 could be generated on the GaN chip or applied externally. The resistor 20408 may be replaced by a current source or an active pull-up circuit.

(122) The ability to overrule the ZVS functionality in order to allow hard switching is necessary in certain applications. Therefore, some variations of the embodiments illustrated can contain such an enable/disable function. This function may be placed in the sensing circuit as in FIG. 4, in the active stage circuit as in FIG. 32 or the gate drive interface circuit as illustrated in FIG. 36.

(123) The sensing circuit of FIG. 4 comprises an additional enhancement mode transistor 1026 compared to the circuit in FIG. 3. The control terminal of transistor 1026 is described as the enable/disable input. The signal for this input may be applied externally or generated on the GaN IC. In this example when the enable/disable signal is high (>Vth) the ZVS function is overruled as the output of the sensing circuit is zero regardless of the voltage across the terminals of the main HEMT 101.

(124) The active stage circuit of FIG. 32 comprises an additional enhancement mode transistor 20416 compared to the circuit in FIG. 31. The control terminal of transistor 20416 is described as the enable/disable input. The signal for this input may be applied externally or generated on the GaN IC. In this example when the enable/disable signal is low (<Vth) the ZVS function is overruled. This is due to that, regardless of the input signal from the sensing circuit 1025, the resistance of the active stage circuit will be high. Therefore, the active stage circuit cannot provide a low resistance path (alternatively described as a high current signal) to the nodes where active stage circuit outputs 2043 and 2044 are connected. Alternatively, a transistor connected to the gates of transistors 2045 and 2046 may be used to disable and enable the function.

(125) The gate drive interface circuit of FIG. 36 comprises additional logic gates 2039, 20301 and 20302 compared to the circuit in FIG. 34. An additional input (enable/disable) is included in this embodiment. The active stage signal is signal 20404 as illustrated in FIG. 27. In this embodiment, the ZVS function is enabled when the enable/disable input is high and the ZVS function is disabled when the input is low.

(126) The skilled person will understand that in the preceding description and appended claims, positional terms such as top, above, overlap, under, lateral, etc. are made with reference to conceptual illustrations of a device, such as those showing standard cross-sectional perspectives. These terms are used for ease of reference but are not intended to be of limiting nature.

(127) Although the disclosure has been described in terms of preferred embodiments as set forth above, it should be understood that these embodiments are illustrative only and that the claims are not limited to those embodiments. Those skilled in the art will be able to make modifications and alternatives in view of the disclosure which are contemplated as falling within the scope of the appended claims. Each feature disclosed or illustrated in the present specification may be incorporated in the disclosure, whether alone or in any appropriate combination with any other feature disclosed or illustrated herein.

(128) Many other effective alternatives will occur to the person skilled in the art. It will be understood that the disclosure is not limited to the described embodiments, but encompasses all the modifications which fall within the spirit and scope of the disclosure.

REFERENCES

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