OPTOELECTRONIC SEMICONDUCTOR CHIP AND METHOD FOR PRODUCTING AN OPTOELECTRONIC SEMICONDUCTOR CHIP

Abstract

In one embodiment, the optoelectronic semiconductor chip comprises a semiconductor layer sequence with an active zone for generating a radiation. The semiconductor layer sequence is based on AlInGaP and/or on AlInGaAs. A metal mirror for the radiation is located on a rear side of the semiconductor layer sequence opposite a light extraction side. A protective metallization is applied directly to a side of the metal mirror facing away from the semiconductor layer sequence. An adhesion promoting layer is located directly on a side of the metal mirror facing the semiconductor layer sequence. The adhesion promoting layer is an encapsulation layer for the metal mirror, so that the metal mirror is encapsulated at least at one outer edge by the adhesion promoting layer together with the protective metallization.

Claims

1. An optoelectronic semiconductor chip comprising: a semiconductor layer sequence with an active zone for generating a radiation; a metal mirror for the radiation; a protective metallization directly on a side of the metal mirror facing away from the semiconductor layer sequence; and an adhesion promoting layer directly on a side of the metal mirror facing the semiconductor layer sequence, wherein the adhesion promoting layer is an encapsulation layer for the metal mirror so that the metal mirror is encapsulated at least at an outer edge by the adhesion promoting layer together with the protective metallization.

2. The optoelectronic semiconductor chip according to claim 1, comprising one or more metallic electrical through-connections which extend directly up to a side of the semiconductor layer sequence facing the metal mirror or directly up to a contact layer of a transparent conductive oxide and terminate at a distance from the active zone, wherein the at least one through-connection is formed in a region closest to the semiconductor layer sequence by the protective metallization, wherein the adhesion promoting layer and the protective metallization project laterally beyond the semiconductor layer sequence, and wherein the metal mirror is completely encapsulated at all edges by the adhesion promoting layer together with the protective metallization and, viewed in cross-section, borders exclusively to the protective metallization together with the adhesion promoting layer.

3. The optoelectronic semiconductor chip according to claim 1, wherein the metal mirror is a silver mirror, the adhesion promoting layer is made of aluminum oxide, the protective metallization is a layer stack of several metal layers, and a region between the semiconductor layer sequence and the protective metallization is free of cavities.

4. The optoelectronic semiconductor chip according to claim 1, further comprising at least one metallic electrical through-connection, wherein the through-connection extends up to a side of the semiconductor layer sequence facing the metal mirror and terminates at a distance from the active zone.

5. The optoelectronic semiconductor chip according to claim 4, wherein the adhesion promoting layer is removed from a region of the through-connection nearest to the semiconductor layer sequence, wherein the adhesion promoting layer partially or completely covers side flanks of the through-connection.

6. The optoelectronic semiconductor chip according to claim 4, wherein the through-connection is formed in a region closest to the semiconductor layer sequence by the metal mirror.

7. The optoelectronic semiconductor chip according to claim 6, wherein the protective metallization in the through-connection is closer to the semiconductor layer sequence than adjacent regions of the metal mirror.

8. The optoelectronic semiconductor chip according to claim 4, wherein the through-connection (5) is formed in a region closest to the semiconductor layer sequence by the protective metallization.

9. The optoelectronic semiconductor chip according to claim 1, further comprising a reflector of at least one material which is transparent for the radiation generated during operation, wherein the reflector is located directly between the semiconductor layer sequence and the adhesion promoting layer.

10. The optoelectronic semiconductor chip according to claim 9, wherein the reflector is electrically insulating and is penetrated by the through-connection, wherein the reflector projects beyond the semiconductor layer sequence and/or the metal mirror when viewed in plan view.

11. The optoelectronic semiconductor chip according to claim 10, wherein the reflector directly adjoins the protective metallization in regions which, seen in plan view, are located next to the semiconductor layer sequence.

12. The optoelectronic semiconductor chip according to claim 1, wherein the adhesion promoting layer and the protective metallization project laterally beyond the semiconductor layer sequence.

13. The optoelectronic semiconductor chip according to claim 1, further comprising a contact layer of a transparent conductive oxide, wherein the contact layer directly adjoins the semiconductor layer sequence and is electrically ohmically connected to the metal mirror.

14. The optoelectronic semiconductor chip according to claim 13, wherein the adhesion promoting layer extends to the contact layer.

15. Optoelectronic semiconductor chip according to claim 4, wherein in region of the through-connections the semiconductor layer sequence has a greater thickness in each case, wherein the contact layer is restricted to the regions with the greater thickness.

16. The optoelectronic semiconductor chip according to claim 1, wherein the adhesion promoting layer has a uniform, constant thickness at least over the metal mirror, wherein different regions of the adhesion promoting layer do not overlap each other.

17. The optoelectronic semiconductor chip according to claim 1, further comprising a cover layer which extends from the light extraction side over side flanks of the semiconductor layer sequence up to the adhesion promoting layer, so that the semiconductor layer sequence is enclosed by the cover layer together with the adhesion promoting layer and the protective metallization in at least one cross-sectional view, wherein the cover layer and the adhesion promoting layer are made of the same material.

18. The optoelectronic semiconductor chip according to claim 17, in which the cover layer is covered with a moisture protection layer.

19. The optoelectronic semiconductor chip according to claim 1, wherein the adhesion promoting layer is spaced apart from the semiconductor layer sequence, and wherein on a side facing the semiconductor layer sequence the adhesion promoting layer is exclusively in contact with the reflector.

20. The optoelectronic semiconductor chip according to claim 1, wherein, on a side facing away from the adhesion promoting layer, the reflector is in direct contact with both, the rear side of the semiconductor layer sequence and the contact layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0076] In the following, an optoelectronic semiconductor chip described here is explained in more detail with reference to the drawings using exemplary embodiments. Identical reference signs indicate identical elements in the individual figures.

[0077] However, references are not shown true to scale; individual elements may be shown in exaggerated size for better understanding.

[0078] In the figures:

[0079] FIG. 1 shows a schematic sectional view of a modification of a semiconductor chip.

[0080] FIGS. 2 to 8 show schematic sectional views of exemplary embodiments of optoelectronic semiconductor chips described here, and

[0081] FIGS. 9A to 9E schematic sectional views of process steps of an exemplary embodiment of a method for producing an optoelectronic semiconductor chip described here.

DETAILED DESCRIPTION

[0082] FIG. 1 illustrates a modification 1′ of a semiconductor chip. The modification 1′ comprises a semiconductor layer sequence 2 with an active zone 23 for generation of radiation. The active zone 23 is located between a first side 21 and a second side 22 of the semiconductor layer sequence 2. A reflector 4 is located at a rear side 12 of the semiconductor layer sequence 2. The reflector 4 is made of a material transparent to the radiation generated during operation. A reflection effect of the reflector 4 is based in particular on a refractive index difference towards the semiconductor layer sequence 2 and/or on total reflection. The rear side 12 is opposite to a light extraction side 10.

[0083] On a side of the reflector 4 facing away from the semiconductor layer sequence 2 an adherent layer 71 is arranged, via which a metal mirror 3 is attached to the reflector 4. The reflector 4, for example, is made of a silicon dioxide layer. The adherent layer 71 is a layer of a transparent conductive oxide, TCO for short, such as zinc oxide or ITO. The metal mirror 3 is made of gold. The semiconductor layer sequence 2 is based on AlInGaAs or on AlInGaP.

[0084] Since the adherent layer 71 is made of a TCO, the adherent layer 71 does not form a tight barrier against the penetration of moisture or other substances harmful to the metal mirror 3. Similarly, penetration of harmful substances for the metal mirror 3 is possible through the reflector 4. Furthermore, there is no additional protection for the metal mirror 3 from the rear side 12 or from side edges.

[0085] This means that moisture or other harmful substances for the metal mirror 3 can penetrate from the side edges of the mirror 3, see path A. A diffusion of harmful materials can also occur from the side via the adherent layer 71, see path B. Corrosion of the metal mirror 3 can occur over a large area through the adherent layer 71 via the reflector 4, see path C. Furthermore, an attack on the metal mirror 3 can occur across the reflector 4 at a through-connection 5, see path D.

[0086] The modification 1′ of FIG. 1, allows only the usage materials such as gold for the metal mirror 3, which show a high stability under the influence of moisture or other environmental influences. However, gold has a comparatively low reflectivity, especially towards shorter wavelengths.

[0087] FIG. 2 shows an exemplary embodiment of an optoelectronic semiconductor chip 1. In contrast to the modification 1′ of FIG. 1, an adhesion promoting layer 7 is present, which also serves as a barrier layer. The adhesion promoting layer 7 is impermeable or essentially impermeable to moisture or other substances harmful to the metal mirror 3. Thus, no moisture or other harmful substances can reach the metal mirror 3 from the side or via the reflector 4. The metal mirror 3 is preferably a silver mirror.

[0088] For example, the adhesion promoting layer 7 is an aluminum oxide layer produced by atomic layer deposition, ALD for short. A thickness of the adhesion promoting layer 7 is preferably at least 1 nm or 5 nm and/or at most 50 nm or 40 nm. In the case of an aluminum oxide layer, the thickness of the adhesion promoting layer 7 is preferably between 20 nm and 40 nm inclusive, in particular around 30 nm.

[0089] The adhesion promoting layer 7 is located directly between the reflector 4, which is for example made of silicon dioxide, and the metal mirror 3. The metal mirror 3 is located on the first side 21 of the semiconductor layer sequence 2. The first side 21 is preferably p-doped.

[0090] On a side facing away from the semiconductor layer sequence 2 there is a protective metallization 6 directly at the metal mirror 3. The protective metallization 6 can be formed by a single metal layer, but preferably the protective metallization 6 is formed by several successive metal layers. For example, protective metallization 6 is a layer stack of Ti-Pt or Ti-Pt-Ti or TiW or Ti-TiW or Cr-Pt or Cr-Pt-Ti.

[0091] A layer of the adhesion promoting layer 7 closest to the metal mirror 3 preferably contains Ti and/or Cr and can serve as an additional adherent layer. Such an adherent layer closest to the metal mirror 3 preferably has a thickness between 1 nm and 10 nm inclusive. A total thickness of the protective metallization 6 is preferably at least 50 nm or 100 nm and/or at most 1.5 .Math.m or 1 .Math.m or 500 nm.

[0092] The protective metallization 6 is preferably dimensionally stable, so that a form of protective metallization 6 does not change or does not change significantly during intendet use and intended assembly of the semiconductor chip 1. In particular, protective metallization 6 is not a solder for mounting the semiconductor chip 1.

[0093] Furthermore, FIG. 2 shows that the semiconductor layer sequence 2 comprises a structuring. This means that the semiconductor layer sequence 2 is 5 thicker in the region of the electrical through-connection than in other regions. By structuring the semiconductor layer sequence 2 in this way, it is possible to ensure that the active zone 23, particularly directly below any metallic current distribution structures 93 on the light extraction side 10, is not or only slightly energized. In addition, such a structuring of the semiconductor layer sequence 2 can increase light extraction efficiency, since light can be deflected or scattered at this structuring. The structuring is optional.

[0094] In the region of the through-connection 5, the metal mirror 3 penetrates the reflector 4. The semiconductor layer sequence 2 is directly electrically contacted by the metal mirror 3. The adhesion promoting layer 7 is only applied to the reflector 4 from the rear side 12, so that side surfaces of the through-connection 5, formed by the metal mirror 3, are free of the adhesion promoting layer 7. In the region of the reflector 4, the metal mirror 3 is thus directly adjacent to the reflector 4 in the lateral direction. Thus, the metal mirror 3 is in direct electrical contact with the semiconductor layer sequence 2.

[0095] The metal mirror 3 may extend with a constant thickness over the semiconductor layer sequence 2. This means that the protective metallization 6 can come relatively close to the semiconductor layer sequence 2 in the region of the through-connection 5. Optionally, it is possible for the protective metallization 6 to serve as a planarization on the rear side 12, in contrast to FIG. 2. In this way a flat mounting side of the semiconductor chip 1 can be achieved on the protective metallization 6. A thickness of the metal mirror 3 is preferably at least 30 nm or 70 nm and/or at most 500 nm or 300 nm.

[0096] It is possible that the reflector 4, the adhesion promoting layer 7 and the protective metallization 6 protrude laterally beyond the semiconductor layer sequence 2. The metal mirror 3 preferably ends laterally with the semiconductor layer sequence 2. At the edge of the semiconductor chip 1, the protective metallization 6 is thus preferably in direct contact with the adhesion promoting layer 7 all around. As a result, the metal mirror 3 is tightly encapsulated laterally by the adhesion promoting layer 7 together with the protective metallization 6.

[0097] This type of encapsulation of the metal mirror 3 makes it possible to use materials such as silver, which are relatively susceptible to moisture, for the metal mirror 3.

[0098] Thus, an increased reflectivity of the metal mirror 3 can be achieved, especially in comparison to gold mirrors.

[0099] As in all other exemplary embodiments, it is possible that the reflector 4 is not formed by a single, comparatively thick radiation-transmitting layer. Layer stacks of layers with alternating high and low refractive indices can be used for the reflector 4, similar to a Bragg mirror.

[0100] The semiconductor layer sequence 2 is based on AlInGaP or on AlInGaAs. In the active zone 23, green light, yellow light, orange light and/or red light is preferably generated during operation. It is also possible that the active zone 23 is configured to generate infrared or near infrared radiation.

[0101] It is possible to form one or more additional layers on the metal mirror 3 towards the protective metallization 6, for example layers of ZnO or other TCO materials or of TiW or other metals. Such an undrawn layer makes it possible to protect the metal mirror 3 from oxidation in subsequent process steps. In particular, a ZnO layer is formed on the side of the Ag metal mirror 3 facing away from the semiconductor layer sequence 2 to prevent oxidation of the silver.

[0102] The adhesion promoting layer 7 can form a multi-layer encapsulation. To simplify the illustration, however, the adhesion promoting layer 7 is always shown as a single layer in the figures.

[0103] The protective metallization 6, the adhesion promoting layer 7 and the reflector 4 can be flush with each other in the lateral direction.

[0104] Unless otherwise indicated, the statements given in connection with FIG. 2 applies to all subsequent exemplary embodiments.

[0105] The exemplary embodiment of FIG. 3 comprises an additional contact layer 8 compared to FIG. 2. The contact layer 8, for example, is made of a transparent conductive oxide such as ITO, but can also be made of a thin metal layer such as Ti, Pt or Pd or Au or Ag. In the case of a metal layer, contact layer 8 preferably has a thickness of 10 nm or 5 nm at most.

[0106] In the case of a TCO, the contact layer 8 preferably has a thickness of at least 10 nm and/or at most 400 nm, in particular between 30 nm and 60 nm inclusive.

[0107] It is possible that the contact layer 8 is limited to the structuring, i.e. to regions of greater thickness of the semiconductor layer sequence 2. Thus the contact layer 8 covers the rear side 12 of the semiconductor layer sequence 2 only in the region of the through-connection 5. Alternatively, it is possible that the contact layer 8 extends continuously over the semiconductor layer sequence 2 and covers the rear side 12 completely or almost completely.

[0108] In the exemplary embodiment of FIG. 4, the through-connection 5 is formed by the protective metallization 6. This means that the metal mirror 3 is completely encapsulated by the adhesion promoting layer 7 together with the protective metallization 6. The metal mirror 3 and the adhesion promoting layer 7 are each applied flat to the reflector 4. Thus, only the protective metallization 6 penetrates the reflector 4 towards the semiconductor layer sequence 2.

[0109] In order to achieve this geometry of the through-connection 5, the adhesion promoting layer 7 and the metal mirror 3 are deposited before the openings of the through-connections 5 are structured. The reflector 4 is also opened. In a first photolithography step, a part of the metal mirror 3 is removed from an edge region of the semiconductor chip 1. In a second photolithography step, the reflector 4, the adhesion promoting layer 7 and the metal mirror 3 are removed to fill the through-connection 5 with a material of protective metallization 6. In a final step, the protective metallization 6 is deposited.

[0110] Here, the encapsulating metal of protective metallization 6 also is the electrical contact metal for the semiconductor layer sequence 2. One advantage of this embodiment is that Ag does not become part of the electrical contact surface and is therefore not exposed to high current densities. However, this places additional restrictions on the choice of material for the protective metallization 6: This material must form a low-resistance electrical contact to the semiconductor layer sequence 2 and enable the encapsulation of the metal mirror 3.

[0111] The exemplary embodiment of FIG. 5 corresponds to that of FIG. 4, wherein the contact layer 8 is also present. The TCO contact layer 8 is restricted to the region of through-connection 5 and to the thicker regions of the semiconductor layer sequence 2 at through-connection 5.

[0112] Thus, the electrical contact to the semiconductor layer sequence is formed by a TCO and the only requirement for the material of the protective metallization 6 is to form an electrical contact to this TCO layer. This has two advantages in particular: Firstly, the Ag of the metal mirror 3 is also completely encapsulated in the electrical contact region. Secondly, the choice of material for protective metallization 6 is less restricted, since the formation of a good metal-TCO contact is much easier than a good metal-semiconductor contact.

[0113] In the exemplary embodiment of FIG. 6 it is shown that the adhesion promoting layer 7 is removed from an edge of the semiconductor chip 1. Here, the adhesion promoting layer 7 preferably protrudes laterally beyond the metal mirror 3, wherein a protrusion of the adhesion promoting layer 7 beyond the metal mirror 3 is preferably at least 0.5 .Math.m or 1 .Math.m or 2 .Math.m and/or at most 10 .Math.m or 5 .Math.m. Thus, the material of the adhesion promoting layer 7 is not exposed laterally. By removing the adhesion promoting layer 7 in the edge region, it is possible that the reflector 4 also has a reduced thickness in the edge region.

[0114] In this case, there is preferably good adhesion of the protective metallization 6 to the reflector 4, but not necessarily to the adhesion promoting layer 7, which is made of aluminum oxide in particular. An additional layer may be applied near the chip edge, not drawn, to achieve increased adhesion between the protective metallization 6 and the reflector 4.

[0115] There are other processing variants which lead to the semiconductor chips 1 described in FIGS. 2 to 6. For example, a structuring of the Ag metal mirror 3 at the edge and in the contact openings can be achieved with two different photolithography steps. It is advantageous to structure the Ag layer immediately before applying the protective metallization 6 in order to avoid a photoresist on the adhesion promoting layer 7 in the chip edge region. A photoresist on the aluminum oxide adhesion promoting layer 7 can negatively influence the adhesion properties after a resist removal step.

[0116] The protective metallization 6 covers an outer edge of the metal mirror 3 as well as side surfaces of the adhesion promoting layer 7 preferably completely. Thus, a tight encapsulation of the adhesion promoting layer 7 together with protective metallization 6 is formed at the edge of the metal mirror 3. At the edge of the semiconductor chip 1, especially all around it, the protective metallization 6 is preferably applied directly on the reflector 4.

[0117] In FIG. 6, the semiconductor chip 1 shows only two of the through-connections 5 in cross-section. It is possible that there is a larger number of through-connections 5 present.

[0118] In the exemplary embodiment of FIG. 7, the semiconductor layer sequence 2 is electrically contacted from the rear side 12 via the optional contact layer 8 and via the protective metallization 6. The metal mirror 3 and the adhesion promoting layer 7 are applied to the side surfaces of the through-connections 5. Thus the metal mirror 3 almost reaches the semiconductor layer sequence 2 and/or the contact layer 8. In particular, the adhesion promoting layer 7 is preferably flush with the protective metallization 6 in a direction towards the semiconductor layer sequence 2. This means that the contact layer 8 can directly border the protective metallization 6 as well as on the adhesion promoting layer 7.

[0119] This geometry from FIG. 7, according to which the adhesion promoting layer 7 covers the side surfaces of the through-connection 5, may also be found in the exemplary embodiments of FIGS. 2 or 3. If the adhesion promoting layer 7 is electrically conductive, the metal mirror 3 or the protective metallization 6 can be completely covered by the adhesion promoting layer 7 in the exemplary embodiments of FIGS. 2 or 3 or in the exemplary embodiment of FIG. 7. This means that even in the region of the through-connections 5, the adhesion promoting layer 7 may then extend continuously over the metal mirror 3 and/or the protective metallization 6. In this case, the adhesion promoting layer 7 lies between the contact layer 8 and the protective metallization 6.

[0120] With this geometry of the metal mirror 3, an enlargement of the reflection region of the metal mirror 3 can be achieved. In this variant, the adhesion promoting layer 7 and the metal mirror 3 are deposited after structuring the dielectric reflector 4, i.e., contact openings are etched. With a second photolithography mask, the adhesion promoting layer 7 and the metal mirror 3 are removed from the electrical contact surface and from the chip edge in a common step. Then the protective metallization 6 is applied.

[0121] The exemplary embodiment of FIG. 8 is based in particular on the exemplary embodiment of FIG. 5. Here, the reflector 4 is removed laterally next to the semiconductor layer sequence 2; this removal is preferably carried out during mesa etching, i.e., during the creation of the separation trenches. From the light extraction side 10, a cover layer 75 extends over the side surfaces of the semiconductor layer sequence 2 up to the adhesion promoting layer 7. The adhesion promoting layer 7 and the cover layer 75 are preferably made of the same material, especially aluminum oxide. The layers 7, 75 are preferably produced by atomic layer deposition. In this way, a particularly tight encapsulation of the metal mirror 3 can also be achieved from the light extraction side 10 and the side surfaces of the semiconductor layer sequence 2.

[0122] Optionally, a moisture protection layer 76 may be applied to the cover layer 75. The moisture protection layer 76 is a nitride like silicon nitride, for example. The moisture protection layer 76 can also be used as an anti-reflective layer, for example together with the cover layer 75. For example, the moisture protection layer 76 is produced by CVD or PVD. The moisture protection layer 76 is preferably thicker than the cover layer 75.

[0123] Such a cover layer 75 and/or such a moisture protection layer 76 may also be present in all exemplary embodiments according to the example of FIG. 8.

[0124] For example, before applying electrical contacts on the light extraction side 10, in particular on the n-doped second side 22 of the semiconductor layer sequence 2, the dielectric reflector 4 is opened in the separation trench so that the adhesion promoting layer 7 deposited on the p-side 21 is exposed. This can be done in a separate photolithography step or in the same photolithography step as the mesa etching.

[0125] Subsequently, the aluminum oxide cover layer 75 is then deposited, which can cover the entire chip surface and which is arranged on the adhesion promoting layer 7 in the separation trench. Thus both layers 7, 75 act as moisture barriers and all moisture paths are closed.

[0126] FIGS. 9 describes a method for producing a semiconductor chip 1. According to FIG. 9A, the semiconductor layer sequence 2 is grown on a growth substrate 20. After growing the semiconductor layer sequence 2, structuring can be optionally carried out so that thicker regions result for the subsequent through-connections 5, not shown in FIG. 9A. It is also optionally possible to apply the contact layer not drawn in FIG. 9A locally or over the entire surface.

[0127] The reflector 4 is created after the semiconductor layer sequence 2 has been grown and optionally after the contact layer has been applied and/or the semiconductor layer sequence 2 has been structured.

[0128] FIG. 9B illustrates that the reflector 4 is preferably covered with the adhesion promoting layer 7. If a structuring not shown in FIG. 9B is present, the adhesion promoting layer 7 preferably forms exactly to such a structuring. The adhesion promoting layer 7 is created by atomic layer deposition.

[0129] Subsequently, the metal mirror 3 is created, for example by evaporation. If necessary, the metal mirror 3 and the adhesion promoting layer 7 can be structured subsequently, i.e., removed in places, not shown in FIG. 9B.

[0130] Neither a structuring for the optional through-connections 5 is drawn in FIGS. 9. The through-connections 5 can be omitted if the reflector 4 and the adhesion promoting layer 7 are electrically conductive. In this case, the reflector 4 and the adhesion promoting layer 7 are made of a transparent conductive oxide or of different transparent conductive oxides, for example.

[0131] In the process step of FIG. 9C it is shown that protective metallization 6 is applied to the metal mirror 3. Again, any structuring of the protective metallization 6 is not illustrated.

[0132] Optionally, protective metallization 6 is followed by a bonding agent 91 like a solder. Furthermore, the semiconductor layer sequence 2 is connected to a carrier 9 on the side of the metal mirror 3. In particular, the carrier 9 may be arranged on the protective metallization 6 by soldering.

[0133] As shown in FIG. 9D, the growth substrate 20 has been removed from the semiconductor layer sequence 2. Optionally, a roughening 92 is created to improve light extraction on the light extraction side 10.

[0134] FIG. 9E illustrates that a current distribution structure 93 may be applied to the light extraction side 10, for example, formed by lattice-like or strip-like metal strips. Alternatively, a layer of a transparent conductive oxide may be used as the current distribution structure.

[0135] Furthermore, FIG. 9E illustrates that optionally the cover layer 75 and/or the moisture protection layer 76 may be applied.

[0136] In general, the requirements for the correct choice of the adhesion promoting layer 7 are as follows: Good adhesion between the dielectric reflector 4 and the metal mirror 3; high uniformity and conformity during application; acting as a moisture barrier, at least when the adhesion promoting layer 7 is placed between other layers; low absorption in the wavelength range emitted by the semiconductor chip 1. As an alternative to ALD, the adhesion promoting layer 7 can also be deposited using a thin-film deposition technique such as Plating or Chemical Vapor Deposition, CVD for short.

[0137] During processing, the metal mirror 3 usually comes into contact with air. To avoid oxidation, the metal mirror 3 should therefore be covered by a thin layer of another material, especially with ZnO, ITO or TiW. This material may finally be removed, if necessary, immediately before the deposition of the protective metallization 6, for example by sputtering. The protective metallization 6 is preferably stable to moisture and adheres well to the metal mirror 3 and to the adhesion promoting layer 7.

[0138] Unless otherwise indicated, the components shown in the figures follow one another, preferably in the order given. Layers not touching each other in the figures are preferably spaced apart. If lines are drawn parallel to each other, the corresponding surfaces are preferably aligned parallel to each other. Likewise, unless otherwise indicated, the relative positions of the drawn components to each other are correctly shown in the figures.

[0139] The invention is not restricted to the exemplary embodiments by the description on the basis of said exemplary embodiments. Rather, the invention encompasses any new feature and also any combination of features, which in particular comprises any combination of features in the patent claims and any combination of features in the exemplary embodiments, even if this feature or this combination itself is not explicitly specified in the patent claims or exemplary embodiments.