DRIVE ACCELERATION CIRCUIT AND CIRCUIT SYSTEM

Abstract

A drive acceleration circuit, including: a drive power supply, including an output end and a reference signal end, where the output end output a drive signal, and the reference signal end is connected to a connection end of a switching device and output a reference signal to the connection end; a first signal route, where the first signal route is connected to the output end of the drive power supply and a control end of the switching device, and is configured to drive, based on the drive signal, the switching device to turn on/off; and a second signal route, connected in parallel with the first signal route, including a drive acceleration unit and a selective conduction unit, one end of the drive acceleration unit is connected to the drive power supply, another end of the drive acceleration unit is connected to the switching device through the selective conduction unit.

Claims

1. A drive acceleration circuit, comprising: a drive power supply, comprising an output end and a reference signal end, wherein the output end is configured to output a drive signal, and the reference signal end is coupled to a connection end of a switching device and is configured to output a reference signal to the connection end; a first signal route, wherein the first signal route is coupled to the output end of the drive power supply and a control end of the switching device, and is configured to drive, based on the drive signal, the switching device to turn on or turn off; and a second signal route, which is connected in parallel with the first signal route, wherein the second signal route comprises a drive acceleration unit and a selective conduction unit, one end of the drive acceleration unit is coupled to the output end of the drive power supply, another end of the drive acceleration unit is coupled to the control end of the switching device through the selective conduction unit, the selective conduction unit is turned on in a time division manner to make the second signal route closed or open, and the drive acceleration unit is configured to accelerate on/off of the switching device based on the drive signal when the second signal route is closed; and the drive acceleration circuit is configured to drive the switching device to turn on or turn off, wherein the switching device has the control end and the connection end.

2. The drive acceleration circuit according to claim 1, wherein the selective conduction unit comprises at least one semiconductor device, one end of the at least one semiconductor device is connected to the drive acceleration unit, another end of the at least one semiconductor device is connected to the control end of the switching device, and the at least one semiconductor device is turned on or off in a time division manner to make the second signal route closed or open.

3. The drive acceleration circuit according to claim 2, wherein the at least one semiconductor device is a zener diode, a transient voltage suppressor, or a switching device.

4. The drive acceleration circuit according to claim 2, wherein the selective conduction unit comprises two semiconductor devices, and either of the semiconductor devices is a zener diode or a transient voltage suppressor; and anodes of the two semiconductor devices are coupled to each other, a cathode of one semiconductor device is coupled to the drive acceleration unit, and a cathode of the other semiconductor device is coupled to the control end of the switching device.

5. The drive acceleration circuit according to claim 3, wherein the selective conduction unit comprises two semiconductor devices, and either of the semiconductor devices is a zener diode or a transient voltage suppressor; and anodes of the two semiconductor devices are coupled to each other, a cathode of one semiconductor device is coupled to the drive acceleration unit, and a cathode of the other semiconductor device is coupled to the control end of the switching device.

6. The drive acceleration circuit according to claim 1, wherein the drive acceleration circuit comprises at least two second signal routes that are connected in parallel, and the at least two second signal routes are closed in a time division manner.

7. The drive acceleration circuit according to claim 2, wherein the drive acceleration circuit comprises at least two second signal routes that are connected in parallel, and the at least two second signal routes are closed in a time division manner.

8. The drive acceleration circuit according to claim 6, wherein the second signal routes are of the same structure.

9. The drive acceleration circuit according to claim 6, wherein the second signal routes have different resistance values.

10. The drive acceleration circuit according to claim 1, wherein the second signal route is configured to be in a closed state when the switching device is in a turn-off delay period, and to be in an open state when the switching device is in a turn-off action period; or the second signal route is configured to be in a closed state both when the switching device is in a turn-off delay period and when the switching device is in a turn-off action period.

11. The drive acceleration circuit according to claim 2, wherein the second signal route is configured to be in a closed state when the switching device is in a turn-off delay period, and to be in an open state when the switching device is in a turn-off action period; or the second signal route is configured to be in a closed state both when the switching device is in a turn-off delay period and when the switching device is in a turn-off action period.

12. The drive acceleration circuit according to claim 1, wherein the second signal route is configured to be in a closed state when the switching device is in a turn-on delay period, and to be in an open state when the switching device is in a turn-on action period; or the second signal route is configured to be in a closed state both when the switching device is in a turn-on delay period and when the switching device is in a turn-on action period.

13. The drive acceleration circuit according to claim 2, wherein the second signal route is configured to be in a closed state when the switching device is in a turn-on delay period, and to be in an open state when the switching device is in a turn-on action period; or the second signal route is configured to be in a closed state both when the switching device is in a turn-on delay period and when the switching device is in a turn-on action period.

14. The drive acceleration circuit according to claim 1, wherein the drive acceleration unit comprises any one or combination of a resistor, a capacitor, and a diode, one end of one of the resistor, the capacitor, and the diode or one end of any combination of the resistor, the capacitor, and the diode that are connected in series or parallel is coupled to the output end of the drive power supply, and another end thereof is coupled to the selective conduction unit.

15. The drive acceleration circuit according to claim 14, wherein the first signal route comprises a first resistor, one end of the first resistor is connected to the output end of the drive power supply, and another end of the first resistor is connected to the control end of the switching device; and the drive acceleration unit comprises a second resistor, wherein one end of the second resistor is connected to the output end of the drive power supply, and another end of the second resistor is connected to the selective conduction unit.

16. The drive acceleration circuit according to claim 15, wherein a resistance value of the first resistor is greater than a resistance value of the second resistor.

17. The drive acceleration circuit according to claim 16, wherein the drive acceleration unit further comprises a capacitor that is connected in series with the second resistor, the one end of the second resistor is connected to the output end of the drive power supply, the another end of the second resistor is connected to the capacitor, another end of the capacitor is connected to the selective conduction unit, and the capacitor is configured to perform charging or discharging when the second signal route is closed.

18. The drive acceleration circuit according to claim 17, wherein the drive acceleration unit further comprises a third resistor, the third resistor is connected in parallel with the capacitor, one end of the third resistor is connected to the second resistor, another end of the third resistor is connected to the selective conduction unit, and the third resistor and the capacitor are comprised in the second signal route in a time division manner.

19. The drive acceleration circuit according to claim 18, wherein a sum of the resistance value of the second resistor and a resistance value of the third resistor is greater than the resistance value of the first resistor.

20. A circuit system, comprising: a switching device, which has a control end and a connection end; and a drive acceleration circuit, wherein the drive acceleration circuit comprises: a drive power supply, comprising an output end and a reference signal end, wherein the output end is configured to output a drive signal, and the reference signal end is coupled to the connection end of the switching device and is configured to output a reference signal to the connection end; a first signal route, wherein the first signal route is coupled to the output end of the drive power supply and the control end of the switching device, and is configured to drive, based on the drive signal, the switching device to turn on or turn off; and a second signal route, which is connected in parallel with the first signal route, wherein the second signal route comprises a drive acceleration unit and a selective conduction unit, one end of the drive acceleration unit is coupled to the output end of the drive power supply, another end of the drive acceleration unit is coupled to the control end of the switching device through the selective conduction unit, the selective conduction unit is turned on in a time division manner to make the second signal route closed or open, and the drive acceleration unit is configured to accelerate on/off of the switching device based on the drive signal when the second signal route is closed; and the drive acceleration circuit is configured to drive the switching device to turn on or turn off, wherein the switching device has the control end and the connection end; and the drive acceleration circuit is coupled to the control end and the connection end of the switching device, and is configured to accelerate an on/off process of the switching device.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0033] FIG. 1 is a schematic diagram of an I-V curve of a switching device when a drive power supply outputs a drive signal with a large pulse;

[0034] FIG. 2 is a schematic diagram of an I-V curve of a switching device when a drive power supply outputs a drive signal with a small pulse;

[0035] FIG. 3 is a schematic diagram of a modular structure of a circuit system according to an embodiment of this application;

[0036] FIG. 4 is a schematic diagram of a circuit structure of a circuit system according to an embodiment of this application;

[0037] FIG. 5 is a schematic diagram of a structure of an equivalent circuit of the circuit system in FIG. 4 in a turn-on delay period of a switching device;

[0038] FIG. 6 is a schematic diagram of a structure of an equivalent circuit of the circuit system in FIG. 4 in a turn-on action period of a switching device;

[0039] FIG. 7 is a schematic diagram of a structure of an equivalent circuit of the circuit system in FIG. 4 in a turn-off delay period of a switching device;

[0040] FIG. 8 is a schematic diagram of a structure of an equivalent circuit of the circuit system in FIG. 4 in a turn-off action period of a switching device;

[0041] FIG. 9 is a schematic diagram of a circuit structure of a circuit system according to an embodiment of this application;

[0042] FIG. 10 is a schematic diagram of a circuit structure of a circuit system according to another embodiment of this application;

[0043] FIG. 11 is a schematic diagram of a circuit structure of a circuit system according to another embodiment of this application;

[0044] FIG. 12 is a schematic diagram of a circuit structure of a circuit system according to another embodiment of this application;

[0045] FIG. 13 is a schematic diagram of a circuit structure of a circuit system according to another embodiment of this application;

[0046] FIG. 14 is a schematic diagram of a circuit structure of a circuit system according to an embodiment of this application;

[0047] FIG. 15 is a schematic diagram of a circuit structure of a circuit system according to an embodiment of this application;

[0048] FIG. 16 is a schematic diagram of a circuit structure of a circuit system according to another embodiment of this application;

[0049] FIG. 17 is a schematic diagram of a circuit structure of a circuit system according to an embodiment of this application;

[0050] FIG. 18 is a schematic diagram of a circuit structure of a circuit system according to an embodiment of this application; and

[0051] FIG. 19 is a schematic diagram of a circuit structure of a circuit system according to another embodiment of this application.

REFERENCE NUMERALS

[0052]

TABLE-US-00001 Circuit system 1, 2, and 3 Drive acceleration circuit 10 Drive power supply 11 Output end out Basic drive unit 12 Drive acceleration unit 13 Selective conduction unit 14 First signal route 15 Second signal route 16 First resistor R1 Second resistor R2 Third resistor R3 Capacitor C First zener diode V.sub.Z1 Second zener diode V.sub.Z2 Switching device 20 Control end G Connection end E Reference signal end GND Period T.sub.1, T.sub.2, T.sub.4, and T.sub.5

DETAILED DESCRIPTION

[0053] The following describes embodiments of this application with reference to accompanying drawings of embodiments of this application.

[0054] It should be noted that when an element is considered to be connected to another element, it may be directly connected to the another element, or an element disposed in between may coexist. When one or more elements or units are considered to constitute or serve as another element, it only indicates that the relationship exists in the described embodiment.

[0055] Unless otherwise specified, all the technical and scientific terms used in this specification have the same meanings as those generally understood by technical personnel in the technical field of this application. Terms used in this specification of this application are merely intended for the purpose of describing specific embodiments rather than limiting this application. The term and/or used in this specification includes any and all combinations of one or more associated items that are listed.

[0056] This application provides a circuit system that includes a drive acceleration circuit and a switching device. The circuit system is applied to a drive circuit of a semiconductor switching device. The drive acceleration circuit is configured to drive the switching device to turn on and turn off. In this application, the switching device is a semiconductor switching device, for example, an insulated gate bipolar transistor, a metal-oxide-semiconductor field-effect transistor, or a new-type wide bandgap semiconductor. The switching device has a control end. The drive acceleration circuit outputs a drive signal to the control end of the switching device, to drive the switching device to turn on and turn off.

[0057] In an embodiment this application, for an I-V curve of an entire process in which the switching device starts to turn on until turn-off ends, refer to FIG. 1. In FIG. 1, a horizontal coordinate indicates time, and a vertical coordinate indicates a voltage V.sub.G of the control end of the switching device. T.sub.1 is defined as a turn-on delay period of the switching device, T.sub.2 is defined as a turn-on action period of the switching device, T.sub.4 is defined as a turn-off delay period of the switching device, and T.sub.5 is defined as a turn-off action period of the switching device. At a moment when the period T.sub.5 ends, the switching device has been completely turned off. However, in a period following the period T.sub.5, V.sub.G still continues to drop, until V.sub.G reaches a low level (5V) of the drive signal.

[0058] In an embodiment of this application, a threshold voltage of the switching device is +5V. In other words, when the switching device reaches a miller plateau, a voltage V.sub.G at a gate is +5V. In other words, when V.sub.G reaches +5V, the switching device is turned on; and when V.sub.G is less than +5V, the switching device is turned off. The voltage of the drive signal periodically jumps between +15V and 5V. However, because of a working characteristic of the semiconductor switching device, V.sub.G of the switching device can hardly be switched instantaneously, but it takes some time to complete voltage switching. For example, in the turn-on delay period T.sub.1 of the switching device, V.sub.G gradually increases from 5V to +5V; and in the turn-off delay period T.sub.4 of the switching device, V.sub.G gradually decreases from +15V to +5V. Existence of the turn-on delay period T.sub.1 and the turn-off delay period T.sub.4 affects turn-on and turn-off speeds of the switching device.

[0059] In an embodiment this application, the basic drive unit 12 is configured to drive the switching device to turn on or turn off. The drive acceleration unit 13 is configured to be turned on in the turn-on delay period T.sub.1 and the turn-off delay period T.sub.4 of the switching device, to shorten the turn-on delay period T.sub.1 and the turn-off delay period T.sub.4 of the switching device, thereby reducing a turn-on delay and a turn-off delay.

[0060] When a pulse width is large, an I-V curve of the switching device is shown in FIG. 1. Refer to FIG. 2. When a pulse width of the drive signal is small, in some cases, when V.sub.G just reaches +5V, in other words, when the switching device is in the turn-on action period T.sub.2 and the switching device is just turned on, a level of the drive signal jumps from +15V to 5V, and the switching device immediately starts to turn off. If the drive acceleration unit 13 drives the switching device at this time, the miller plateau is directly accelerated. This speeds up a normal turn-off process of the switching device, and a current change rate suddenly increases, greatly increasing stress of the switching device and causing a risk of stress to the switching device.

[0061] It can be learned that delays (the turn-on delay period T.sub.1 and the turn-off delay period T.sub.4) of specific duration exist both in turn-on and turn-off processes of the switching device. If the turn-on delay period T.sub.1 and the turn-off delay period T.sub.4 of the switching device are shortened, this is conducive to reducing turn-on and turn-off delays of the switching device, thereby speeding up turn-on and turn-off speeds. However, when the pulse width of the drive signal is small, the miller plateau of the switching device is consequently accelerated. In other words, the normal turn-on action period T.sub.2 and turn-off action period T.sub.5 of the switching device are also shortened. This brings a risk of increased stress.

[0062] In an embodiment this application, a drive signal whose pulse width is greater than a sum of the turn-on delay period T.sub.1 and the turn-on action period T.sub.2 of the switching device is defined as a drive signal with a large pulse, and a drive signal whose pulse width is less than or equal to a sum of the turn-on delay period T.sub.1 and the turn-on action period T.sub.2 of the switching device is defined as a drive signal with a small pulse.

Embodiment 1

[0063] In this embodiment, a drive acceleration circuit 10 performs acceleration in a turn-on delay period T.sub.1 and a turn-off delay period T.sub.4 of a switching device, and is disconnected in a turn-on action period T.sub.2 and a turn-off action period T.sub.5 of the switching device. This resolves the foregoing technical problem that when the pulse width of the drive signal is small, stress of the switching device is consequently increased.

[0064] Refer to FIG. 3. A circuit system 1 of this embodiment includes the drive acceleration circuit 10 and a switching device 20. In this embodiment, the switching device 20 has a control end G. The drive acceleration circuit 10 is coupled to the control end G of the switching device 20 to output a drive signal, thereby driving the switching device 20 to turn on or turn off. In this embodiment, as an example for description, the switching device 20 is an insulated gate bipolar transistor, and the control end G is a gate of the insulated gate bipolar transistor. The drive acceleration circuit 10 includes a drive power supply 11, a basic drive unit 12, a drive acceleration unit 13, and a selective conduction unit 14. In this embodiment, the basic drive unit 12 constitutes a first signal route 15, and the drive acceleration unit 13 and the selective conduction unit 14 serve as a second signal route 16 after being connected in series. The first signal route 15 and the second signal route 16 are configured to: when closed, provide a charging and discharging path for the switching device 20. The drive acceleration unit 13 and the selective conduction unit 14 are connected in series, and then connected to the basic drive unit 12 in parallel. In other words, the first signal route 15 and the second signal route 16 are connected in parallel.

[0065] The drive power supply 11 has an output end OUT and a signal reference end GND. The output end OUT is configured to output a drive signal, and the signal reference end GND is configured to output a reference signal that serves as a reference ground. The switching device 20 further includes a connection end E. In this embodiment, the connection end is an emitter. In another embodiment, the connection end E may alternatively be a collector. The signal reference end GND is coupled to the connection end E. The drive signal output by the output end OUT is applied to the control end G of the switching device 20. In this embodiment, the selective conduction unit 14 is configured to control a working status of the second signal route 16. In other words, the second signal route 16 is controlled by the selective conduction unit 14 to be in a closed or open state. In this way, the drive acceleration unit 13 is included in the drive acceleration circuit 10 or excluded from the drive acceleration circuit 10. (In other words, the drive acceleration unit 13 is connected to the drive acceleration circuit 10 or disconnected from the drive acceleration circuit 10.)

[0066] In this embodiment, the drive signal is a pulse signal. When the drive signal is in a first state (for example, a high level state, such as 15V), the switching device 20 is driven to turn on. When the drive signal is in a second state (for example, at a low level, such as 5V), the switching device 20 is driven to turn off.

[0067] In this embodiment, the selective conduction unit 14 controls the working status of the second signal route 16, so that the drive acceleration unit 13 is included in the turn-on delay period T.sub.1 and the turn-off delay period T.sub.4 of the switching device 20; and the selective conduction unit 14 controls the working status of the second signal route 16, so that the drive acceleration unit 13 is excluded in the turn-on action period T.sub.2 and the turn-off action period T.sub.5 of the switching device 20. In other words, the selective conduction unit 14 controls the second signal route 16 to be in a closed state in the turn-on delay period T.sub.1 and the turn-off delay period T.sub.4 of the switching device 20; and the selective conduction unit 14 controls the second signal route 16 to be in an open state in the turn-on action period T.sub.2 and the turn-off action period T.sub.5 of the switching device 20.

[0068] The basic drive unit 12 and the drive acceleration unit 13 include one of or any combination of a resistor, a capacitor, and a diode. There is one or more resistors, capacitors, and diodes. The one or more resistors, capacitors, and diodes may be connected in series or in parallel.

[0069] Refer to FIG. 4. In this embodiment, the basic drive unit 12 includes a first resistor R1, the drive acceleration unit 13 includes a second resistor R2 and a capacitor C, and the selective conduction unit 14 includes a first zener diode V.sub.Z1 and a second zener diode V.sub.Z2. The second resistor R2, the capacitor C, the first zener diode V.sub.Z1, and the second zener diode V.sub.Z2. are consecutively connected in series. The second resistor R2 is further coupled to the output end OUT of the drive power supply 11. The second zener diode V.sub.Z2 is further coupled to the control end G of the switching device 20. In this embodiment, a negative electrode of the first zener diode V.sub.Z1 is coupled to the output end OUT of the drive power supply 11, and a positive electrode of the first zener diode V.sub.Z1 is coupled to the switching device 20. A positive electrode of the second zener diode V.sub.Z2 is coupled to the output end OUT of the drive power supply 11, and a negative electrode of the second zener diode V.sub.Z2 is coupled to the switching device 20. The first resistor R1 is coupled between the output end OUT of the drive power supply 11 and the control end G of the switching device 20, and is connected in parallel with the second resistor R2, the capacitor C, the first zener diode V.sub.Z1, and the second zener diode V.sub.Z2.

[0070] In this embodiment, a working principle of the circuit system 1 shown in FIG. 4 is illustrated by using an example in which a threshold voltage of the switching device 20 is 5V, and breakdown voltages of the first zener diode V.sub.Z1 and the second zener diode V.sub.Z2 are 10V.

[0071] Refer to FIG. 5. The drive signal is in a high level (+15V) state in the turn-on delay period T.sub.1. When driven by the drive signal, a voltage V.sub.G of the control end G of the switching device 20 gradually increases from 5V to the threshold voltage of +5V (which is a miller plateau of the switching device 20 in this embodiment). At this time, the first zener diode V.sub.Z1 enters a reverse breakdown state, with a working voltage of 10V. The second zener diode V.sub.Z2 enters a forward conduction state, and acts as a diode. At this time, both the first signal route 15 and the second signal route 16 are in a closed state. In the second signal route 16, the second resistor R2 and the capacitor C can provide a sufficient gate drive peak current. In this way, the switching device 20 is charged by using the first signal route 15, and the charging is accelerated by using the second signal route 16, to accelerate a turn-on delay process of the switching device 20.

[0072] Refer to FIG. 6. A voltage V.sub.G of the control end G has reached the threshold voltage of +5V of the switching device in the turn-on action period T.sub.2. At this time, the switching device 20 is turned on, and the first zener diode V.sub.Z1 in the selective conduction unit 14 is cut off, so that the second signal route 16 is in an open state. At this time, only the first signal route 15 is closed, and the switching device 20 is charged only by using the first signal route 15. Therefore, a charging speed is reduced in comparison with that in the turn-on delay period, and a small current change rate is maintained for the switching device 20, thereby avoiding a risk of stress.

[0073] During normal operation of the switching device 20, the first signal route 15 constantly stays in a closed state, and the second signal route 16 constantly stays in an open state. Although the voltage V.sub.G of the control end G has exceeded +5V and the switching device 20 has been turned on, to prevent the switching device 20 from being erroneously turned off due to fluctuation of the drive signal, a high level of the drive signal needs to be greater than +5V. Therefore, the voltage V.sub.G of the control end G continues to increase to +15V after reaching the miller plateau.

[0074] Refer to FIG. 7. The drive signal is in a low level (5V) state in the turn-off delay period T.sub.4. When driven by the drive signal, a voltage of the control end G of the switching device 20 gradually decreases from +15V to +5V. At this time, the first zener diode V.sub.Z1 enters a forward conduction state and acts as a diode. The second zener diode V.sub.Z2 enters a reverse breakdown state, with a working voltage of 10V. At this time, both the first signal route 15 and the second signal route 16 are in a closed state. In the second signal route 16, the second resistor R2 and the capacitor C can provide a discharging path that has a low impedance, to accelerate a turn-off delay process of the switching device 20.

[0075] Refer to FIG. 8. The second zener diode V.sub.Z2 is cut off in the turn-off action period T.sub.5, so that the second signal route 16 is in an open state. At this time, only the first signal route 15 is closed, and the switching device 20 is discharged only by using the first signal route 15. A discharging speed is reduced, and a small current change rate is maintained for the switching device 20, thereby avoiding a risk of stress.

[0076] Although the voltage V.sub.G of the control end G is already greater than +5V in a period following the turn-off action period T.sub.5 of the switching device 20 and the switching device 20 has been turned off, to prevent the switching device 20 from being erroneously turned on due to fluctuation of the drive signal, a low level of the drive signal needs to be less than +5V. Therefore, the voltage V.sub.G of the control end G continues to decrease to 5V after decreasing to less than +5V.

[0077] It should be understood that in another embodiment, a voltage V.sub.G of the control end G may not be +15V during normal operation of the switching device 20, and a voltage V.sub.G of the control end G may not be 5V when the switching device 20 is turned off. The foregoing voltage values in this embodiment are merely intended for illustrative description.

[0078] It can be learned, from the foregoing working process of the circuit system 1, that the drive acceleration unit 13 accelerates normal turn-on delay and turn-off delay processes in the turn-on delay period T.sub.1 and the turn-off delay period T.sub.4, but does not accelerate normal turn-on and turn-off processes of the switching device 20. When the switching device 20 reaches the miller plateau, a corresponding zener diode (V.sub.Z1 or V.sub.Z2) in the selective conduction unit 14 is cut off, to control the second signal route 16 in which the drive acceleration unit 13 is located to be in an open state, so that charging and discharging processes of the switching device 20 are not accelerated, achieving a stable current change rate for the switching device 20. This can effectively suppress a voltage spike and reduce a risk of stress to the switching device 20, thereby solving the foregoing technical problem that stress of the switching device 20 is prone to increase when the drive signal has a small pulse width.

[0079] To accurately control the second signal route 16 to be in an open state in the turn-on action period T.sub.2 and the turn-off action period T.sub.5 of the switching device 20 (namely when the switching device 20 is at the miller plateau), zener diodes V.sub.Z1 and V.sub.Z2 with matching working voltages need to be selected based on the threshold voltage of the switching device 20 and the high level and the low level of the drive signal.

[0080] In this embodiment, turn-on and turn-off speeds of the switching device 20 are related to values of the capacitor C, the first resistor R1, and the second resistor R2. A capacitor C with a specific capacitance value and a first resistor R1 and a second resistor R2 with specific resistance values may be selected to achieve specific turn-on and turn-off speeds. A larger capacitance value and a smaller resistance value mean larger charging and discharging currents and faster charging and discharging speeds of the switching device 20. A smaller capacitance value and a larger resistance value mean smaller charging and discharging currents and slower charging and discharging speeds of the switching device 20.

[0081] In this embodiment, a resistance value of the first resistor R1 is greater than a resistance value of the second resistor R2. In this way, when the second signal route 16 is open, and the first signal route 15 is used for charging and discharging, charging and discharging currents are small, and a current change rate is small. This is conducive to normal turn-on and turn-off of the switching device 20, thereby reducing a risk of stress to the switching device 20.

[0082] In a variant embodiment, the first zener diode V.sub.Z1 and/or the second zener diode V.sub.Z2 may alternatively be replaced by another semiconductor device such as a transient voltage suppressor (Transient Voltage Suppressor, TVS) or a switching device. In another variant embodiment, circuit structures of the basic drive unit 12 and the drive acceleration unit 13 may alternatively be different, provided that a charging and discharging path can be provided.

[0083] In this embodiment, by using a working characteristic of the first zener diode V.sub.Z1, the first zener diode V.sub.Z1 is made to enter a reverse breakdown state in the turn-on delay period T.sub.1 of the switching device 20 and to be cut off in the turn-on action period T.sub.2, thereby controlling the drive acceleration unit 13 to be included in the drive acceleration circuit 10 or excluded from the drive acceleration circuit 10. Similarly, by using a working characteristic of the second zener diode V.sub.Z2, the second zener diode V.sub.Z2 is made to enter a reverse breakdown state in the turn-off delay period T.sub.4 of the switching device 20 and to be cut off in the turn-off action period T.sub.5, thereby controlling the drive acceleration unit 13 to be included in the drive acceleration circuit 10 or excluded from the drive acceleration circuit 10.

[0084] In another variant embodiment, the selective conduction unit 14 includes the first zener diode V.sub.Z1 or the second zener diode V.sub.Z2, rather than including the first zener diode V.sub.Z1 and the second zener diode V.sub.Z2. In other words, in another variant embodiment, the selective conduction unit 14 may include only one of the first zener diode V.sub.Z1 and the second zener diode V.sub.Z2. For example, refer to FIG. 9. When the selective conduction unit 14 includes the first zener diode V.sub.Z1, the selective conduction unit 14 is configured to control a working status of the second signal route 16 in a turn-on process (including the turn-on delay period T.sub.1 and the turn-on action period T.sub.2) of the switching device 20. For example, refer to FIG. 10. When the selective conduction unit 14 includes the second zener diode V.sub.Z2, the selective conduction unit 14 is configured to control a working status of the second signal route 16 in a turn-off process (including the turn-off delay period T.sub.4 and the turn-off action period T.sub.5) of the switching device 20.

[0085] In the variant embodiments shown in FIG. 9 and FIG. 10, the selective conduction unit 14 includes only one of the first zener diode V.sub.Z1 and the second zener diode V.sub.Z2. This is conducive to meeting requirements of switching devices 20 in different circuit systems.

[0086] Refer to FIG. 11. In another variant embodiment, the drive acceleration unit 13 does not include a capacitor C. In this variant embodiment, a resistance value of the second resistor R2 is far less than a resistance value of the first resistor R1. Therefore, charging and discharging currents of the second signal route 16 are far greater than charging and discharging currents of the first signal route 15, and the switching device 20 can be rapidly charged and discharged by using the second signal route 16, thereby achieving rapid turn-on or turn-off.

[0087] Refer to FIG. 12 and FIG. 13. In a variant embodiment in which the drive acceleration unit 13 does not include a capacitor C, selective conduction unit 14 may include only one of the first zener diode V.sub.Z1 and the second zener diode V.sub.Z2, as shown in FIG. 8 and FIG. 10. Details are not described herein again.

[0088] In summary, the circuit system 1 of this embodiment includes the drive acceleration circuit 10. The drive acceleration circuit 10 includes the selective conduction unit 14. The selective conduction unit 14 is configured to control the drive acceleration unit 13 to be in a closed state in the turn-on delay period T.sub.1 and the turn-off delay period T.sub.4, to shorten the turn-on delay period T.sub.1 and the turn-off delay period T.sub.4. The selective conduction unit 14 is further configured to control the drive acceleration unit 13 to be in an open state in the turn-on action period T.sub.2 and the turn-off action period T.sub.5, so that the turn-on action period T.sub.2 and the turn-off action period T.sub.5 are not shortened. In this way, the drive acceleration circuit 10 implements selective acceleration of charging and discharging processes of the switching device 20. This further accelerates normal turn-on and turn-off processes while ensuring shortened turn-on and turn-off delays. This effectively suppresses a voltage spike and reduces a risk of stress to the switching device 20, thereby solving the foregoing technical problem that stress of the switching device is prone to increase when the drive signal has a small pulse width.

Embodiment 2

[0089] Refer to FIG. 14. A main difference of a circuit system 2 in this embodiment from the circuit system 1 in the embodiments shown in FIG. 4 to FIG. 10 lies in that a drive acceleration unit 13 in a second signal route 16 further includes a third resistor R3. The third resistor R3 is connected in series with a second resistor R2, and the third resistor R3 is connected in parallel with a capacitor C. In this embodiment, a resistance value of the third resistor R3 is far greater than resistance values of a first resistor R1 and the second resistor R2, and the resistance value of the second resistor R2 is less than the resistance value of the first resistor R1. In this embodiment, the capacitor C and the third resistor R3 are included in the second signal route 16 in a time division manner.

[0090] In this embodiment, in a turn-on delay period T.sub.1, the switching device 20 is charged by using a first signal route 15 and the second signal route 16. Specifically, the switching device 20 is charged by using the second resistor R2 and the capacitor C in the second signal route 16, so that the drive acceleration unit 13 accelerates a turn-on process of the switching device 20 in the turn-on delay period T.sub.1.

[0091] In a turn-on action period T.sub.2, the capacitor C in the drive acceleration unit 13 has been charged to a specific voltage. At this time, a path including the second resistor R2 and the third resistor R3 is closed. A total resistance value of the second signal route 16 is a sum of the resistance values of the second resistor R2 and the third resistor R3, and is far greater than the resistance value of the first resistor R1 in the first signal route 15. At this time, although both the first signal route 15 and the second signal route 16 are in a closed state, a resistance value on the second signal route 16 is far greater than a resistance value on the first signal route 15. Therefore, a charging current on the second signal route 16 is far smaller than a charging current on the first signal route 15. In other words, at this time, the switching device 20 is mainly charged by using the first signal route 15. A current change rate is small, so that normal turn-on of the switching device 20 is not affected.

[0092] In a turn-off delay period T.sub.4, a drive signal is jumped to a low level, and the switching device 20 starts to perform discharging. At this time, both the first signal route 15 and the second signal route 16 are closed. Specifically, the switching device 20 is discharged by using the second resistor R2 and the capacitor C in the second signal route 16, so that the drive acceleration unit 13 accelerates a discharging process of the switching device 20 in the turn-off delay period T.sub.4.

[0093] In a turn-off action period T.sub.5, the capacitor C in the drive acceleration unit 13 is in an open state. At this time, a path including the second resistor R2 and the third resistor R3 is closed, and the switching device 20 is also charged and discharged by using the first signal route 15 and the second signal route 16. Specifically, the switching device 20 is charged and discharged by using the second resistor R2 and the third resistor R3 in the second signal route 16. A total resistance value of the second signal route 16 is far greater than a total resistance value of the first signal route 15. Therefore, a discharging current of the first signal route 15 is far greater than a discharging current of the second signal route 16. In other words, the switching device 20 is mainly discharged by using the first signal route 15. A current change rate is small, so that normal turn-off of the switching device 20 is not affected.

[0094] In other words, in this embodiment, even if the second signal route 16 is not disconnected by the selective conduction unit 14, after the capacitor C is fully charged, the capacitor C can be excluded from the second signal route 16, so that the third resistor R3 is included, in place of the capacitor C, in the second signal route 16. Therefore, this can also effectively improve turn-on and turn-off speeds of the switching device 20.

[0095] Refer to FIG. 15 and FIG. 16. In a variant embodiment of this embodiment, the selective conduction unit 14 may include only one of the first zener diode V.sub.Z1 and the second zener diode V.sub.Z2, similar to the embodiments shown in FIG. 9 and FIG. 10. Details are not described herein again.

[0096] In summary, the circuit system 2 and a drive acceleration circuit 10 of this embodiment can achieve all beneficial effects described in Embodiment 1. In addition, when the second signal route 16 is not disconnected by the selective conduction unit 14, a charging/discharging status of the capacitor C may be further used to control the second signal route 16 to be included or excluded.

Embodiment 3

[0097] Refer to FIG. 17. A main difference of a circuit system 3 in this embodiment from the circuit system 1 in Embodiment 1 and the circuit system 2 in Embodiment 2 lies in that a drive acceleration circuit 10 includes at least two second signal routes 16. The second signal routes 16 are connected with each other in parallel. In this embodiment, as an example for description, two second signal routes 16 are included.

[0098] In this embodiment, the second signal routes 16 work in a time division manner. When closed, the second signal routes 16 have different charging/discharging currents. In this embodiment, second resistors R2 with different resistance values or/and capacitors C with different capacitance values are selected, so that the second signal routes 16 have different charging/discharging currents when closed. In this embodiment, a first zener diode V.sub.Z1 and a second zener diode V.sub.Z2 in the selective conduction unit 14 have different breakdown voltages, so that the second signal routes 16 are closed in a time division manner. In other words, the second signal routes 16 are not closed at the same time.

[0099] In this way, in a turn-on delay period T.sub.1 and a turn-off delay period T.sub.4, the two second signal routes 16 are controlled, by using the selective conduction unit 14 in each second signal route 16, to be closed in a time division manner. In this way, the switching device 20 has different charging/discharging speeds in sub-periods of the turn-on delay period T.sub.1 and the turn-off delay period T.sub.4. For example, for each second signal route 16, a charging/discharging current when the second signal route 16 is closed may be set, to control charging/discharging speeds of the switching device 20 in the sub-periods of the turn-on delay period T.sub.1 and the turn-off delay period T.sub.4 to gradually decrease, until a charging/discharging speed at a miller plateau is reached.

[0100] In the drive acceleration circuit 10 of this embodiment, a structure of each second signal route 16 may be the same as a structure of any second signal route 16 described in Embodiment 1 and Embodiment 2, for example, structures in examples shown in FIG. 18 and FIG. 19. Details are not described herein again.

[0101] The circuit system 3 and the drive acceleration circuit 10 of this embodiment can achieve all beneficial effects described in Embodiment 1 and Embodiment 2. In addition, the switching device 20 may further be controlled to have gradient charging/discharging speeds in turn-on and turn-off processes.

[0102] A person with ordinary skills in the art should be aware that the foregoing implementations are merely intended for describing the present invention, rather than for limiting the present invention. Any appropriate modifications and changes made to the foregoing embodiments within the scope of the present invention shall fall within the protection scope claimed by the present invention.