Deadtime automatic-optimization system for flyback power supply having primary-side feedback in CCM, control system and method for flyback power supply having primary-side feedback in CCM

Abstract

An automatic dead zone time optimization system in a primary-side regulation flyback power supply continuous conduction mode (CCM), including a closed loop formed by a control system, including a single output digital to analog converter (DAC) midpoint sampling module, a digital control module, a current detection module, a dead zone time calculation module and a pulse-width modulation (PWM) driving module, and a controlled synchronous rectification primary-side regulation flyback converter. A primary-side current is sampled using a DAC Sampling mechanism to calculate a secondary-side average current, so as to obtain a primary-side average current and a secondary-side average current, in the case of CCM. A secondary-side current is input into the dead zone time calculation module to obtain a reasonable dead zone time; and the PWM driving module is jointly controlled by a primary-side regulation loop and the obtained dead zone time.

Claims

1. A deadtime automatic-optimization system of a flyback power supply having a primary-side feedback in a continuous conduction mode (CCM), comprising: a control system consisting of a single-output digital to analog converter (DAC) midpoint sampling module, a digital control module, a current detection module, a deadtime calculation module, and a pulse-width modulation (PWM) driving module, the control system forming a closed loop with a main topology of a controlled flyback converter having a synchronous-rectification primary-side feedback; wherein the single-output DAC midpoint sampling module is configured to sample a voltage signal V.sub.sense(t.sub.mid) on an auxiliary winding at a midpoint instant of a secondary-side current reset time T.sub.r, to output to the digital control module; the digital control module is configured to calculate an error e(n) between the voltage signal V.sub.sense(t.sub.mid) and a system-predetermined fixed value V.sub.REF and calculate an input voltage control amount V.sub.c(n) for the PWM driving module by using proportion and integration to output to the PWM driving module; the digital control module is configured to output a digital value V.sub.peak_d of a peak voltage on a primary-side current sampling resistor R.sub.cs according to a value of the error e(n); the digital value V.sub.peak_d and a voltage V.sub.cs at two terminals of the primary-side current sampling resistor R.sub.cs are configured to output to the current detection module; the current detection module is configured to obtain a primary-side average current I.sub.mid_p and a secondary-side average current I.sub.s(t.sub.mid) in the CCM indirectly by sampling and calculating in a pure digital manner through a DAC, and output the secondary-side average current I.sub.x(t.sub.mid) as an output signal to the deadtime calculation module to calculate a reasonable deadtime t.sub.d between a turn-off of a secondary-side rectifier SR and a turn-on of a primary-side switching transistor SW; the PWM driving module is configured to generate duty cycle control signals duty and duty_SR under a common control of the deadtime t.sub.d output by the deadtime calculation module and the control amount V.sub.c(n) output by the digital control module; and the duty cycle control signals duty and duty_SR are configured to control switching of the primary-side switching transistor SW and the secondary-side rectifier SR, respectively, to implement an automatic optimization of the deadtime of the flyback power supply having the synchronous-rectification primary-side feedback in the CCM.

2. The deadtime automatic-optimization system of claim 1, wherein the single-output DAC midpoint sampling module comprises: a first DAC, a triangular wave generator, a first comparator CMP1, a second comparator CMP2, a counter, and a feedback amount calculation module; wherein a voltage signal V.sub.sense on the auxiliary winding is connected as an input signal to positive terminals of the first comparator CMP1 and the second comparator CMP2, respectively; a negative terminal of the first comparator CMP1 is connected to a voltage signal V.sub.ref_slope of a single slope digital wave obtained by superimposition of a digital single sloping wave output by the triangular wave generator and an analog reference voltage output by the first DAC; a negative terminal of the second comparator CMP2 is connected to zero voltage; the first comparator CMP1 and the second comparator CMP2 respectively output a feedback comparison signal V.sub.ref_comp and a zero-crossing comparison signal V.sub.zvs_comp to be connected to the counter; the counter is configured to count to obtain values of Δt.sub.r_half and T.sub.r according to changes between high levels and low levels of the feedback comparison signal and the zero-crossing comparison signal V.sub.zvs_comp, Δt.sub.r half is a total time required for the voltage signal V.sub.ref_slope of the single slope digital wave to rise from a position of an initial voltage V.sub.initial to a position crossing the voltage signal V.sub.sense on the auxiliary winding, and T.sub.r is a reset time required for the secondary-side current to drop from a peak value to a lowest point; the feedback amount calculation module is configured to output a feedback signal V.sub.ref initial to be connected to an input terminal of the triangular wave generator and an input terminal of the first DAC, and is configured to adjust a digital value of the initial voltage V.sub.initial of the single slope digital wave for a next cycle according to a difference between the values of Δt.sub.r half and T.sub.r; and when the voltage signal V.sub.sense on the auxiliary winding is equal to the voltage signal V.sub.ref_slope of the single slope digital wave, an instant value of the voltage signal V.sub.ref_slope of the single slope digital wave is assigned to the voltage signal V.sub.sense(t.sub.mid) at the midpoint instant T.sub.mid to output as an output signal of the single-output DAC midpoint sampling module in a current switching cycle.

3. The deadtime automatic-optimization system of claim 1, wherein the digital control module comprises: an adder, a subtractor, a multiplier, a register, operational amplifiers K.sub.p and K.sub.i, and a mode determination module; wherein an input signal of the digital control module is the voltage signal V.sub.sense(t.sub.mid) of the single-output DAC midpoint sampling module, and output signals of the digital control module are the digital value V.sub.peak_d of the peak voltage on the primary-side current sampling resistor R.sub.cs and the control amount V.sub.c(n); a value of the error e(n) between the voltage signal V.sub.sense(t.sub.mid) of the single-output DAC midpoint sampling module and the system-predetermined fixed value V.sub.REF is calculated, and the control amount V.sub.c(n) is calculated by proportion and integration according to the error e(n) to output; and the mode determination module is configured to output the digital value V.sub.peak_d of the peak value on the primary-side current sampling resistor R.sub.cs as an output signal according to the value of the error e(n).

4. The deadtime automatic-optimization system of claim 1, wherein the current detection module comprises: a single-input double-output DAC, a third comparator CMP3 and a fourth comparator CMP4, a primary-side current time counting module, and a secondary-side average current calculation module; wherein the digital value V.sub.peak_d of the peak voltage on the primary-side current sampling resistor R.sub.cs output by the digital control module is respectively connected to the single-input double-output DAC and the secondary-side average current calculation module; a positive terminal of the third comparator CMP3 is connected to the voltage V.sub.cs at the two terminals of the primary-side current sampling resistor R.sub.cs, and a negative terminal of the third comparator CMP3 is connected to a voltage analog value V.sub.peak on the primary-side current sampling resistor corresponding to a primary-side peak current output by the single-input double-output DAC; a positive terminal of the fourth comparator CMP4 is connected to the voltage V.sub.cs at the two terminals of the primary-side current sampling resistor R.sub.cs, and a negative terminal of the fourth comparator CMP4 is connected to a voltage analog value V.sub.peak_half on the primary-side current sampling resistor corresponding to k times of the voltage analog value V.sub.peak on the primary-side current sampling resistor corresponding to the primary-side peak current, and V.sub.peak_half=k.Math.V.sub.peak, 0<k<1; the third comparator CMP3 and the fourth comparator CMP4 are configured to output comparison signals and V.sub.cmp3 and V.sub.cmp4, respectively, and the comparison signals V.sub.cmp3 and V.sub.cmp4 are connected to the primary-side current time counting module; the primary-side current time counting module comprises two counters, input signals of the two counters are the comparison signals and V.sub.cmp3 and V.sub.cmp4 of the comparators CMP3 and CMP4, respectively; according to changes between high levels and low levels of the comparison signals V.sub.cmp3 and V.sub.cmp4, a time t.sub.a required by a linear increase of a primary-side current from zero amp or an initial current to a peak current in a discontinuous conduction mode (DCM), and a time t.sub.b required by a linear increase of the primary-side current from zero amp or the initial current to the peak current in the CCM are obtained; the times t.sub.a and t.sub.b are configured to output to the secondary-side average current calculation module; according to the input times t.sub.a and t.sub.b and the digital value V.sub.peak_d of the peak voltage on the primary-side current sampling resistor R.sub.cs output by the digital control module, the secondary-side average current calculation module is configured to divide V.sub.peak_d by a resistance of the primary-side current sampling resistor R.sub.cs to obtain a digital value corresponding to a peak current I.sub.peak p of a primary-side winding inductor, and the digital value corresponding to the peak current I.sub.peak p is substituted into an expression of I.sub.s(t.sub.mid): $I_s\left(t_{\mathrm{mid}}\right)=\frac{N_p}{N_s}.Math.\frac{\left(1+k\right)t_b-\left(1-k\right)t_a}{2t_b}.Math.I_{pea{k}_{-}p},$ wherein N.sub.p and N.sub.s denote a number of turns of a primary side and a secondary side of a transformer, respectively, and the secondary-side average current I.sub.s(t.sub.mid) in the CCM is obtained and output.

5. The deadtime automatic-optimization system of claim 1, wherein the deadtime calculation module is configured to calculate the reasonable deadtime t.sub.d between the turn-off of the secondary-side rectifier SR and the turn-on of the primary-side switching transistor SW according to the secondary-side average current I.sub.s(t.sub.mid) output by the current detection module by using a calculation chain comprising an adder, a multiplier, and a divider, and the deadtime t.sub.d is calculated according to following formulas: $$\begin{gathered} t_d=K_1+K_2+K_3+f\left(I_s\right), \\ {K}_1=R_g\frac{Q_g-Q_{gd}-Q_{gs}}{U_{GS}-U_P}\ln \left(\frac{U_g}{U_P}\right), \\ {K}_2=\frac{R_g}{U_P}{Q}_{\mathrm{gd}}, \\ {K}_3=-\frac{2R_g}{U_P}\sqrt{U_{dg}\left(t\right)}{C}_{\mathrm{rss}}\left(t\right)\sqrt{U_{DS}-I_L{R}_{ds}-U_T}, \\ f\left(I_s\right)=m-\frac{n}{m}{I}_s-\frac{n^2}{2m^3}{I}_s^2, \\ m=\sqrt{U_X-U_T},n=R_{ds}, \end{gathered}$$ in the formulas, U.sub.p is a Miller plateau voltage, U.sub.g is a gate voltage of the secondary-side rectifier, R.sub.g is a gate resistance of the secondary-side rectifier, Q.sub.g is a total dissipation charge amount of the gate during the turn-off of the secondary-side rectifier, Q.sub.gd is a dissipation charge amount of the gate in a Miller effect phase during the turn-off of the secondary-side rectifier, Q.sub.gs is a dissipation charge amount of the gate in a phase that U.sub.gs decreases from the Miller plateau voltage U.sub.p to 0 during the turn-off of the secondary-side rectifier, I.sub.L is a load current, U.sub.ds is an input voltage of the secondary-side rectifier, C.sub.rss is a reverse transfer capacitance of the secondary-side rectifier, I.sub.s is a secondary-side current, U.sub.X is an experimental measurement, U.sub.τ is a threshold voltage of the secondary-side rectifier, and R.sub.ds is a source-drain resistance of the secondary-side rectifier.

6. A control system of a flyback power supply having a primary-side feedback in a continuous conduction mode (CCM), the flyback power supply having the primary-side feedback comprising: a primary side of a transformer comprising a primary-side winding, a primary-side switching transistor, and a primary-side current sampling resistor connected in series to the primary-side switching transistor; a secondary side of the transformer comprising a secondary-side winding and a secondary-side rectifier; and an auxiliary winding; wherein the control system comprises: a single-output digital to analog converter (DAC) midpoint sampling module configured to sample a voltage signal V.sub.sense(t.sub.mid) on the auxiliary winding at a midpoint instant T.sub.r/2 of a secondary-side current reset time T.sub.r; a digital control module configured to calculate an error e(n) between the voltage signal V.sub.sense(t.sub.mid) and a system-predetermined fixed value V.sub.REF, calculate an input voltage control amount V.sub.c(n) for a PWM driving module by using proportion and integration according to the error e(n), and obtain a digital value V.sub.peak_d of a peak voltage on the primary-side current sampling resistor R.sub.cs according to the error e(n); a current detection module configured to obtain a primary-side average current J.sub.mid_p and a secondary-side average current I.sub.x(t.sub.mid) in the CCM indirectly by sampling and calculating through a digital-to-analog conversion according to the digital value V.sub.peak_d and a voltage V.sub.cs at two terminals of the primary-side current sampling resistor R.sub.cs; a deadtime calculation module configured to calculate a deadtime t.sub.d between a turn-off of the secondary-side rectifier and a turn-on of the primary-side switching transistor according to the secondary-side average current I.sub.x(t.sub.mid); and the PWM driving module configured to generate a primary-side duty cycle control signal duty and a secondary-side duty cycle control signal duty_SR according to the deadtime t.sub.d and the input voltage control amount V.sub.c(n), control switching of the primary-side switching transistor according to the primary-side duty cycle control signal duty, and control switching of the secondary-side rectifier according to the secondary-side duty cycle control signal duty_SR.

7. The control system of claim 6, wherein the single-output DAC midpoint sampling module comprises: a first DAC, a triangular wave generator, a first comparator CMP1, a second comparator CMP2, a counter, and a feedback amount calculation module; wherein a voltage signal V.sub.sense on the auxiliary winding is configured to input as input signals to a positive terminal of the first comparator CMP1 and a positive terminal of the second comparator CMP2, respectively; after superimposition of a digital single sloping wave output by the triangular wave generator and an analog reference voltage output by the first DAC, a voltage signal V.sub.ref_slope of a single slope digital wave is obtained and is configured to input to a negative terminal of the first comparator CMP1; a negative terminal of the second comparator CMP2 is connected to zero voltage; the first comparator CMP1 is configured to output a feedback comparison signal V.sub.ref_comp to the counter, and the second comparator CMP2 is configured to output a zero-crossing comparison signal V.sub.zvs_comp to the counter; the counter is configured to count to obtain values of Δt.sub.r half and T.sub.r according to changes between high levels and low levels of the feedback comparison signal V.sub.ref_comp and the zero-crossing comparison signal V.sub.zvs_comp, wherein Δt.sub.r half is a total time required for the voltage signal V.sub.ref_slope of the single slope digital wave to rise from a position of an initial voltage V.sub.initial to a position crossing the voltage signal V.sub.sense on the auxiliary winding, and T.sub.r is a reset time required for the secondary-side current to drop from a peak value to a lowest point; according to a difference between the values of Δt.sub.r half and T.sub.r, the feedback amount calculation module is configured to output a feedback signal V.sub.ref initial to an input terminal of the triangular wave generator and an input terminal of the first DAC, and adjust a digital value of the initial voltage V.sub.initial for a next cycle; when the voltage signal V.sub.sense on the auxiliary winding is equal to the voltage signal V.sub.ref_slope of the single slope digital wave, an instant value of the voltage signal V.sub.ref_slope of the single slope digital wave is assigned to the voltage signal V.sub.sense(t.sub.mid) to output as an output signal of the single-output DAC midpoint sampling module in a current switching cycle.

8. The control system of claim 6, wherein the current detection module comprises: a single-input double-output DAC, a third comparator CMP3, a fourth comparator CMP4, a primary-side current time counting module, and a secondary-side average current calculation module; wherein the single-input double-output DAC and the secondary-side average current calculation module are configured to receive the digital value V.sub.peak_d output by the digital control module; a positive terminal of the third comparator CMP3 and a positive terminal of the fourth comparator CMP4 are configured to receive the voltage V.sub.cs ; a voltage analog value V.sub.peak on the primary-side current sampling resistor corresponds to a primary-side peak current output by a first output terminal of the single-input double-output DAC, and the voltage analog value V.sub.peak is configured to output to a negative terminal of the third comparator CMP3; a second output terminal of the single-input double-output DAC is configured to output V.sub.peak_half, wherein V.sub.peak_half=k.Math.V.sub.peak, 0<k<1, and the V.sub.peak_half is configured to output to a negative terminal of the fourth comparator CMP4; the third comparator CMP3 is configured to output a comparison signal V.sub.cmp3 to a first counter of the primary-side current time counting module, and the fourth comparator CMP4 is configured to output a comparison signal V.sub.cmp4 to a second counter of the primary-side current time counting module; according to changes of high levels and low levels of the comparison signal V.sub.cmp3 and the comparison signal V.sub.cmp4, the primary-side current time counting module is configured to obtain a time T.sub.q required by a linear increase of a primary-side current from zero amp or an initial current to a peak current in a DCM and a time t.sub.b, required by a linear increase of the primary-side current from zero amp or the initial current to the peak current in the CCM, and output the times t.sub.a and t.sub.b to the secondary-side average current calculation module; the secondary-side average current calculation module is configured to divide the digital value V.sub.peak_d by a resistance of the primary-side current sampling resistor R.sub.cs to obtain a digital value I.sub.peak p corresponding to a peak current of a primary-side winding inductor, and the digital value I.sub.peak p is substituted into an expression of I.sub.x(t.sub.mid ) along with the times t.sub.a and t.sub.b; $I_s\left(t_{\mathrm{mid}}\right)=\frac{N_p}{N_s}.Math.\frac{\left(1+k\right)t_b-\left(1-k\right)t_a}{2t_b}.Math.I_{pea{k}_{-}p},$ wherein N.sub.p and N.sub.s denote a number of turns of the primary-side winding and the secondary-side winding of the transformer, respectively, and the secondary-side average current I.sub.s(t.sub.mid) in the CCM is obtained and output.

9. The control system of claim 6, wherein the deadtime calculation module is configured to calculate the deadtime t.sub.d according to following formulas: $$\begin{gathered} t_d=K_1+K_2+K_3+f\left(I_s\right), \\ {K}_1=R_g\frac{Q_g-Q_{gd}-Q_{gs}}{U_{GS}-U_P}\ln \left(\frac{U_g}{U_P}\right), \\ {K}_2=\frac{R_g}{U_P}{Q}_{\mathrm{gd}}, \\ {K}_3=-\frac{2R_g}{U_P}\sqrt{U_{dg}\left(t\right)}{C}_{\mathrm{rss}}\left(t\right)\sqrt{U_{DS}-I_L{R}_{ds}-U_T}, \\ f\left(I_s\right)=m-\frac{n}{m}{I}_s-\frac{n^2}{2m^3}{I}_s^2, \\ m=\sqrt{U_X-U_T},n=R_{ds}, \end{gathered}$$ in the above formulas, U.sub.p is a Miller plateau voltage, U.sub.g is a gate voltage of the secondary-side rectifier, R.sub.q is a gate resistance of the secondary-side rectifier, Q.sub.g is a total dissipation charge amount by the gate during the turn-off of the secondary-side rectifier, Q.sub.gd is a dissipation charge amount of the gate in a Miller effect phase during the turn-off of the secondary-side rectifier, Q.sub.gs is a dissipation charge amount of the gate in a phase that U.sub.gs decreases from the Miller plateau voltage U.sub.p to 0 during the turn-off of the secondary-side rectifier, I.sub.L is a load current, U.sub.ds , is an input voltage of the secondary-side rectifier, C.sub.rss is a reverse transfer capacitance of the secondary-side rectifier, I.sub.s is a secondary-side current, U.sub.X is an experimental measurement, U.sub.T : is a threshold voltage of the secondary-side rectifier, and R.sub.ds is a source-drain resistance of the secondary-side rectifier.

10. The control system of claim 6, wherein the PWM driving module comprises: a sixth comparator, an inverter, a D flip-flop, an OR-gate, and a PWM driving unit; wherein a positive input terminal of the sixth comparator is configured to receive the deadtime t.sub.d, and a negative input terminal of the sixth comparator is connected to zero voltage; an output terminal of the sixth comparator is connected to an input terminal of the inverter; an output terminal of the inverter is connected to a D-input terminal of the D flip-flop; an input signal of the PWM driving unit is the input voltage control amount V.sub.c(n); a first output terminal of the PWM driving unit is configured to output the primary-side duty cycle control signal duty, and a second output terminal of the PWM driving unit is configured to output a signal duty_SRI to a clock control terminal of the D flip-flop; a Q-output terminal of the D flip-flop is connected to one input terminal of the OR-gate, the signal duty_SRI is configured to input to the other input terminal of the OR-gate, and an output terminal of the OR-gate is configured to output the secondary-side duty cycle control signal duty_SR.

11. The control system of claim 6, wherein the secondary-side rectifier is a metal oxide semiconductor (MOS) transistor.

12. The control system of claim 6, wherein the primary-side switching transistor is a MOS transistor, and the primary-side current sampling resistor is connected in series between a source of the primary-side switching transistor and ground.

13. A method of controlling a flyback power supply having a primary-side feedback in a continuous conduction mode (CCM), the flyback power supply having the primary-side feedback comprising: a primary side of a transformer comprising a primary-side winding, a primary-side switching transistor, and a primary-side current sampling resistor connected in series to the primary-side switching transistor; a secondary side of the transformer comprising a secondary-side winding and a secondary-side rectifier; and an auxiliary winding; wherein the method comprises: sampling a voltage signal V.sub.sense(t.sub.mid) on the auxiliary winding at a midpoint instant T.sub.r/2 of a secondary-side current reset time T.sub.r; calculating an error e(n) between the voltage signal V.sub.sense(t.sub.mid) and a system-predetermined fixed value V.sub.REF, calculating an input voltage control amount V.sub.c(n) for a PWM driving module by using proportion and integration according to the error e(n), and obtaining a digital value V.sub.peak_d of a peak voltage on the primary-side current sampling resistor R.sub.cs according to the error e(n); obtaining a primary-side average current I.sub.mid p and a secondary-side average current I.sub.s(t.sub.mid) in the CCM indirectly by sampling and calculating through a digital-to-analog conversion according to the digital value V.sub.peak_d and a voltage V.sub.cs at two terminals of the primary-side current sampling resistor R.sub.cs; calculating a deadtime t.sub.d between a turn-off of the secondary-side rectifier and a turn-on of the primary-side switching transistor according to the secondary-side average current I.sub.s(t.sub.mid); generating, by the PWM driving module, a primary-side duty cycle control signal duty and a secondary-side duty cycle control signal duty_SR according to the deadtime t.sub.d and the input voltage control amount V.sub.c(n); and controlling switching of the primary-side switching transistor according to the primary-side duty cycle control signal duty, and controlling switching of the secondary-side rectifier according to the secondary-side duty cycle control signal duty_SR.

14. The method of claim 13, wherein the step of sampling the voltage signal V.sub.sense(t.sub.mid) on the auxiliary winding at the midpoint instant T.sub.r/2 of the secondary-side current reset time T.sub.r comprises: inputting, by a positive terminal of a first comparator CMP1, a voltage signal V.sub.sense on the auxiliary winding, after superimposition of a digital single sloping wave output by a triangular wave generator and an analog reference voltage output by a first DAC, obtaining a voltage signal V.sub.ref_slope of a single slope digital wave to output to a negative terminal of the first comparator CMP1, and outputting, by the first comparator CMP1, a feedback comparison signal V.sub.ref_comp; inputting, by a positive terminal of a second comparator CMP2, the voltage signal V.sub.sense on the auxiliary winding, inputting, by a negative terminal of the second comparator CMP2, zero voltage, and outputting, by the second comparator CMP2, a zero-crossing comparison signal V.sub.zvs_comp; counting to obtain values of Δt.sub.r half and T.sub.r according to changes between high levels and low levels of the feedback comparison signal V.sub.ref_comp and the zero-crossing comparison signal V.sub.zvs_comp, wherein Δt.sub.r half is a total time required for the voltage signal V.sub.ref_slope of the single slope digital wave to rise from a position of an initial voltage V.sub.initial to a position crossing the voltage signal V.sub.sense on the auxiliary winding, and T.sub.r is a reset time required for a secondary-side current to drop from a peak value to a lowest point; outputting a feedback signal V.sub.ref initial to an input terminal of the triangular wave generator and an input terminal of the first DAC, and adjusting a digital value of the initial voltage V.sub.initial for a next cycle according to a difference between the values of Δt.sub.r half and T.sub.r; and assigning, when the voltage signal V.sub.sense on the auxiliary winding is equal to the voltage signal V.sub.ref_slope of the single slope digital wave, an instant value of the voltage signal V.sub.ref_slope of the single slope digital wave to the voltage signal V.sub.sense(t.sub.mid).

15. The method of claim 13, wherein the step of obtaining the primary-side average current I.sub.mid p and the secondary-side average current I.sub.s(t.sub.mid) in the CCM indirectly by sampling and calculating through the digital-to-analog conversion according to the digital value V.sub.peak_d and the voltage V.sub.cs at the two terminals of the primary-side current sampling resistor R.sub.cs comprises: receiving, by a positive terminal of a third comparator CMP3 and a positive terminal of a fourth comparator CMP4, the voltage V.sub.csl performing a digital-to-analog conversion on the digital value V.sub.peak_d to obtain a voltage analog value V.sub.peak on the primary-side current sampling resistor corresponding to a primary-side peak current and output the voltage analog value V.sub.peak to a negative terminal of the third comparator CMP3, and to obtain V.sub.peak_half and output the V.sub.peak_half to a negative terminal of the fourth comparator CMP4, wherein V.sub.peak_half=k.Math.V.sub.peak, 0<k<1; obtaining, according to changes between high levels and low levels of a comparison signal V.sub.cmp3 output by the third comparator CMP3 and changes between high levels and low levels of a comparison signal V.sub.cmp4 output by the fourth comparator CMP4, a time t.sub.a required by a linear increase of a primary-side current from zero amp or an initial current to a peak current in a DCM and a time t.sub.b required by a linear increase of the primary-side current from zero amp or the initial current to the peak current in the CCM; dividing the digital value V.sub.peak_d by a resistance of the primary-side current sampling resistor R.sub.cz to obtain a digital value I.sub.peak p of a peak current of a primary-side winding inductor; and substituting the digital value I.sub.peak p, the times t.sub.a and t.sub.b into an expression of I.sub.s(t.sub.mid): $I_s\left(t_{\mathrm{mid}}\right)=\frac{N_p}{N_s}.Math.\frac{\left(1+k\right)t_b-\left(1-k\right)t_a}{2t_b}.Math.I_{pea{k}_{-}p},$ wherein N.sub.p and N.sub.s denote a number of turns of the primary-side winding and the secondary-side winding of the transformer, respectively, to obtain the secondary-side average current I.sub.x(t.sub.mid) in the CCM.

16. The method of claim 13, wherein during the step of calculating the deadtime t.sub.d between the turn-off of the secondary-side rectifier and the turn-on of the primary-side switching transistor according to the secondary-side average current I.sub.s(t.sub.mid), the deadtime T.sub.d is calculated according to following formulas: $$\begin{gathered} t_d=K_1+K_2+K_3+f\left(I_s\right), \\ {K}_1=R_g\frac{Q_g-Q_{gd}-Q_{gs}}{U_{GS}-U_P}\ln \left(\frac{U_g}{U_P}\right), \\ {K}_2=\frac{R_g}{U_P}{Q}_{\mathrm{gd}}, \\ {K}_3=-\frac{2R_g}{U_P}\sqrt{U_{dg}\left(t\right)}{C}_{\mathrm{rss}}\left(t\right)\sqrt{U_{DS}-I_L{R}_{ds}-U_T}, \\ f\left(I_s\right)=m-\frac{n}{m}{I}_s-\frac{n^2}{2m^3}{I}_s^2, \\ m=\sqrt{U_X-U_T},n=R_{ds}, \end{gathered}$$ in the above formulas, U.sub.p is a Miller plateau voltage, U.sub.g is a gate voltage of the secondary-side rectifier, R.sub.g is a gate resistance of the secondary-side rectifier, Q.sub.g is a total dissipation charge amount of the gate during the turn-off of the secondary-side rectifier, Q.sub.gd is a dissipation charge amount of the gate in a Miller effect phase during the turn-off of the secondary-side rectifier, Q.sub.gs is a dissipation charge amount of the gate in a phase that U.sub.gs decreases from the Miller plateau voltage U.sub.p to 0 during the turn-off of the secondary-side rectifier, I.sub.L is a load current, U.sub.ds is an input voltage of the secondary-side rectifier, C.sub.rss is a reverse transfer capacitance of the secondary-side rectifier, I.sub.s is a secondary-side current, is an experimental measurement, U.sub.T is a threshold voltage of the secondary-side rectifier, and R.sub.ds is a source-drain resistance of the secondary-side rectifier.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) In order to illustrate the technical solutions in the embodiments of the present disclosure more clearly, the drawings used in the description of the embodiments will be briefly introduced below. Apparently, the drawings in the following description are merely some embodiments of the present disclosure. For those skilled in the art, drawings of other embodiments can be obtained according to these drawings, without any creative efforts.

(2) FIG. 1 shows a circuit diagram of a conventional flyback switching converter having a primary-side feedback using a diode rectification method.

(3) FIG. 2 shows a circuit diagram of a flyback switching converter having a primary-side feedback using a MOSFET switching transistor rectification method having a low on-resistance.

(4) FIG. 3 shows waveforms of main signals of a flyback converter having a synchronous-rectification primary-side feedback in a CCM.

(5) FIG. 4 shows a curve of current changes over time during a reverse recovery of a parasitic diode.

(6) FIG. 5 shows an operating circuit diagram of a turn-off delay phase.

(7) FIG. 6 shows an operating circuit diagram of a Miller effect phase.

(8) FIG. 7 shows waveforms of main signals during a turn-off of a secondary-side rectifier.

(9) FIG. 8 shows a circuit diagram of an overall implementation of a deadtime automatic-optimization system of a flyback switching converter having a primary-side feedback in a CCM using a synchronous-rectification method according to the present disclosure.

(10) FIG. 9 shows an internal structure diagram of a current detection module in FIG. 8.

(11) FIG. 10 shows an internal structure diagram of a deadtime calculation module in FIG. 8.

(12) FIG. 11 shows an internal structure diagram of a PWM driving module in FIG. 8.

(13) FIG. 12 shows an internal structure diagram of a single-output DAC midpoint sampling module in FIG. 8.

(14) FIG. 13 shows an internal structure diagram of a digital control module in FIG. 8.

DETAILED DESCRIPTION OF THE EMBODIMENTS

(15) In order to make the objectives, features, and advantages of the present disclosure more comprehensible, the specified embodiments of the present disclosure will be illustrated in detail with reference to the accompanying drawings.

(16) FIG. 1 shows a circuit diagram of a conventional flyback switching converter having a primary-side feedback and using a diode rectification method. In a conventional flyback switching converter, a diode rectification method is used, as shown in FIG. 1. For the application of high-power power supply systems, the loss on rectifier diodes has become a bottleneck for improving system efficiency. To this end, a synchronous rectification structure having higher efficiency is provided.

(17) The synchronous rectification is a new technology for replacing a rectifier diode with a MOSFET having an extremely low on-resistance, which is generally applied to scenarios with low voltages and high current. A synchronous rectifier has a lower on-resistance and less forward voltage drop, resulting in low rectification losses and meeting current design requirements.

(18) FIG. 2 shows a circuit diagram of the flyback switching converter having the primary-side feedback and using a MOSFET switching transistor rectification method having a low on-resistance. Gates of a primary-side switching transistor SW and a secondary-side rectifier SR are driven by two voltages having opposite timings, that is, when the switching transistor SW is turned on, the rectifier SR is turned off, or when the switching transistor SW is turned off, the rectifier SR is turned on. When the switching transistor SW is turned on and the rectifier SR is turned off, the input voltage yin linearly increases the current through an inductor L, and the inductor begins to store energy. When the rectifier SR is turned on and the switching transistor SW is turned off, the energy stored in the primary-side inductor is coupled to the secondary side through the transformer to supply power to the load and the output capacitor.

(19) In order to avoid the breakdown phenomenon caused by a simultaneous turning-on of the primary-side switching transistor and the secondary-side switching transistor during the switching between the primary-side and secondary-side switches of the flyback converter, it must ensure that a deadtime is interposed between the primary-side and secondary-side switching transistors. That is, the secondary-side switching transistor can be turned on only after the primary-side switching transistor is turned off; the primary-side switching transistor can be turned on only after the secondary-side switching transistor is turned off

(20) FIG. 3 shows waveforms of main signals of the flyback converter having the synchronous-rectification primary-side feedback in the CCM. FIG. 3 shows the waveforms of the main signals of the flyback converter having the synchronous-rectification primary-side feedback in the CCM, in order to facilitate the analysis, an operating cycle is divided into a plurality of different phases as below.

(21) At an instant t.sub.0, a primary-side switching transistor SW is turned on, a primary-side current I.sub.p flows through a primary-side inductor L.sub.m and the primary-side switching transistor SW, and the primary-side current I.sub.p increases linearly. In a period between t.sub.0 to t.sub.1, the primary-side switching transistor SW is turned on, and a voltage V.sub.ds.sup.sw at two terminals thereof is zero.

(22) At the instant t.sub.1, the primary-side switching transistor SW is turned off. An equivalent parasitic capacitor C.sub.eqp at the two terminals of the switching transistor is charged by the excitation current I.sub.p, until the value of the voltage V.sub.ds.sup.sw at the two terminals of the primary-side switching transistor SW reaches V.sub.in+NV.sub.o at the instant t.sub.2.

(23) In a period between t.sub.1 and t.sub.3, a secondary-side switching transistor SR is not turned on yet. At the instant t.sub.2, the primary-side current I.sub.p drops to zero, and primary-side energy is transferred to the secondary side through a transformer. At this instant, the secondary-side switching transistor SR is still in the off state, a parasitic diode D.sub.R is turned on, and a secondary-side current I.sub.S increases quickly. Since the on-resistance of the parasitic diode D.sub.R is much greater than the on-resistance of the MOSFET of the secondary-side switching transistor SR, the secondary-side current I.sub.S flowing through the parasitic diode D.sub.R will cause a large conduction loss of the diode, resulting in a decrease in the efficiency of the flyback converter, and therefore the deadtime of t.sub.1 to t.sub.3 should be as small as possible.

(24) In a period between t.sub.3 and t.sub.4, the secondary-side switching transistor SR is turned on. The secondary-side current I.sub.S flows through the MOSFET, rather than through the parasitic diode D.sub.R. The on-resistance of the MOSFET of the secondary-side switching transistor SR is extremely low, thereby greatly reducing the conduction loss.

(25) At an instant t.sub.4, the secondary-side switching transistor SR is turned off. In a period between t.sub.4 and t.sub.5, the MOSFET of the secondary-side switching transistor SR is off, and the current flows through the parasitic diode D.sub.R of the MOSFET. When the primary-side switching transistor SW is turned on at the instant t.sub.6, the voltage drop at the two terminals of the parasitic diode suddenly changes from forward to reverse, and a reverse recovery current can be generated in the process, which causes a reverse recovery loss of the parasitic diode D.sub.R. Therefore, in order to reduce the reverse recovery loss of the parasitic diode D.sub.R in the CCM, the deadtime of t.sub.4 to t.sub.5 should be as small as possible.

(26) FIG. 4 shows a curve of current changes over time during the reverse recovery of the parasitic diode. As shown in FIG. 4, in a forward conduction period t.sub.f, a value of the current flowing through the parasitic diode D.sub.R is I.sub.F. When the voltage drop at the two terminals of the parasitic diode D.sub.R changes from a forward voltage V.sub.F to a reverse voltage V.sub.R, so the current changes from the forward current I.sub.F to a reverse current I.sub.R, and remains constant in a storing time t.sub.s. Then, the current gradually drops to 0.1 of I.sub.R in a transit time t.sub.t. At this instant of the end of the transit time t.sub.t, the value of the reverse current is negligible. Namely, only when the storing time t.sub.s and the transit time t.sub.t have lapsed, does the parasitic diode D.sub.R enter a reverse off-state. This is due to the charge storage effect of the PN junction of the parasitic diode D.sub.R. During the forward conduction, a certain number of unbalanced minority carriers are accumulated in the PN junction of the parasitic diode D.sub.R. When the voltage drop at the two terminals changes from forward to reverse, the stored unbalanced minority carriers do not disappear immediately, but instead, form a reverse drift current and are gradually consumed by being compounded with the majority carriers. This time is the reverse recovery time of the parasitic diode D.sub.R. In this process, the reverse recovery current will be generated, thereby causing the reverse recovery loss of the parasitic diode D.sub.R.

(27) FIG. 5 shows an operating circuit diagram of a turn-off delay phase. The portion in the dashed box is not considered in this phase. At the instant t.sub.4, a square wave drive signal for the gate of the secondary-side switching transistor SR drops from a high level to zero. The transistor SR starts to enter the turn-off process. A gate current i.sub.g discharges C.sub.gs, and charges C.sub.dg. U.sub.gs starts to drop. In this period, the decay time constant of U.sub.gs is τ=R.sub.g(C.sub.dg+C.sub.gs), and the transistor SR remains on. I.sub.s in the transistor SR is divided into i.sub.ch flowing through the channel, i.sub.ds flowing through C.sub.ds, and i.sub.dg flowing through C.sub.dg. Since i.sub.ds and i.sub.dg are significantly less than I.sub.s in this phase, it can be considered that i.sub.ch≈I.sub.s and U.sub.gs≈I.sub.sR.sub.ds, in which R.sub.ds is the drain-source on-resistance of the transistor SR. At the instant t.sub.5, U.sub.gs=I.sub.sR.sub.ds+U.sub.T, in which U.sub.T is a threshold voltage of the MOSFET. The transistor SR is transformed from an unsaturated region (linear resistance region) to a saturated region to operate. When the Miller effect occurs, this process ends. This phase is the turn-off delay phase of the turn-off process of the MOSFET.

(28) FIG. 6 shows an operating circuit diagram of the Miller effect phase. The portion in the dashed box is not considered in this phase. In view of the presence of the Miller effect, U.sub.gs remains substantially constant and departs from the original trajectory in this phase. The value of U.sub.gs is referred to a Miller plateau voltage, which is denoted by U.sub.p. It is readily known from the analysis in the previous phase that U.sub.p≈I.sub.sR.sub.ds+U.sub.T. In addition, C.sub.gs does not discharge any more, and i.sub.g completely flows through C.sub.dg and causes U.sub.dg, to increase. Since i.sub.g is small and U.sub.ds =U.sub.p+U.sub.dg, U.sub.ds slowly rises and arrives at U.sub.X at the instant t.sub.6. At this instant, the N.sup.− epitaxial layer of the transistor SR changes from depletion to accumulation. The channel is turned off, and i.sub.ch=0. Therefore, I.sub.s flows only through C.sub.ds and C.sub.dg. U.sub.X is an important parameter for analyzing the switching process of the MOSFET. Although most MOSFET datasheets fail to give U.sub.X, it can be measured through simple test experiments. This phase is the Miller effect phase in the turn-off process of the MOSFET, and the sum of the duration of the Miller effect phase and the duration of the turn-off delay phase is the turn-off time of the MOSFET.

(29) FIG. 7 shows waveforms of main signals during a turn-off of a secondary-side rectifier. At the instant t.sub.4, a square wave drive signal for the gate of the secondary-side switching transistor SR drops from a high level to zero. The transistor SR starts to enter the turn-off process. A gate current i.sub.g discharges the gate-source capacitor C.sub.gs, and charges the gate-drain capacitor C.sub.dg. U.sub.gs starts to drop. In this period, the decay time constant of U.sub.gs is τ=R.sub.g(C.sub.dg+C.sub.gs), and the transistor SR remains on. I.sub.s in the transistor SR is divided into i.sub.ch flowing through the channel, i.sub.ds flowing through C.sub.ds, and i.sub.dg flowing through C.sub.dg. Since i.sub.ds and i.sub.dg are significantly less than I.sub.s in this phase, it can be considered that i.sub.ch≈I.sub.s and U.sub.gs≈I.sub.sR.sub.ds, in which R.sub.ds is the drain-source on-resistance of the transistor SR. At the instant t.sub.5, U.sub.gs=I.sub.sR.sub.ds+U.sub.T, in which U.sub.T is a threshold voltage of the MOSFET. The transistor SR is transformed from an unsaturated region (linear resistance region) to a saturated region to operate. When the Miller effect occurs, this process ends. This phase is the turn-off delay phase of the turn-off process of the MOSFET.

(30) In view of the presence of the forward conduction loss and the reverse recovery loss of the parasitic diode of the conventional flyback converter having the synchronous-rectification primary-side feedback in the CCM, the present disclosure provides a deadtime automatic-optimization system in the CCM, which can reasonably optimize the deadtime, thereby minimizing the forward conduction loss and the reverse recovery loss of the parasitic diode. According to the present disclosure, the primary-side current is sampled to calculate the secondary-side average current through a digital to analog converter (DAC) sampling mechanism, to obtain a primary-side average current I.sub.mid_p and a secondary-side average current I.sub.s(t.sub.mid) in the CCM. Then, the secondary-side average current is input into a deadtime calculation module, so that a reasonable deadtime t.sub.d is obtained. Finally, a PWM driving module is controlled by a primary-side feedback loop and the obtained deadtime t.sub.d together to generate a drive signal duty for the primary-side switching transistor and a drive signal duty_SR for the secondary-side rectifier, so that the deadtime between the turn-off of the secondary-side rectifier and the turn-on of the primary-side switching transistor in the CCM can be reasonably optimized.

(31) FIG. 8 shows a block diagram of a deadtime automatic-optimization solution of a flyback switching converter having a primary-side feedback in the CCM using the synchronous-rectification method according to the present disclosure. Compared with a conventional diode rectification method, the present disclosure is based on the main topology of the flyback converter using the synchronous-rectification method. The topology includes the primary-side switching transistor, the secondary-side rectifier, and the transformer. The deadtime optimization system in the CCM includes a current detection module, a deadtime calculation module, a PWM driving module, a single-output DAC midpoint sampling module, and a digital control module. The present disclosure provides a scheme for automatically optimizing deadtime in a pure digital control manner according to different operating conditions. As shown in the figures, under the main topology of the primary-side feedback, the single-output DAC midpoint sampling module of the control system accurately and carefully generates a digital value of an initial voltage V.sub.initial of a single slope digital wave through an internal feedback amount calculation module according to a result of continuous comparison of Δt.sub.r_half and T.sub.r/2 in each switching cycle. The digital value of the initial voltage V.sub.initial is configured for a triangular wave generator to generate a digital single sloping wave, which is superimposed on an analog reference voltage generated by the DAC to form the single slope digital wave V.sub.ref_slope. Finally, a comparator is used to compare the sampled slope voltage with a voltage V.sub.sense sampled by the auxiliary winding, which can accurately sample the voltage signal V.sub.sense on the auxiliary winding. By continuously comparing the size relationship between Δt.sub.r_half and T.sub.r/2 in each switching cycle, the feedback amount calculation module accurately and carefully adjusts the digital value of the initial voltage V.sub.initial of the single slope digital wave. This can ensure that the initial position of the voltage signal V.sub.ref_slope of the single slope digital wave can always change along with the change of the voltage signal V.sub.sense on the auxiliary winding under different load conditions, so as to accurately output the sampled midpoint sampling voltage signal V.sub.sense(t.sub.mid), thereby obtaining a better midpoint following effect under steady-state and dynamic conditions. In addition, by the current detection module, a pure digital schema is implemented rather than the conventional schema that widely uses analog to digital converters, the values of the primary-side average current I.sub.mid_p and the secondary-side average current I.sub.s(t.sub.mid) in the CCM are indirectly sampled and calculated through the DAC sampling mechanism. The output secondary-side average current I.sub.s(t.sub.mid) is input to the deadtime calculation module, and the current reasonable deadtime t.sub.d is obtained by the calculation of the deadtime calculation module. The digital control module calculates a control amount V.sub.c(n) using the proportion and integration according to an error e(n) between the midpoint voltage signal V.sub.sense(t.sub.mid) sampled by the single-output DAC and a system-predetermined value V.sub.REF. A steady-state error is eliminated by negative feedback adjustment to make an output voltage V.sub.o stable. The operation of the PWM driving module is adjusted according to the deadtime t.sub.d and the control amount V.sub.c(n) output by the digital control module. The PWM driving module can be the same as the PWM driving module used in the prior art, including a reset-set (RS) flip-flop, a comparator, a digital to analog converter DAC, and a driving circuit therein. The slight difference here is that the present disclosure uses the output t.sub.d of the deadtime calculation module to control a duty cycle control signal duty_SR for the secondary-side synchronous rectifier, which is generated by the PWM driving module, so that when the duty cycle control signal duty_SR is at a falling edge, a width of a low level changes along with the deadtime t.sub.d. In overall, the PWM driving module controls the switching of the primary-side switching transistor and the secondary-side synchronous rectifier through the signal duty and the signal duty_SR, so as to achieve the conversion from digital signals to time signals, thereby forming a closed loop system for the digitally controlled switching power supply.

(32) The present disclosure has the advantages and benefits that: according to the present disclosure, the primary-side current is sampled to calculate the secondary-side average current through a digital to analog converter (DAC) sampling mechanism, and a primary-side average current I.sub.mid_p and a secondary-side average current I.sub.s(t.sub.mid) in the CCM are obtained. Then, the secondary-side current is input into a deadtime calculation module, so that a reasonable deadtime t.sub.d is obtained. Finally, a PWM driving module is controlled by a primary-side feedback loop and the obtained deadtime t.sub.d together to generate a drive signal duty for the primary-side switching transistor and a drive signal duty_SR for the secondary-side rectifier, so that the deadtime between the turn-off of the secondary-side rectifier and the turn-on of the primary-side switching transistor in the CCM can be reasonably optimized.

(33) FIG. 9 shows an internal structure diagram of the current detection module. The pure digital schema is implemented rather than the conventional schema that widely uses analog to digital converters, the primary-side current is sampled to calculate the secondary-side average current through the DAC sampling mechanism, and the primary-side average current I.sub.mid_p and the secondary-side average current I.sub.s(t.sub.mid) in the CCM are obtained. The secondary-side average current I.sub.s(t.sub.mid) as an output signal is input into the deadtime calculation module to calculate the reasonable deadtime t.sub.d. The current detection module includes a single-input double-output DAC, two comparators CMP3 and CMP4, a primary-side current time counting module, and a secondary-side average current calculation module. The input of the DAC is given by a digital value V.sub.peak_d of the voltage on a primary-side current sampling resistor, which corresponds to a primary-side peak current that an output signal of the control module is. The output of the DAC is analog values V.sub.peak and V.sub.peak_half corresponding to V.sub.peak_d, in which V.sub.peak_half is k.Math.I.sub.peak_p, 0<k<1. A positive terminal of the comparator CMP3 is connected to a voltage V.sub.cs at the two terminals of the primary-side current sampling resistor R.sub.cs, and a negative terminal thereof is connected to the voltage analog value V.sub.peak on the primary-side current sampling resistor corresponding to the primary-side peak current. An output signal V.sub.cmp3 is input to the primary-side current time counting module as an input signal. A positive terminal of the comparator CMP4 is connected to the voltage V.sub.cs at the two terminals of the primary-side current sampling resistor R.sub.cs, and a negative terminal thereof is connected to the voltage analog value V.sub.peak_half on the primary-side current sampling resistor corresponding to k (0<k<1) times the primary-side peak current. To facilitate the calculation, the k here is given as 0.5. Therefore, V.sub.peak half =k.Math.V.sub.peak =0.5.Math.V.sub.peak. An output signal V.sub.cmp4 is input into the primary-side current time counting module as an input signal. The primary-side current time counting module consists of two counters. The input signals are the output signals V.sub.cmp3 .sup.and V.sub.cmp4 of the two comparators, respectively. According to changes between the high levels and low levels of V.sub.cmp3 and V.sub.cmp4, the time t.sub.a in which the primary-side current linearly increases from zero amp or an initial current to the peak current in the DCM, and the time t.sub.b in which the primary-side current linearly increases from zero amp or an initial current to the peak current in the CCM are obtained, so that the required times t.sub.a and t.sub.b are calculated respectively, and are input into the secondary-side average current calculation module as output signals. The input signals of the secondary-side average current calculation module are t.sub.a and t.sub.b, and the primary-side peak current corresponds to the digital value V.sub.peak_dof the voltage on the primary-side current sampling resistor. By means of the division of V.sub.peak_d by a resistance of the primary-side current sampling resistor R.sub.cs, a digital value corresponding to the peak current I.sub.peak_pof the primary-side winding inductor can be derived. This digital value can be substituted into an expression of I.sub.s(t.sub.mid) to obtain the secondary-side average current I.sub.s(t.sub.mid) in the CCM, thereby obtaining a reasonable deadtime t.sub.d, and achieving a reasonable optimization of the deadtime for the next operating cycle.

(34) FIG. 10 shows an internal structure diagram of the deadtime calculation module. In view of the above analysis, the deadtime consists of the turn-off delay phase and the Miller effect phase of the MOSFET. To calculate the value of the deadtime, it is required to derive a relational expression which the times of the turn-off delay phase and the Miller effect phase should respectively satisfy. The derivation is given respectively below.

(35) Turn-off delay phase: the circuit in this phase is as shown in FIG. 5. According to the above-stated analysis, I.sub.s substantially flows through the channel of the SR transistor in this phase. Therefore, U.sub.ds≈I.sub.sR.sub.ds, U.sub.dg≈I.sub.sR.sub.ds−U.sub.gs. Moreover, C.sub.gs and C.sub.dg are discharged through the resistor R.sub.g, and U.sub.gs drops from U.sub.g to U.sub.p. Therefore, by analyzing the gate of the SR transistor, the following can be obtained:

(36) $\begin{array}{cc}{R}_{g1}\left(C_{\mathrm{gs}}+C_{\mathrm{dg}}\right)\frac{d{U}_{gs}\left(t\right)}{dt}+U_{gs}\left(t\right)=0.& \left(1\right)\end{array}$

(37) By substituting C.sub.iss=C.sub.gs+C.sub.dg into the above formula, a duration ΔT.sub.1 of the turn-off delay phase can be calculated as follows:

(38) $\begin{array}{cc}\Delta T_1=R_g{C}_{\mathrm{iss}}\ln \left(\frac{U_g}{U_P}\right).& \left(2\right)\end{array}$

(39) Since

(40) $U_{gs}\ge U_P,C_{iss}\approx C_{ISS}=\frac{Q_g-Q_{gd}-Q_{gs}}{U_{GS}-U_P}.$
Therefore, the above formula can be written as:

(41) $\begin{array}{cc}\Delta T_1=R_g\frac{Q_g-Q_{gd}-Q_{gs}}{U_{GS}-U_P}\ln \left(\frac{U_g}{U_P}\right).& \left(3\right)\end{array}$

(42) Miller effect phase: the circuit in this phase is as shown in FIG. 6. According to the above-stated analysis, in this phase U.sub.gs and i.sub.g substantially remain constant, that is,

(43) $U_{gs}\left(t\right)\approx U_P,i_g\left(t\right)\approx \frac{U_P}{R_g},$
and i.sub.g merely flows through C.sub.dg and causes U.sub.dg to increase from I.sub.sR.sub.ds−U.sub.p to U.sub.X−U.sub.p. In this process, the charge Q.sub.p dissipated in the gate of the SR transistor can be calculated as follows:

(44) $\begin{array}{cc}{Q}_P={\int }_{I_s{R}_{\mathrm{ds}}-U_P}^{U_X-U_P}{C}_{dg}\left(U_{dg}\right)d{U}_{dg}.& \left(4\right)\end{array}$

(45) According to the above-stated analysis, U.sub.p≈I.sub.sR.sub.ds+U.sub.T and C.sub.dg=C.sub.dg=C.sub.rss1. Therefore, the above-mentioned formula can be derived into:

(46) $\begin{array}{cc}{Q}_P={\int }_{-U_T}^{U_X-I_s{R}_{\mathrm{ds}}-U_T}{C}_{rss1}\left(U_{dg}\right)d{U}_{dg}={\int }_{-U_T}^{U_{\mathrm{DS}}-I_L{R}_{\mathrm{ds}}-U_T}{C}_{\mathrm{rss}1}\left(U_{\mathrm{dg}}\right)d{U}_{\mathrm{dg}}-{\int }_{U_X-I_s{R}_{\mathrm{ds}}-U_T}^{U_{\mathrm{DS}}-I_L{R}_{\mathrm{ds}}-U_T}{C}_{\mathrm{rss}1}\left(U_{dg}\right)d{U}_{dg}=Q_{P1}-Q_{P2}.& \left(5\right)\end{array}$

(47) Taking account into

(48) $Q_{gd}={\int }_{-U_T}^{U_{\mathrm{DS}}-I_L{R}_{\mathrm{ds}}-U_T}{C}_{\mathrm{rss}1}\left(U_{dg}\right)d{U}_{dg},$
so Q.sub.P1=Q.sub.gd.

(49) According to data sheets of MOSFETs, it can be known that

(50) $\begin{array}{cc}{C}_{rss}=\frac{C_{rss}\left(t\right)\sqrt{U_{dg}\left(t\right)}}{\sqrt{U_{dg}}},& \left(6\right)\end{array}$

(51) wherein C.sub.rss(t) is the real-time data of C.sub.rss when U.sub.dg=U.sub.dg(t). C.sub.rss(t) and U.sub.dg(t) are the routine parameters in the data sheets of MOSFETs, and U.sub.dg(t) is normally given as 25V.

(52) When substituting Q.sub.P1=Q.sub.gd and the formula (6) into the formula (5),

(53) it can be derived that:
Q.sub.P=Q.sub.gd−2√{square root over (U.sub.dg(t))}C.sub.rss(t)(√{square root over (U.sub.DS−I.sub.LR.sub.ds−U.sub.T)}−√{square root over (U.sub.X−I.sub.sR.sub.ds−U.sub.T)})  (7)

(54) According to the formula (7) and

(55) 0$i_g\left(t\right)\approx \frac{U_P}{R_g},$
a duration ΔT.sub.2 in this phase (that is, the Miller effect phase) can be calculated as follows:

(56) $\begin{array}{cc}\Delta T_2=\frac{R_g{Q}_P}{U_P}=\frac{R_g}{U_P}\left[Q_{gd}-2\sqrt{U_{dg}\left(t\right)}{C}_{\mathrm{rss}}\left(t\right)\left(\sqrt{U_{DS}-I_L{R}_{ds}-U_T}-\sqrt{U_X-I_s{R}_{ds}-U_T}\right)\right].& \left(8\right)\end{array}$

(57) In summary, the most optimized deadtime t.sub.d between the turn-off of the secondary-side rectifier SR and the turn-on of the primary-side switching transistor SW is:

(58) $\begin{array}{cc}{t}_d=\Delta T_1+\Delta T_2=R_g\frac{Q_g-Q_{gd}-Q_{gs}}{U_{GS}-U_P}\ln \left(\frac{U_g}{U_P}\right)+\frac{R_g}{U_P}\left[\text{⁠}{Q}_{gd}-2\sqrt{U_{dg}\left(t\right)}{C}_{\mathrm{rss}}\left(t\right)\left(\sqrt{U_{DS}-I_L{R}_{ds}-U_T}-\sqrt{U_X-I_s{R}_{ds}-U_T}\right)\right].& \left(9\right)\end{array}$

(59) According to the above-stated analysis, for a given circuit, the variables in the above formulas, except I.sub.s, are all constants. Therefore, the following constants can be defined:

(60) $$\begin{gathered} K_1=R_g\frac{Q_g-Q_{gd}-Q_{gs}}{U_{\mathrm{GS}}-U_P}\ln \left(\frac{U_g}{U_P}\right), \\ {K}_2=\frac{R_g}{U_P}{Q}_{gd}, \\ {K}_3=-\frac{2R_g}{U_P}\sqrt{U_{dg}\left(t\right)}{C}_{\mathrm{rss}}\left(t\right)\sqrt{U_{DS}-I_L{R}_{ds}-U_T}. \end{gathered}$$

(61) For the fourth term in the formula (9), Taylor series is used herein to expand the fourth term, and higher-order terms are negligible:

(62) $f\left(I_s\right)=m-\frac{n}{m}{I}_s-\frac{n^2}{2m^3}{I}_s^2,$

(63) wherein m=√{square root over (U.sub.X−U.sub.T)}, and n=R.sub.ds. Therefore, the deadtime t.sub.d can be represented by:
t.sub.d=K.sub.1+K.sub.2+K.sub.3+f(I.sub.s)   (10).

(64) For the internal block diagram of the deadtime calculation module in FIG. 10, according to the analysis, the variables are constants except that the secondary-side current I.sub.s is the variable. For the four components of the deadtime, K.sub.1, K.sub.2, and K.sub.3 are constants, and the last term f(I.sub.s) is a power function of the secondary-side current I.sub.s. Therefore, the input constants K.sub.1, K.sub.2, and K.sub.3 are input to an adder A.sub.1. A divider D.sub.1 and a multiplier M.sub.1 are used to arrive at a coefficient of I.sub.s. A divider D.sub.2 and multipliers M.sub.2, M.sub.3, and M.sub.4 are used to arrive at a coefficient of I.sub.s.sup.2. Finally, adders A.sub.2 and A.sub.3 are used to arrive at the deadtime t.sub.d.

(65) FIG. 11 shows the PWM driving module. The PWM driving module includes a conventional PWM driving module, which can be the same as the PWM driving unit used in the prior art, including a RS flip-flop, a comparator, a digital to analog converter DAC, and a driving circuit therein. The PWM driving module generates the duty cycle control signal duty for the primary-side switching transistor and the duty cycle control signal duty_SR for the secondary-side synchronous rectifier, resets the RS flip-flop to generate PWM waveforms having different duty cycles, and controls the switching of the primary-side switching transistor and the secondary-side synchronous rectifier. This achieves the conversion from digital signals to time signals, thereby forming the closed loop system for the digitally controlled switching power supply. The control signal duty for the primary-side switching transistor generated by the internal conventional PWM driving unit is used as an output signal to directly control the primary-side switching transistor, and the generated control signal duty_SRI for the secondary-side rectifier can be used to optimize the deadtime only after going through a simple logic circuit. The output t.sub.d from the deadtime calculation module passes through a zero-crossing comparator to generate a positive pulse. The positive pulse passes through an inverter to obtain a negative pulse. When a D flip-flop is triggered by a falling edge of the signal duty_SR, an AND logical operation is performed on the negative pulse and duty_SR, so that the deadtime at this time changes along with the width of the negative pulse, thereby achieving the optimization of the deadtime.

(66) FIG. 12 shows an internal structure diagram of the single-output DAC midpoint sampling module. The single-output DAC midpoint sampling module includes a digital to analog converter DAC, a triangular wave generator, a comparator CMP1, a comparator CMP2, a counter, and a feedback amount calculation module. The function of the single-output DAC midpoint sampling module is to sample a voltage signal V.sub.sense(t.sub.mid) on the auxiliary winding at the midpoint t.sub.mid of the secondary-side current reset time. The flowing direction of the signal is that: the voltage signal V.sub.sense on the auxiliary winding flows in as an input signal, and is input to the positive terminals of the two comparators, and is respectively compared with the voltage signal V.sub.ref_slope of the single slope digital wave and with the zero voltage to obtain a feedback comparison signal V.sub.ref_comp and a zero-crossing comparison signal V.sub.zvs_comp, respectively. The counter counts to obtain values of Δt.sub.r_half and T.sub.r according to changes between high levels and low levels of the feedback comparison signal V.sub.ref_comp and the zero-crossing comparison signal V.sub.zvs_comp. Δt.sub.r_half is a total time required for the single slope digital wave V.sub.ref_slope to rise from the position of the initial voltage V.sub.initial to the position crossing the voltage signal V.sub.sense on the auxiliary winding. T.sub.r is a reset time required for the secondary-side current to drop from the peak value to the lowest point. Finally, the feedback amount calculation module adjusts the digital value of the initial voltage V.sub.initial of the single slope digital wave for the next cycle according to the difference between the values of Δt.sub.r_half and T.sub.r. When the voltage signal V.sub.sense on the auxiliary winding is equal to the voltage signal V.sub.ref_slope of the single slope digital wave, the instant value of the voltage signal V.sub.ref_slope of the single slope digital wave is assigned to the midpoint voltage signal V.sub.sense(t.sub.mid) to output as the output signal of the single-output DAC midpoint sampling module in the current switching cycle. It should be noted that the midpoint voltage signal V.sub.sense(t.sub.mid) can be output for each cycle. Although during a dynamic phase when the load changes and the voltage signal V.sub.sense on the auxiliary winding changes, the midpoint voltage signal V.sub.sense(t.sub.mid) output from the single-output DAC midpoint sampling module is in the strict sense not the voltage signal V.sub.sense(t.sub.mid) on the auxiliary winding at an instant T.sub.r/2, instead is only an approximate amount which gradually approaches. Through the continuous comparison of the values of Δt.sub.r_half and T.sub.r/2 in each cycle, the midpoint voltage signal V.sub.sense(t.sub.mid) output by the single-output DAC midpoint sampling module can have a value that in the strict sense precisely equal to the value of the voltage signal V.sub.sense(t.sub.mid) on the auxiliary winding at the instant T.sub.r/2 by gradually approaching in a plurality of switching cycles. Since the adjustment rate of the single-output DAC midpoint sampling module is high, and the proportion of the dynamically adjusted cycles is very small in comparison with the steady-state cycles, the assigned output signals of the single-output DAC midpoint sampling module are referred to as the midpoint voltage signal V.sub.sense(t.sub.mid) when the voltage signal V.sub.sense on the auxiliary winding for each switching cycle is equal to the voltage signal V.sub.ref_slope of the single slope digital wave.

(67) FIG. 13 shows an internal structure diagram of the digital control module. The digital control module can be the same as the digital control module in the prior art. In an embodiment, it is a digital PI control module, the core of which is a PI control, that is, a proportional-integral control. The digital control module includes an adder, a subtractor, a multiplier, a register, operational amplifiers K.sub.p and K.sub.i, and a mode determination module. The specific connection relationship is that: the midpoint sampling voltage signal V.sub.sense(t.sub.mid) of the DAC and the system-predetermined fixed value V.sub.REF pass through the subtractor to obtain an error e(n). On the one hand, e(n) serves as an input to the register, and on the other hand, controls the mode determination module. The mode determination module outputs two signals V.sub.peak a and a state state. The state signal state is divided into two signals passing through the operational amplifiers, and then are summed through the adder. An output e(n−1) of the register is multiplied by one of the signals from the state state, and the result is transferred to the subsequent subtractor. The summed state signal is multiplied by the error e(n), and passes sequentially through the subtractor and adder to finally obtain a control signal V.sub.c(n). The control signal V.sub.c(n) here is fed back to the adder of the previous level through a register. The input signal is the midpoint sampling voltage signal V.sub.sense(t.sub.mid) of the single-output DAC, and the output signals are the digital value V.sub.peak_d of the peak voltage on the primary-side current sampling resistor R.sub.cs and the control signal V.sub.c(n). The output of the proportional control is proportional to the input error signal. The output of the integral control is proportional to the integration of the input error signal. When the system has only the proportional control, a steady-state error exists in the output. To eliminate the steady-state error, it is required to introduce the integral control. The PI controller can bring the system into a steady state without any steady-state error. According to the error between the midpoint sampling voltage signal V.sub.sense(t.sub.mid) of the single-output DAC as the input signal and the system-predetermined fixed value V.sub.REF, the control amount V.sub.c(n) is calculated by the proportion and integration, thereby eliminating the steady-state error. In addition, the mode determination module can also directly give a digital value V.sub.peak of the peak voltage on the primary-side current sampling resistor R.sub.cs as the output signal according to the value of the error e(n). The expressions are given as following formulas (11) and (12):
V.sub.c(n)=V.sub.c(n−1)+K.sub.p.Math.(e(n)−e(n−1))+K.sub.i.Math.e(n)   (11),
e(n)=V.sub.sense(t.sub.mid)−V.sub.REF   (12).

(68) V.sub.c(n) denotes a control amount in a current cycle. V.sub.c(n−1) denotes a control amount in a previous cycle. e (n) denotes an error in the current cycle. e(n−1) denotes an error in the previous circle. K.sub.p and K.sub.i denote an integral parameter and a differential parameter, respectively, which are not a unique value in the full load range, and need to be set to different values according to different modes.

(69) The present disclosure further provides a control system of a flyback power supply having a primary-side feedback in the CCM. The flyback power supply having the primary-side feedback includes a primary side of a transformer, a secondary side of the transformer, and an auxiliary winding. The primary side includes a primary-side winding, a primary-side switching transistor, and a primary-side current sampling resistor that is in series connected to the primary-side switching transistor. The secondary side includes a secondary-side winding and a secondary-side rectifier. The control system includes: a single-output DAC midpoint sampling module sampling a voltage signal V.sub.sense(t.sub.mid) on the auxiliary winding at a midpoint instant T.sub.r/2 of a secondary-side current reset time T.sub.r; a digital control module calculating an error e(n) between the voltage signal V.sub.sense(t.sub.mid) and a predetermined fixed value V.sub.REF, calculating an input voltage control amount V.sub.c(n) for a PWM driving module by using proportion and integration according to the error e(n), and obtaining a digital value V.sub.peak_d of a peak voltage on the primary-side current sampling resistor R.sub.cs according to the error e(n); a current detection module indirectly sampling and calculating through a digital-to-analog conversion according to the digital value V.sub.peak_d and a voltage V.sub.cs at two terminals of the primary-side current sampling resistor R.sub.cs to obtain a primary-side average current I.sub.mid_p and a secondary-side average current I.sub.s(t.sub.mid) in the CCM; a deadtime calculation module calculating a deadtime t.sub.d between a turn-off of the secondary-side rectifier and a turn-on of the primary-side switching transistor according to the secondary-side average current I.sub.s(t.sub.mid); and the PWM driving module generating a primary-side duty cycle control signal duty and a secondary-side duty cycle control signal duty_SR according to the deadtime t.sub.d and the input voltage control amount V.sub.c(n), and controlling switching of the primary-side switching transistor according to the primary-side duty cycle control signal duty, and controlling switching of the secondary-side rectifier according to the secondary-side duty cycle control signal duty_SR.

(70) In one of the embodiments, the single-output DAC midpoint sampling module includes a digital to analog converter, a triangular wave generator, a comparator CMP1, a comparator CMP2, a counter, and a feedback amount calculation module. The voltage signal V.sub.sense on the auxiliary winding is input as input signals to a positive terminal of the comparator CMP1 and a positive terminal of the comparator CMP2, respectively. After a digital single sloping wave output by the triangular wave generator is superimposed on an analog reference voltage output by the digital to analog converter, a voltage signal V.sub.ref_slope of the single slope digital wave is obtained and is input to a negative terminal of the comparator CMP1. A negative terminal of the comparator CMP2 is connected to zero voltage. The comparator CMP1 outputs a feedback comparison signal V.sub.ref_comp to the counter, and the comparator CMP2 outputs a zero-crossing comparison signal V.sub.zvs_comp to the counter. The counter counts to obtain values of Δt.sub.r_half and T.sub.r according to changes between high levels and low levels of the feedback comparison signal V.sub.ref_comp and the zero-crossing comparison signal V.sub.zvs_comp, in which Δt.sub.r_half is a total time required for the voltage signal V.sub.ref_slope of the single slope digital wave to rise from a position of an initial voltage V.sub.initial to a position crossing the voltage signal V.sub.sense on the auxiliary winding, and T.sub.r is a reset time required for the secondary-side current to drop from a peak value to the lowest point. According to a difference between the values of Δt.sub.r_half and T.sub.r, the feedback amount calculation module outputs a feedback signal V.sub.ref_initial to an input terminal of the triangular wave generator and an input terminal of the digital to analog converter and adjusts a digital value of the initial voltage V.sub.initial for a next cycle. When the voltage signal V.sub.sense on the auxiliary winding is equal to the voltage signal V.sub.ref_slope of the single slope digital wave, the instant value of the voltage signal V.sub.ref_slope of the single slope digital wave is assigned to the voltage signal V.sub.sense(t.sub.mid) to output as an output signal of the single-output DAC midpoint sampling module in a current switching cycle.

(71) In one of the embodiments, the current detection module includes a single-input double-output digital to analog converter, a comparator CMP3, a comparator CMP4, a primary-side current time counting module, and a secondary-side average current calculation module. The single-input double-output digital to analog converter and the secondary-side average current calculation module receive the digital value V.sub.peak_d output by the digital control module. A positive terminal of the comparator CMP3 and a positive terminal of the comparator CMP4 receive the voltage V.sub.cs. A primary-side peak current output by a first output terminal of the single-input double-output digital to analog converter corresponds to the voltage analog value V.sub.peak on the primary-side current sampling resistor, and the voltage analog value V.sub.peak is output to a negative terminal of the comparator CMP3. A second output terminal of the single-input double-output digital to analog converter outputs V.sub.peak half, wherein V.sub.peak_half=k.Math.V.sub.peak, 0<k<1, and the V.sub.peak_half is output to a negative terminal of the comparator CMP4. The comparator CMP3 outputs a comparison signal V.sub.cmp3 to a first counter of the primary-side current time counting module. The comparator CMP4 outputs a comparison signal V.sub.cmp4 to a second counter of the primary-side current time counting module. According to changes of high levels and low levels of the comparison signal V.sub.cmp3 and the comparison signal V.sub.cmp4, the primary-side current time counting module obtains a time t.sub.a required by a linear increase of a primary current from zero amp or an initial current to a peak current in a DCM and a time t.sub.b required by a linear increase of the primary-side current from zero amp or the initial current to the peak current in the CCM, and outputs the times t.sub.a and t.sub.b to the secondary-side average current calculation module. The secondary-side average current calculation module divides the digital value V.sub.peak_d by a resistance of the primary-side current sampling resistor R.sub.cs to obtain a digital value I.sub.peak_p corresponding to a peak current of the primary-side winding inductor, which is substituted into an expression of I.sub.s(t.sub.mid) along with the times t.sub.a and t.sub.b:

(72) $I_s\left(t_{\mathrm{mid}}\right)=\frac{N_p}{N_s}.Math.\frac{\left(1+k\right)t_b-\left(1-k\right)t_a}{2t_b}.Math.I_{pea{k}_{-}p},$

(73) wherein N.sub.p and N.sub.s denote a number of turns of the primary-side winding and the secondary-side winding of the transformer respectively, to obtain and output the secondary-side average current I.sub.s(t.sub.mid) in the CCM.

(74) In one of the embodiments, the deadtime calculation module calculates the deadtime t.sub.d according to the following formulas:

(75) $$\begin{gathered} t_d=K_1+K_2+K_3+f\left(I_s\right), \\ {K}_1=R_g\frac{Q_g-Q_{gd}-Q_{gs}}{U_{GS}-U_P}\ln \left(\frac{U_g}{U_P}\right), \\ {K}_2=\frac{R_g}{U_P}{Q}_{\mathrm{gd}}, \\ {K}_3=-\frac{2R_g}{U_P}\sqrt{U_{dg}\left(t\right)}{C}_{\mathrm{rss}}\left(t\right)\sqrt{U_{DS}-I_L{R}_{ds}-U_T}, \\ f\left(I_s\right)=m-\frac{n}{m}{I}_s-\frac{n^2}{2m^3}{I}_s^2, \\ m=\sqrt{U_X-U_T},n=R_{ds}. \end{gathered}$$

(76) In the above-mentioned formulas, U.sub.p is a Miller plateau voltage. U.sub.g is a gate voltage of the secondary-side rectifier. R.sub.g is a gate resistance of the secondary-side rectifier. Q.sub.g is a total dissipation charge amount of the gate during the turn-off of the secondary-side rectifier. Q.sub.gd is a dissipation charge amount of the gate in a Miller effect phase during the turn-off of the secondary-side rectifier. Q.sub.gs is a dissipation charge amount of the gate in a phase that U.sub.gs decreases from the Miller plateau voltage U.sub.p to 0 during the turn-off of the secondary-side rectifier. I.sub.L is a load current. U.sub.ds is an input voltage of the secondary-side rectifier. C.sub.rss is a reverse transfer capacitance of the secondary-side rectifier. I.sub.s is a secondary-side current. U.sub.X is an experimental measurement. U.sub.T is a threshold voltage of the secondary-side rectifier, and R.sub.ds is a source-drain resistance of the secondary-side rectifier.

(77) In one of the embodiments, the PWM driving module includes a comparator, an inverter, a D flip-flop, an OR-gate, and a PWM driving unit. A positive input terminal of the comparator inputs the deadtime t.sub.d. A negative input terminal of the comparator is connected to zero voltage. An output terminal of the comparator is connected to an input terminal of the inverter. An output terminal of the inverter is connected to a D-input terminal of the D flip-flop. An input signal of the PWM driving unit is the input voltage control amount V.sub.c(n). A first output terminal of the PWM driving unit outputs the primary-side duty cycle control signal duty, and a second output terminal thereof outputs the signal duty_SRI to a clock control terminal of the D flip-flop. A Q-output terminal of the D flip-flop is connected to one input terminal of the OR-gate, the signal duty_SRI is input to the other input terminal of the OR-gate. An output terminal of the OR-gate outputs the secondary-side duty cycle control signal duty_SR.

(78) In one of the embodiments, the secondary-side rectifier is a MOS transistor.

(79) In one of the embodiments, the primary-side switching transistor is a MOS transistor. The primary-side current sampling resistor is connected in series between the source of the primary-side switching transistor and the ground.

(80) The present disclosure further provides a method of controlling a flyback power supply having a primary-side feedback in the CCM. The flyback power supply having the primary-side feedback includes a primary side of a transformer, a secondary side of the transformer, and an auxiliary winding. The primary side includes a primary-side winding, a primary-side switching transistor, and a primary-side current sampling resistor that is connected in series to the primary-side switching transistor. The secondary side includes a secondary-side winding and a secondary-side rectifier. The method includes: sampling a voltage signal V.sub.sense(t.sub.mid) on the auxiliary winding at a midpoint instant T.sub.r/2 of a secondary-side current reset time T.sub.r; calculating an error e(n) between the voltage signal V.sub.sense(t.sub.mid) and a predetermined fixed value V.sub.REF, calculating an input voltage control amount V.sub.c(n) for a PWM driving module by using proportion and integration according to the error e(n), and obtaining a digital value V.sub.peak_d of a peak voltage on the primary-side current sampling resistor R.sub.cs according to the error e(n); indirectly sampling and calculating to obtain a primary-side average current I.sub.mid_p and a secondary-side average current I.sub.s(t.sub.mid) in the CCM through a digital-to-analog conversion according to the digital value V.sub.peak_d and a voltage V.sub.cs at two terminals of the primary-side current sampling resistor R.sub.cs; calculating a deadtime t.sub.d between a turn-off of the secondary-side rectifier and a turn-on of the primary-side switching transistor according to the secondary-side average current I.sub.s(t.sub.mid); generating, by the PWM driving module, a primary-side duty cycle control signal duty and a secondary-side duty cycle control signal duty_SR according to the deadtime t.sub.d and the input voltage control amount V.sub.c(n); and controlling switching of the primary-side switching transistor according to the primary-side duty cycle control signal duty, and controlling switching of the secondary-side rectifier according to the secondary-side duty cycle control signal duty_SR.

(81) In one of the embodiments, the step of sampling the voltage signal V.sub.sense(t.sub.mid) on the auxiliary winding at the midpoint instant T.sub.r/2 of the secondary-side current reset time T.sub.r, includes:

(82) inputting, by a positive terminal of a comparator CMP1, a voltage signal V.sub.sense on the auxiliary winding, after superimposition of a digital single sloping wave output by a triangular wave generator and an analog reference voltage output by a digital to analog converter, obtaining a voltage signal V.sub.ref_slope of a single slope digital wave to output to a negative terminal of the comparator CMP1, and outputting, by the comparator CMP1, a feedback comparison signal V.sub.ref_comp;

(83) inputting, by a positive terminal of a comparator CMP2, the voltage signal V.sub.sense on the auxiliary winding, inputting, by a negative terminal thereof, zero voltage, and outputting, by the comparator CMP2, a zero-crossing comparison signal V.sub.zvs_comp;

(84) counting to obtain values of Δt.sub.r_half and T.sub.r according to changes between high levels and low levels of the feedback comparison signal V.sub.ref_comp and the zero-crossing comparison signal V.sub.zvs_comp, wherein Δt.sub.r_half is a total time required for the voltage signal V.sub.ref_slope of the single slope digital wave to rise from a position of an initial voltage V.sub.initial to a position crossing the voltage signal V.sub.sense on the auxiliary winding, and T.sub.r is a reset time required for a secondary-side current to drop from a peak value to a lowest point;

(85) outputting a feedback signal V.sub.ref_initial to an input terminal of the triangular wave generator and an input terminal of the digital to analog converter and adjusting a digital value of the initial voltage V.sub.initial for a next cycle according to a difference between the values of Δt.sub.r_half and T.sub.r; and

(86) assigning, when the voltage signal V.sub.sense on the auxiliary winding is equal to the voltage signal V.sub.ref_slope of the single slope digital wave, an instant value of the voltage signal V.sub.ref_slope of the single slope digital wave to the voltage signal V.sub.sense(t.sub.mid)

(87) In one of the embodiments, the step of indirectly sampling and calculating to obtain the primary-side average current I.sub.mid_p and the secondary-side average current I.sub.s(t.sub.mid) in the CCM through the digital-to-analog conversion according to the digital value V.sub.peak_d and the voltage V.sub.cs at the two terminals of the primary-side current sampling resistor R.sub.cs, includes:

(88) receiving, by a positive terminal of a comparator CMP3 and a positive terminal of a comparator CMP4, the voltage V.sub.cs;

(89) performing a digital-to-analog conversion on the digital value V.sub.peak_d to obtain a voltage analog value V.sub.peak on the primary-side current sampling resistor corresponding to a primary-side peak current and output the voltage analog value V.sub.peak to a negative terminal of the comparator CMP3, and to obtain V.sub.peak_half and output the V.sub.peak_half to a negative terminal of the comparator CMP4, wherein V.sub.peak_half=k.Math.V.sub.peak, 0<k<1;

(90) obtaining, according to changes between high levels and low levels of a comparison signal V.sub.cmp3 output by the comparator CMP3 and changes between high levels and low levels of a comparison signal V.sub.cmp4 output by the comparator CMP4, a time t.sub.a required by a linear increase of a primary-side current from zero amp or an initial current to a peak current in a DCM and a time t.sub.b required by a linear increase of the primary-side current from zero amp or the initial current to the peak current in the CCM;

(91) dividing the digital value V.sub.peak_d by a resistance of the primary-side current sampling resistor R.sub.cs to obtain a digital value I.sub.peak_p of a peak current of a primary-side winding inductor; and

(92) substituting the digital value I.sub.peak_p, and the times t.sub.a and t.sub.b into an expression of I.sub.s(t.sub.mid):

(93) $I_s\left(t_{\mathrm{mid}}\right)=\frac{N_p}{N_s}.Math.\frac{\left(1+k\right)t_b-\left(1-k\right)t_a}{2t_b}.Math.I_{pea{k}_{-}p},$

(94) wherein N.sub.p and N.sub.s denote a number of turns of the primary-side winding and the secondary-side winding of the transformer respectively, to obtain the secondary-side average current I.sub.s(t.sub.mid) in the CCM.

(95) In one of the embodiments, during the step of calculating the deadtime t.sub.d between the turn-off of the secondary-side rectifier and the turn-on of the primary-side switching transistor according to the secondary-side average current I.sub.s(t.sub.mid), the deadtime t.sub.d is calculated according to following formulas:

(96) $$\begin{gathered} t_d=K_1+K_2+K_3+f\left(I_s\right), \\ {K}_1=R_g\frac{Q_g-Q_{gd}-Q_{gs}}{U_{GS}-U_P}\ln \left(\frac{U_g}{U_P}\right), \\ {K}_2=\frac{R_g}{U_P}{Q}_{\mathrm{gd}}, \\ {K}_3=-\frac{2R_g}{U_P}\sqrt{U_{dg}\left(t\right)}{C}_{\mathrm{rss}}\left(t\right)\sqrt{U_{DS}-I_L{R}_{ds}-U_T}, \\ f\left(I_s\right)=m-\frac{n}{m}{I}_s-\frac{n^2}{2m^3}{I}_s^2, \\ m=\sqrt{U_X-U_T},n=R_{ds}. \end{gathered}$$

(97) In the above-mentioned formulas, U.sub.p is a Miller plateau voltage, U.sub.g is a gate voltage of the secondary-side rectifier, R.sub.g is a gate resistance of the secondary-side rectifier, Q.sub.g is a total dissipation charge amount of the gate during the turn-off of the secondary-side rectifier, Q.sub.gd is a dissipation charge amount of the gate in a Miller effect phase during the turn-off of the secondary-side rectifier, Q.sub.gs is a dissipation charge amount of the gate in a phase that U.sub.gs decreases from the Miller plateau voltage U.sub.p to 0 during the turn-off of the secondary-side rectifier, I.sub.L is a load current, U.sub.ds is an input voltage of the secondary-side rectifier, C.sub.rss is a reverse transfer capacitance of the secondary-side rectifier, I.sub.s is a secondary-side current, U.sub.X is an experimental measurement, U.sub.T is a threshold voltage of the secondary-side rectifier, and R.sub.ds is a source-drain resistance of the secondary-side rectifier.