METHOD AND APPARATUS WITH NEURAL RECORDING

Abstract

A neural recording apparatus including an electrode array including a plurality of electrodes configured to detect voltage signals of one or more neurons and a reference electrode configured to detect a reference signal, a regulator configured to regulate the reference signal, a plurality of transconductance circuits configured to generate current signals by performing transconductance based on the voltage signals and the regulated reference signal, a multiplexer (MUX) configured to multiplex on the generated current signals, and an analog-to-digital converter (ADC) configured to convert the multiplexed current signals into a digital signal

Claims

1. A neural recording apparatus, the apparatus comprising: an electrode array comprising: a plurality of electrodes configured to respectively detect voltage signals of one or more neurons; and a reference electrode configured to detect a reference signal of a neuron; a regulator configured to regulate the reference signal; transconductance circuits configured to generate respective current signals by performing transconductance based on multiple voltage signals, of the detected voltage signals, and the regulated reference signal; a first multiplexer (MUX) configured to multiplex the current signals; and an analog-to-digital converter (ADC) configured to convert the multiplexed current signals into a digital signal, wherein each of the transconductance circuits comprises: a transistor configured to perform the transconductance; and a capacitor connected to the transistor, and wherein the regulator is configured to apply the regulated reference signal to the transistor of each of the transconductance circuits as a source voltage.

2. The apparatus of claim 1, wherein each of the transconductance circuits further comprises a bias resistance connected to a respective gate of the transistor of each of the transconductance circuits and to one end of the capacitor of each of the transconductance circuits.

3. The apparatus of claim 1, wherein each of the transconductance circuits is configured to receive each of the detected voltage signals, and wherein the capacitor of each of the transconductance circuits is configured to remove a direct current (DC) component of a respectively received voltage signal.

4. The apparatus of claim 3, wherein each of the voltage signals from which the DC component is removed and each of bias signals are configured to be applied as a gate voltage of the transistor of each of the transconductance circuits.

5. The apparatus of claim 1, further comprising a control circuit configured to merge current signals corresponding to a same neuron among the current signals.

6. The apparatus of claim 5, wherein the control circuit is configured to control the first MUX so that the current signals corresponding to the same neuron are simultaneously output from the first MUX.

7. The apparatus of claim 1, further comprising: a first voltage source configured to generate a first voltage signal in a test mode for performing calibration and configured not to generate the first voltage signal in a measurement mode for detecting the voltage signals; and a second voltage source configured to generate a test voltage signal in the test mode and configured not to generate the test voltage signal in the measurement mode.

8. The apparatus of claim 7, wherein the regulator comprises: an operational amplifier; and a second MUX connected to an input terminal of the operational amplifier, the second MUX being configured to transmit the first voltage signal to the operational amplifier in the test mode and configured to transmit the reference signal to the operational amplifier in the measurement mode, wherein each of the transconductance circuits further comprises a third MUX, the third MUX being configured to transmit the test voltage signal to the capacitor of each of the transconductance circuits in the test mode and configured to transmit each of the detected voltage signals to the capacitor of each of the transconductance circuits in the measurement mode.

9. The apparatus of claim 1, wherein the regulator, the plurality of transconductance circuits, the MUX, and the ADC comprise an analog front-end (AFE) circuit.

10. The apparatus of claim 1, further comprising a communication circuit configured to transmit the digital signal to an external device.

11. A neural recording apparatus, the apparatus comprising: an electrode array comprising: a plurality of electrodes configured to respectively detect voltage signals of one or more neurons; and a reference electrode configured to detect a reference signal of a neuron; a regulator configured to regulate the reference signal; transconductance circuits configured to generate current signals by performing transconductance based on multiple voltage signals, of the detected voltage signals, and the regulated reference signal; an analog-to-digital converter (ADC); a plurality of switches positioned between the transconductance circuits and the ADC; and a control circuit configured to turn on a switch of each of the transconductance circuits that generates the current signals corresponding to a same neuron among the plurality of switches so that current signals corresponding to the same neuron among the current signals are merged and input to the ADC, wherein each of the transconductance circuits comprises: a transistor configured to perform the transconductance; and a capacitor connected to the transistor, and wherein the regulator is configured to apply the regulated reference signal to the transistor of each of the transconductance circuits as a source voltage.

12. The apparatus of claim 11, wherein the control circuit is configured to: turn on first switches among the plurality of switches so that first current signals corresponding to a first neuron among the current signals are merged and input to the ADC while turning off second switches, the second switches comprising a first remaining portion of the plurality of switches excluding the first switches; and turn on third switches among the plurality of switches so that second current signals corresponding to a second neuron among the current signals are merged and input to the ADC while turning off fourth switches, the fourth switches comprising a second remaining portion of the plurality of switches excluding for the third switches.

13. The apparatus of claim 11, wherein each of the transconductance circuits further comprises a bias resistance connected to a respective gate of the transistor of each of the transconductance circuits and one end of the capacitor of each of the transconductance circuits.

14. The apparatus of claim 11, wherein each of the transconductance circuits is configured to receive each of the voltage signals, and wherein the capacitor of each of the transconductance circuits is configured to remove a direct current (DC) component of a respectively received voltage signal.

15. The apparatus of claim 14, wherein each of the voltage signals from which the DC component is removed and each of bias signals are configured to be applied as a gate voltage of the transistor of each of the transconductance circuits.

16. The apparatus of claim 11, further comprising: a first voltage source configured to generate a first voltage signal in a test mode for performing calibration and configured not to generate the first voltage signal in a measurement mode for detecting the voltage signals; and a second voltage source configured to generate a test voltage signal in the test mode and configured not to generate the test voltage signal in the measurement mode.

17. The apparatus of claim 16, wherein the regulator comprises: an operational amplifier; and a MUX connected to an input terminal of the operational amplifier and configured to transmit the first voltage signal to the operational amplifier in the test mode and configured to transmit the reference signal to the operational amplifier in the measurement mode, wherein each of the transconductance circuits further comprises a second MUX configured to transmit the test voltage signal to the capacitor of each of the transconductance circuits in the test mode and configured to transmit each of the voltage signals to the capacitor of each of the transconductance circuits in the measurement mode.

18. The apparatus of claim 11, wherein the regulator, the plurality of transconductance circuits, the ADC, the plurality of switches, and the control circuit comprise an analog front-end (AFE) circuit.

19. A method of operating a neural recording apparatus, the method comprising: detecting voltage signals of one or more neurons and a reference signal of a neuron through an electrode array; generating current signals by performing respective transconductances on the detected voltage signals, each transconductance being based on the reference signal; performing multiplexing on the current signals through a multiplexer (MUX); and converting the multiplexed current signals into a digital signal through an analog-to-digital converter (ADC).

20. The method of claim 19, further comprising merging current signals corresponding to a same neuron among the generated current signals.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0026] FIG. 1 illustrates an example of a neural recording apparatus according to one or more embodiments.

[0027] FIG. 2 illustrates an example of an analog front-end (AFE) circuit of a neural recording apparatus according to one or more embodiments.

[0028] FIG. 3 illustrates an example of an AFE circuit of a neural recording apparatus according to one or more embodiments.

[0029] FIG. 4 illustrates an example of a transconductance circuit in an AFE circuit according to one or more embodiments.

[0030] FIGS. 5 and 6 illustrate an example of an AFE circuit of a neural recording apparatus according to one or more embodiments.

[0031] FIG. 7 illustrates an example of an AFE circuit of a neural recording apparatus according to one or more embodiments.

[0032] FIGS. 8A and 8B illustrate an example of merging current signals corresponding to the same neuron in an AFE circuit of a neural recording apparatus according to one or more embodiments.

[0033] FIG. 9 illustrates an example of an AFE circuit of a neural recording apparatus according to one or more embodiments.

[0034] FIG. 10 illustrates an example of a method of operating a neural recording apparatus according to one or more embodiments.

[0035] Throughout the drawings and the detailed description, unless otherwise described or provided, the same or like drawing reference numerals may be understood to refer to the same elements, features, and structures. The drawings may not be to scale, and the relative size, proportions, and depiction of elements in the drawings may be exaggerated for clarity, illustration, and convenience.

DETAILED DESCRIPTION

[0036] The following detailed description is provided to assist the reader in gaining a comprehensive understanding of the methods, apparatuses, and/or systems described herein. However, various changes, modifications, and equivalents of the methods, apparatuses, and/or systems described herein will be apparent after an understanding of the disclosure of this application. For example, the sequences of operations described herein are merely examples, and are not limited to those set forth herein, but may be changed as will be apparent after an understanding of the disclosure of this application, with the exception of operations necessarily occurring in a certain order.

[0037] The features described herein may be embodied in different forms and are not to be construed as being limited to the examples described herein. Rather, the examples described herein have been provided merely to illustrate some of the many possible ways of implementing the methods, apparatuses, and/or systems described herein that will be apparent after an understanding of the disclosure of this application.

[0038] Advantages and features of the present disclosure and methods of achieving the advantages and features will be clear with reference to embodiments described in detail below together with the accompanying drawings. However, the present disclosure is not limited to the embodiments disclosed herein but will be implemented in various forms. The embodiments of the present disclosure are provided so that the present disclosure is disclosed, and a person with ordinary skill in the art can understand the scope of the present disclosure. Meanwhile, the terms used in the present specification are for explaining the embodiments, not for limiting the present disclosure. The use of the term may herein with respect to an example or embodiment (for example, as to what an example or embodiment may include or implement) means that at least one example or embodiment exists where such a feature is included or implemented, while all examples are not limited thereto.

[0039] Terms, such as first, second, A, B, (a), (b) or the like, may be used herein to describe components. Each of these terminologies is not used to define an essence, order or sequence of a corresponding component but used merely to distinguish the corresponding component from other component(s). For example, a first component may be referred to as a second component, and similarly the second component may also be referred to as the first component.

[0040] Throughout the specification, when a component is described as being connected to, or coupled to another component, it may be directly connected to, or coupled to the other component, or there may be one or more other components intervening therebetween. In contrast, when an element is described as being directly connected to, or directly coupled to another element, there can be no other elements intervening therebetween.

[0041] In a description of the embodiment, in a case in which any one element is described as being formed on or under another element, such a description includes both a case in which the two elements are formed in direct contact with each other and a case in which the two elements are in indirect contact with each other with one or more other elements interposed between the two elements. In addition, when one element is described as being formed on or under another element, such a description may include a case in which the one element is formed at an upper side or a lower side with respect to another element.

[0042] The singular forms a, an, and the are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms comprises/comprising and/or includes/including when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof.

[0043] FIG. 1 illustrates an example of a neural recording apparatus.

[0044] Referring to FIG. 1, a neural sensing system 50 includes a neural recording apparatus 100 may include an electrode array 110 and an analog front-end (AFE) circuit 120. The neural sensing system may further include a communication circuit 130 in communication with the neural recording apparatus, and a processor and memory 155 which may communicate with the communication circuit 130.

[0045] The neural recording apparatus 100 may be implemented as a chip.

[0046] The electrode array 110 may correspond to a microelectrode array (MEA).

[0047] The electrode array 110 may include a plurality of electrodes. For example, the electrodes may be spaced apart by a 20 micrometer (pm) pitch.

[0048] Each of the electrodes of the electrode array 110 may be configured to detect or obtain an electrical signal (e.g., a voltage signal) generated from a target. The target may include neural targets such as a neuron, a brain cell, or a brain nerve cell that are in contact with each of one or more electrodes, and which generate respective voltages in response to a stimulation, e.g., from other target(s) and/or from the respective electrodes of the electrode array 110. For example, the neural recording apparatus 100 may stimulate the target of each of the electrodes by applying respective electrical signals to the target using the one or more electrodes of the electrode array 110. The applied electrical signals may respectively be one of a voltage signal or a current signal. When the target of each of the electrodes is stimulated by the applied electrical signal, a voltage signal may be generated by/at each target, and each of the one or more electrodes of the electrode array 110 may be used to detect the voltage signal generated by the target.

[0049] In an example, the electrode array 110 may include one or more reference electrodes.

[0050] The reference electrode of the electrode array 110 may detect or obtain a reference electrical signal of a target that is in contact with the reference electrode. In one example, the neural recording apparatus 100 may stimulate the target of the reference electrode by applying the electrical signal (e.g., the applied electrical signal) to the target of the reference electrode through the reference electrode of the electrode array 110. When the target of the reference electrode is stimulated by the applied electrical signal, a voltage signal may be generated, and the reference electrode may detect the voltage signal generated by the target. The electrical signal detected by the reference electrode may be referred to as a reference signal, or reference electrical signal.

[0051] Each of the electrodes of the electrode array 110 may transmit their detected (or obtained) electrical signal to the AFE circuit 120. The reference electrode of the electrode array 110 may transmit the detected reference electrical signal to the AFE circuit 120.

[0052] The AFE circuit 120 may generate a digital signal based on the electrical signals received from the electrodes of the electrode array 110 and the reference signal received from the reference electrode of the electrode array 110. For example, the AFE circuit 120 may regulate the reference signal and may generate current signals by performing transconductance based on the detected voltage signals and the regulated reference signal through transconductance circuits. In one example, the transconductance may include a conversion and an amplification from a voltage to a current. The AFE circuit 120 may perform multiplexing on the generated current signals through a multiplexer (MUX) and convert the multiplexed current signals into a digital signal through an analog-to-digital converter (ADC).

[0053] As will be described in detail below, as the AFE circuit 120 may process the multiplexed current signals with one ADC for generating the digital signal, the area per channel of the AFE circuit 120 may be small at the level of the electrode size of the electrode array 110. That is, an AFE channel may be secured in each pitch of the microelectrode. In addition, since the AFE circuit 120 may perform multiplexing after performing amplification through the transconductance circuits, a memory effect may be prevented and a crosstalk phenomenon may be reduced or eliminated.

[0054] The neural recording apparatus 100 may include the communication circuit (or a communication interface) 130. The communication circuit may communicate by wire or wirelessly (e.g., where the communication circuit 130 is representative of one or more transceivers). The communication circuit 130 may communicate with the AFE 120, for example, to provide generated digital signals to the processor and memory 155. Accordingly, the neural recording apparatus 100 may transmit the digital signal(s) generated by one or more of the AFE circuits 120 to the processor and memory 155, which may be an external terminal (e.g., a computing device), through the communication circuit 130. The external terminal may analyze the activity of many targets by processing the digital signal(s) received from the neural recording apparatus 100. For example, the external terminal may analyze and/or map biological neural activities and/or connections using the received digital signal(s).

[0055] For example, the AFE circuit 120, according to an example, may be applied to the neural recording and a technique using the MEA (e.g., a digital physiology technique, a drug screening technique, etc.).

[0056] FIG. 2 illustrates an example of an AFE circuit of a neural recording apparatus.

[0057] The AFE circuit 200 shown in FIG. 2 may correspond to the AFE circuit 120 of FIG. 1.

[0058] Referring to FIG. 2, the AFE circuit 200 may include a plurality of transconductance circuits 210-1 to 210-3, a MUX 220, and an ADC 230.

[0059] Although the AFE circuit 200 includes three transconductance circuits 210-1 to 210-3 in FIG. 2, this is merely an example, and the AFE circuit 200 may include three or more transconductance circuits.

[0060] In FIG. 2, each of V.sub.i1, V.sub.i2, and V.sub.i3 may represent, for example, respective voltage signals detected by, and provided through, each of electrode.sub.1, electrode.sub.2, and electrode.sub.3 of the electrode array 110, and V.sub.ref may represent a reference signal, such as discussed above.

[0061] The transconductance circuits 210-1 to 210-3 may generate respective current signal I.sub.1, I.sub.2, and I.sub.3 by performing respective transconductance on a corresponding input voltage signal. As illustrated in the example of FIG. 2, the input signals include one or more input voltage signals V.sub.i and as well as a reference voltage signal V.sub.ref. In addition, the transconductance circuits 210-1 to 210-3 may transmit each of their respective current signals to the MUX 220. For example, the transconductance circuit 210-1 may generate a current signal I.sub.1 corresponding to Gm (V.sub.i1V.sub.ref) from the input voltage signal V.sub.i1 and V.sub.ref. Here, Gm may represent a gain from an amplification or an amplifier. The transconductance circuit 210-1 may transmit the current signal I.sub.1 to the MUX 220. The transconductance circuit 210-2 may generate a current signal I.sub.2 corresponding to Gm (V.sub.i2V.sub.ref) from the input voltage signal V.sub.i2 and V.sub.ref. The transconductance circuit 210-2 may transmit the current signal I.sub.2 to the MUX 220. The transconductance circuit 210-3 may generate a current signal I.sub.3 corresponding to Gm (V.sub.i3V.sub.ref) from the input voltage signal V.sub.i3 and V.sub.ref. The transconductance circuit 210-3 may transmit the current signal I.sub.3 to the MUX 220.

[0062] The MUX 220 may perform multiplexing on the input current signals I.sub.1, I.sub.2, and I.sub.3. After performing the multiplexing on the input current signals, the MUX 220 may then transmit the multiplexed current signals I.sub.MUX to the ADC 230.

[0063] Referring to FIG. 2, the MUX 220 may perform multiplexing on the input current signals I.sub.1, I.sub.2, and I.sub.3 in a time domain. That is, the MUX 220 may perform time division multiplexing (TDM) on the input current signals I.sub.1, I.sub.2, and I.sub.3. For example, the MUX 220 may transmit the current signal I.sub.1, the current signal I.sub.2, and the current signal I.sub.3 in an order of the current signal I.sub.1, the current signal I.sub.2, and the current signal I.sub.3 to the ADC 230.

[0064] In an example, the MUX 220 may perform multiplexing on the input current signals I.sub.1, I.sub.2, and I.sub.3 in a frequency domain. For example, the MUX 220 may modulate each of the current signals I.sub.1, I.sub.2, and I.sub.3 into different frequencies, e.g., respective modulation frequency 1 (MOD1), modulation frequency 2 (MOD2), and modulation frequency 3 (MOD3) shown in FIG. 3. The MUX 220 may then transmit the modulated current signal I.sub.1, the modulated current signal I.sub.2, and the modulated current signal I.sub.3 to the ADC 230.

[0065] The ADC 230 may convert the input current signal (e.g., the multiplexed current signals I.sub.MUX) into a digital signal D.sub.out.

[0066] A multi-channel may be formed (or included) in the neural recording apparatus 100. Here, each of the channels of the multi-channel may respectively include, for each of the electrodes, a corresponding transconductance circuit for a corresponding electrode of the electrodes, the MUX 220, and the ADC 230. In the example shown in FIG. 2, three channels may be formed. For example, a channel 1 may include an electrode.sub.1 that detects V.sub.i1, the corresponding transconductance circuit 210-1 of the electrode.sub.1, the MUX 220, and the ADC 230. That is, the electrode.sub.1, the corresponding transconductance circuit 210-1 of the electrode.sub.1, the MUX 220, and the ADC 230 may form channel 1. Channel 2 may include an electrode.sub.2 that detects V.sub.i2, the corresponding transconductance circuit 210-2 of the electrode.sub.2, the MUX 220, and the ADC 230. That is, the electrode.sub.2 that measures V.sub.i2, the corresponding transconductance circuit 210-2 of the electrode.sub.2, the MUX 220, and the ADC 230 may form channel 2. Channel 3 may include an electrode.sub.3 that measures V.sub.i3, the corresponding transconductance circuit 210-3 of the electrode.sub.3, the MUX 220, and the ADC 230. That is, the electrode 3 that measures V.sub.i3, the corresponding transconductance circuit 210-3 of the electrode.sub.3, the MUX 220, and the ADC 230 may form channel 3. Channel 1, channel 2, and channel 3 may share the MUX 220 and ADC 230.

[0067] In the example shown in FIG. 2, the AFE 200 may convert (or combine) the multi-channel signals I.sub.1, I.sub.2, and I.sub.3 into the single signal I.sub.MUX through the MUX 220 and a single ADC, such as ADC 230, may be used to process a single signal. Accordingly, an area per channel of the AFE 200 (or the area per channel allocated to the ADC 230) may be reduced to the level of the electrode's size, and each corresponding circuitry of the AFE 200, for receiving a voltage measured from a corresponding electrode, may be disposed in a chip and/or attached to the electrode array 110 with a pitch matching the pitch of the electrodes of the electrode array 110. This pitch relationship between the AFE 200 and the electrode array 110 with respect to FIG. 2 is also applicable to the remaining examples.

[0068] The electrical signals detected by the electrodes of the electrode array 110 may have a very small amplitude (e.g., several tens to several hundred microvolt (V)) and a high contact impedance (e.g., several tens to several hundreds of megohm M). When the detected electrical signals are multiplexed and then amplified, a memory effect due to the contact impedance may occur, a crosstalk phenomenon may occur, and a signal-to-noise ratio (SNR) drop may occur.

[0069] Because the AFE 200 may perform multiplexing after amplifying through the transconductance circuits 210-1 to 210-3 such as those shown in the example of FIG. 2, the memory effect may not occur, the crosstalk phenomenon may be reduced or eliminated, and the SNR drop may be prevented.

[0070] FIG. 3 illustrates an example of an AFE circuit of a neural recording apparatus.

[0071] Referring to FIG. 3, the AFE circuit 300 shown in FIG. 3 may correspond to the example of the AFE circuit 120 of FIG. 1. In addition,

[0072] the AFE circuit 300 may include a plurality of transconductance circuits 210-1 to 210-3, a plurality of modulators 310-1 to 310-3, and the ADC 230.

[0073] The operation of the modulators 310-1 to 310-3 may correspond to the example of multiplexing in the frequency domain of the MUX 220 of FIG. 2.

[0074] Each of the modulators 310-1 to 310-3 may include, for example, a chopper, but is not limited thereto.

[0075] Each of the modulators 310-1 to 310-3 may respectively perform modulation (e.g., chopper modulation) on an input current signal and may transmit each of the modulated current signals to the ADC 230.

[0076] In the example shown in FIG. 3, similar to the AFE 200, the area per channel of the AFE 300 may be reduced to the level of the electrode size. In addition, similar to the AFE 200, since the AFE 300 may perform modulation after performing amplification through the transconductance circuits 210-1 to 210-3, the memory effect may not occur, the crosstalk phenomenon may be reduced or eliminated, and the SNR drop may not be prevented.

[0077] FIG. 4 illustrates an example of a transconductance circuit 400 in an AFE circuit.

[0078] Referring to FIG. 4, a transconductance circuit 400 may include a capacitor 410, a bias resistance 420, and a transistor 430.

[0079] The transconductance circuit 400 of FIG. 4 may be any of, or each of, the transconductance circuits 210-1 to 210-3 described with reference to FIGS. 2 to 3. That is, a structure of each of the transconductance circuits 210-1 to 210-3 may be the same as that of the transconductance circuit 400.

[0080] In the example of FIG. 4, the transconductance circuit 400 outputs a current signal I based on the reference voltage V.sub.ref and the input voltage signal V.sub.i provided to the capacitor 410. The capacitor 410 may remove a direct current (DC) component of the input voltage signal V.sub.i. For example, when an electrode is in contact with a neuron, a DC potential may occur between the electrode and the neuron. The voltage signal V.sub.i may include the DC potential and the capacitor 410 may remove the DC potential from the input voltage signal V.sub.i.

[0081] The transistor 430 may perform transconductance. The bias resistance 420 may be connected to one end of the capacitor 410 and a gate of the transistor 430.

[0082] As discussed above, the capacitor 410 may remove the DC component from the input voltage signal V.sub.i and a bias signal V.sub.b may also be applied to the gate of the transistor 430. That is, the voltage signal (e.g., the voltage signal from which the DC component is removed) passing through the capacitor 410 and the bias signal V.sub.b may be applied as the gate voltage of the transistor 430. A reference signal V.sub.ref may be applied to the source of the transistor 430. When the gate voltage and the source voltage are applied, the transistor 400 may generate and output the current signal I corresponding to Gm (V.sub.iV.sub.ref).

[0083] In one example, each respective transconductance circuit 400 of the electrode array may be separated by a pitch that matches the corresponding pitch between the respective electrodes. Each transconductance circuit 400 may be repeated for each electrode so respective input voltage signals V.sub.i of different electrodes are provided at different pitch positions that match the different pitch positions of the electrodes, while the same measured reference voltage V.sub.ref may be provided to each transconductance circuit 400.

[0084] An element performing transconductance may include an operational transconductance amplifier (OTA). The OTA may include a plurality of transistors (e.g., five or more transistors), and thus has a size larger than the transconductance circuit 400 of FIG. 4. When each of the transconductance circuits 210-1 to 210-3 described with reference to FIGS. 2 to 3 are provided with the structure of the transconductance circuit 400, the sizes of the AFE circuits 120, 200, and 300 may be further reduced than when each of the transconductance circuits 210-1 to 210-3 corresponds to the OTA.

[0085] FIGS. 5 and 6 each illustrate examples of an AFE circuit of a neural recording apparatus.

[0086] Referring to FIG. 5, an AFE circuit 500 may correspond to the example of the AFE circuit 120 of FIG. 1.

[0087] Referring to FIG. 5, the AFE circuit 500 may include a regulator 510, the plurality of transconductance circuits 210-1 to 210-3, the MUX 220, and the ADC 230.

[0088] The regulator 510 may perform regulating (or boosting) on the reference signal V.sub.ref and may output (or provide) a regulated reference signal V.sub.ref_reg to each of the transconductance circuits 210-1 to 210-3. As described with reference to FIG. 4, each of the transconductance circuits 210-1 to 210-3 may include a transistor. In some examples, the amplitude of the reference signal V.sub.ref may be too small to drive a source of the transistor of each of the transconductance circuits 210-1 to 210-3. The regulator 510 may regulate and boost a signal provided thereto to generate a boosted and regulated signal. Accordingly, in one or more examples, where the reference signal V.sub.ref is too small to drive a source of the transistor, the resulting boosted reference may be large enough to drive the source of the transistor. The regulator 510 may apply this regulated reference signal V.sub.ref_reg (or the boosted reference signal) to a source of the transistor of each of the transconductance circuits 210-1 to 210-3.

[0089] Referring to FIG. 6, the regulator 510 may include a capacitor 610, a bias resistance 620, an operational amplifier (or a comparator) 630, and a transistor 640.

[0090] The capacitor 610 and the bias resistance 620 may be connected to a first terminal (-terminal) of the operational amplifier 630. An output signal of the transistor 640 may be fed back to a second terminal (+terminal) of the operational amplifier 630.

[0091] An output terminal of the operational amplifier 630 may be connected to a gate of the transistor 640. A drain of the transistor 640 may be electrically connected to a source of the transistor of each of the transconductance circuits 210-1 to 210-3.

[0092] The transistor 640 may output the regulated reference signal V.sub.ref_reg, for example, when both an output signal of the operational amplifier 630 is applied as a gate voltage and a source voltage is applied.

[0093] A circuit configuration of the regulator 510 illustrated in FIG. 6 is merely an example, and the circuit configuration of the regulator 510 is not limited to the descriptions illustrated in FIG. 6.

[0094] The regulator 510 may apply the regulated reference signal V.sub.ref_reg to a source of the transistor of each of the transconductance circuits 210-1 to 210-3. That is, each of the regulated reference signals V.sub.ref_reg may be applied to the transistor of each of the transconductance circuits 210-1 to 210-3 to a source voltage.

[0095] Each of the transconductance circuits 210-1 to 210-3 may generate and output a current signal corresponding to Gm (V.sub.iV.sub.ref_reg). For example, the transconductance circuit 210-1 may generate a current signal 1, corresponding to Gm (V.sub.i1V.sub.ref_reg) and output it to the MUX 220, the transconductance circuit 210-2 may generate a current signal I.sub.b corresponding to Gm (V.sub.i2V.sub.ref_reg) and output it to the MUX 220, and the transconductance circuit 210-3 may generate a current signal corresponding to Gm (V.sub.i3V.sub.ref_reg) and output it to the MUX 220.

[0096] Again, in these examples, the MUX 220 may perform multiplexing on the input current signals I.sub.a, I.sub.b, and I.sub.c and may transmit the multiplexed current signals to the ADC 230. The ADC 230 may convert the multiplexed current signals into a digital signal.

[0097] FIG. 7 illustrates an example of an AFE circuit 700 provided in of a neural recording apparatus.

[0098] Referring to FIG. 7, an AFE circuit 700 shown in FIG. 7 may correspond to the example of the AFE circuit 120 of FIG. 1.

[0099] The AFE circuit 700 may include a regulator 701, a plurality of MUXs 720-1 to 720-3, and the plurality of transconductance circuits 210-1 to 210-3. The MUX's illustrated in FIG. 7 may be a 2:1 MUX. For the sake of convenience, the MUX 220 and the ADC 230 illustrated, for example, in the AFE circuit 200 of FIG. 2 are omitted from FIG. 7 although the AFE circuit 700 may still include the MUX 220 and the ADC 230.

[0100] On the other hand, the regulator 701 may include a MUX 710. MUX 710 may be a 2:1 MUX. A first input terminal of the MUX 710 may be connected to a first voltage source to be described later and a second input terminal of the MUX 710 may be connected to the capacitor 610 and the bias resistance 620. An output terminal of the MUX 710 may be connected to an input terminal (e.g., a first terminal) of the operational amplifier 630.

[0101] Referring back to FIG. 1, the neural recording apparatus 100 may operate in a test mode and a measurement mode. The test mode may include performing a calibration (e.g., foreground calibration). The measurement mode may include obtaining or measuring a signal generated from a target.

[0102] The neural recording apparatus 100 may include a first voltage source that generates a first voltage signal V.sub.a when in the test mode while not generating the first voltage signal V a when in the measurement mode. The neural recording apparatus 100 may also include a second voltage source that generates a test voltage signal V.sub.TEST when in the test mode while not generating the test voltage signal V.sub.TEST when in the measurement mode.

[0103] The neural recording apparatus 100 may generate a calibration signal CAL in the test mode. Referring back to FIG. 7, the calibration signal CAL may be provided as a control signal to each of the MUXs 710 and 720-1 to 720-3.

[0104] When the CAL is input to the MUX 710 in the test mode, the MUX 710 may transmit the first voltage signal V.sub.a to the first terminal (-terminal) of the operational amplifier 630.

[0105] In the test mode, the regulator 701 may apply the regulated first voltage signal V.sub.a_reg to the source of the transistor of each of the transconductance circuits 210-1 to 210-3.

[0106] When the CAL is input to each of the MUXs 720-1 to 720-3 in the test mode, each of the MUXs 720-1 to 720-3 may transmit the test voltage signal V.sub.TEST to each of the transconductance circuits 210-1 to 210-3.

[0107] Each of the transconductance circuits 210-1 to 210-3 may transmit, for example, a current signal corresponding to Gm (V.sub.TESTV.sub.a_reg) to the MUX 220. The MUX 220 may perform multiplexing on the input current signals and may transmit the multiplexed current signals to the ADC 230. The ADC 230 may convert the multiplexed current signals into a digital signal.

[0108] In the test mode, the neural recording apparatus 100 may transmit the digital signal to an external terminal through the communication interface. The external terminal may analyze the digital signal. For example, the external terminal may measure for a nonlinearity by processing the digital signal. In another example, the external terminal can perform a post-processing to the digital signal. The external terminal may transmit calibration information for calibrating the nonlinearity to the neural recording apparatus 100. The neural recording apparatus 100 may calibrate the nonlinearity based on the received calibration information.

[0109] When the test mode ends, the neural recording apparatus 100 may operate in the measurement mode. In the measurement mode, the neural recording apparatus 100 may not generate the CAL.

[0110] In the measurement mode, the MUX 710 may transmit the reference signal V.sub.ref to the first terminal of the operational amplifier 630. The regulator 701 may apply the regulated reference signal V.sub.ref_reg to a source of the transistor of each of the plurality of transconductance circuits 210-1 to 210-3.

[0111] Each of the MUXs 720-1 to 720-3 may transmit a voltage signal measured by each of the electrodes to each of the transconductance circuits 210-1 to 210-3.

[0112] Each of the transconductance circuits 210-1 to 210-3 may then transmit a current signal corresponding to Gm (V.sub.iV.sub.ref_reg) to the MUX 220. The MUX 220 may then perform multiplexing on the input current signals and transmit the multiplexed current signals to the ADC 230. The ADC 230 may convert the multiplexed current signals into a digital signal.

[0113] When the nonlinearity is not calibrated in the test mode, a linearity drop by a 2nd harmonic may occur in the neural recording apparatus 100. When the nonlinearity is calibrated in the test mode, the linearity drop by the 2nd harmonic may be prevented from occurring in the neural recording apparatus 100.

[0114] FIGS. 8A and 8B illustrate an example of merging current signals corresponding to the same neuron in an AFE circuit of a neural recording apparatus.

[0115] Referring to FIG. 8A, an example of merging of current signals corresponding to a same neuron is illustrated.

[0116] An electrode 801 and an electrode 803 may contact the same neuron. For example, the neuron may correspond to one of many neurons that are contacted by the electrodes of an electrode array, e.g., the electrode array 110 of FIG. 1. Electrode 801 may generate voltage signal V.sub.sig1 from the neuron while electrode 803 may generate voltage signal V.sub.sig2 from the neuron. In addition, as described above, a regulator such as the regulator 510 from FIG. 5 may be provided to provide a regulated reference signal.

[0117] The difference between the voltage signal V.sub.sig1 detected by the electrode 801 and the regulated reference signal may be converted into a current signal I.sub.sig1. The difference between the voltage signal V.sub.sig2 detected by the electrode 803 and the regulated reference signal may be converted into a current signal I.sub.sig2. The current signals I.sub.sig1 and I.sub.sig2 corresponding to the same neuron may be merged and transmitted to the ADC 230. That is, the current signals I.sub.sig1 and I.sub.sig2 of channels for the same neuron may be merged and transmitted to the ADC 230. The ADC 230 may convert the merged current signals (e.g., I.sub.sig1+I.sub.sig2) into a digital signal. The ADC 230 may reduce noise and improve the SNR by processing the merged current signals (e.g., I.sub.sig1+I.sub.sig2) rather than processing the current signal I.sub.sig1 and the current signal I.sub.sig2 separately.

[0118] In the example shown in FIG. 8B, the AFEs 120, 200, 300, 500, and 700 of FIGS. 1, 2, 3, 5, and 7 may include a control circuit 810 that merges current signals corresponding to the same neuron. The same label may be assigned to channels for the same neuron.

[0119] Referring to FIG. 8B, the control circuit 810 may be configured to know the label assigned to each of the channels. For example, the control circuit 810 may know that a label 1 is assigned to a channel corresponding to the current signal I.sub.1 and a channel corresponding to the current signal I.sub.2 and a label 2 is assigned to a channel corresponding to the current signal I.sub.3 and a channel corresponding to the current signal I.sub.4.

[0120] The control circuit 810 may be configured to control the MUX 220 to merge current signals of channels to which the same label is assigned. For example, when the current signals I.sub.1, I.sub.2, I.sub.3, and I.sub.4 are input to the MUX 220, the control circuit 810 may control the MUX 220 so that the current signal I.sub.1 and the current signal I.sub.2 are simultaneously output from the MUX 220. The current signal I.sub.3 and the current signal I.sub.4 may not be output from the MUX 220. As the current signal I.sub.1 and the current signal I.sub.2 are simultaneously output from the MUX 220, the current signal I.sub.1 and the current signal I.sub.2 may be merged, and the merged current signal I.sub.1 and the merged current signal I.sub.2 may be transmitted to the ADC 230. The control circuit 810 may be configured to control the MUX 220 so that the current signal I.sub.3 and the current signal I.sub.4 are simultaneously output from the MUX 220. As the current signal I.sub.3 and the current signal I.sub.4 are simultaneously output from the MUX 220, the current signal I.sub.3 and the current signal I.sub.4 may be merged, and the merged current signal I.sub.3 and the merged current signal I.sub.4 may be transmitted to the ADC 230.

[0121] In the example illustrated in FIG. 8B, the number of inputs and outputs of the MUX 220 is merely an example, and the number of inputs and outputs of the MUX 220 is not limited to the example illustrated in FIG. 8B.

[0122] FIG. 9 illustrates an example of an AFE circuit 900 of a neural recording apparatus.

[0123] Referring to FIG. 9, an AFE circuit 900 shown in FIG. 9 may correspond to the example of the AFE circuit 120 of FIG. 1.

[0124] The AFE circuit 900 may include a regulator 910, a plurality of MUXs (e.g., 2:1 MUXs) 920-1 to 920-n, a plurality of transconductance circuits 930-1 to 930-n, a plurality of switches 940-1 to 940-n, a control circuit 950, and an ADC 960. According to an implementation, the control circuit 950 may be located outside the AFE circuit 900.

[0125] The neural recording apparatus 100 including the AFE circuit 900 may operate in a test mode and a measurement mode. The test mode and the measurement mode may be comparable to the modes described with reference to FIG. 7.

[0126] Each of the MUXs 920-1 to 920-n may transmit a test voltage signal V.sub.TEST to a corresponding transconductance circuit in the test mode and transmit a voltage signal detected by a corresponding electrode to a corresponding transconductance circuit in the measurement mode.

[0127] The descriptions of the MUXs 720-1 to 720-n of FIG. 7 may be applied to the descriptions of the MUXs 920-1 to 920-n.

[0128] Each of the transconductance circuits 930-1 to 930-n may correspond to the transconductance circuit 400 of FIG. 4. Each of the transconductance circuits 930-1 to 930-n may include a transistor for performing transconductance, a capacitor connected to the transistor, and a bias resistance.

[0129] The regulator 910 may perform regulating the reference signal V.sub.ref and apply the regulated reference signal V.sub.ref_reg as a source voltage of the transistor of each of the transconductance circuits 930-1 to 930-n. The description of the regulator 701 of FIG. 7 may be applied to the description of the regulator 910.

[0130] Each of the transconductance circuits 930-1 to 930-n may perform transconductance on the input voltage signals (e.g., V.sub.i and V.sub.ref_reg) and may generate each of current signals (e.g., I.sub.a_1 to I.sub.a_n). The description of the transconductance circuits 210-1 to 210-3 described above may be applied to the description of the transconductance circuits 930-1 to 930-n.

[0131] The switches 940-1 to 940-n may be located between the transconductance circuits 930-1 to 930-n and the ADC 960.

[0132] The control circuit 950 may be configured to turn on a switch of each of the transconductance circuits that generates current signals corresponding to the same neuron among the switches 940-1 to 940-n so that the current signals corresponding to the same neuron among the current signals (e.g., I.sub.a_1 to I.sub.a_n) are merged and input to the ADC 960. That is, the control circuit 950 may be configured to turn on a switch of each of the channels for the same neuron so that current signals of each of the channels for the same neuron are merged and input to the ADC 960. For example, the current signal I.sub.a_1 shown in FIG. 9 and a current signal I.sub.a_3 not shown in FIG. 9 may correspond to a first neuron. The control circuit 950 may be configured to turn on first switches (e.g., the switch 940-1 of the transconductance circuit 930-1 that generates the current signal I.sub.a_1 and the switch of the transconductance circuit that generates the current signal I.sub.a_3) to merge the current signals I.sub.a_1 and I.sub.a_3 of the channels for the first neuron. The control circuit 950 may be configured to turn off remaining switches except for the first switches. The current signal I.sub.a_2 and the current signal I.sub.a_n illustrated in FIG. 9 may correspond to a second neuron. The control circuit 950 may be configured to turn on second switches (e.g., the switch 940-2 of the transconductance circuit 930-2 that generates the current signal I.sub.a_2 and the switch 940-n of the transconductance circuit 930-n that generates the current signal I.sub.a_n) to merge the current signals I.sub.a_2 and I.sub.a_n of the channels for the second neuron. The control circuit 950 may be configured to turn off the remaining switches except for the second switches. In this way, the control circuit 950 may turn on the switch of each of the channels for the same neuron and turn off the remaining switches, so that the current signals corresponding to the same neuron may be merged and input to the ADC 960.

[0133] The description provided with reference to FIGS. 1 to 8A and 8B may be applied to the description provided with reference to FIG. 9.

[0134] FIG. 10 illustrates an example of a method of operating a neural recording apparatus.

[0135] Referring to FIG. 10, in operation 1010, the neural recording apparatus 100 may detect voltage signals of one or more neurons and a reference signal through the electrode array 110.

[0136] In operation 1020, the neural recording apparatus 100 may regulate the reference signal through the regulator.

[0137] In operation 1030, the neural recording apparatus 100 may generate current signals by performing a transconductance based on the detected voltage signals and the regulated reference signal through the transconductance circuits.

[0138] In operation 1040, the neural recording apparatus 100 may perform multiplexing on the generated current signals through the MUX.

[0139] In operation 1050, the neural recording apparatus 100 may convert the multiplexed current signals into a digital signal through the ADC.

[0140] In an example, the neural recording apparatus 100 may merge current signals corresponding to the same neuron among the generated current signals.

[0141] The description provided with reference to FIGS. 1 to 9 may be applied to the method of operating the neural recording apparatus 100 of FIG. 10.

[0142] The processors, memories, neural recording apparatuses 100, electrode arrays 110, communication circuits 130, AFE circuits 200, MUXs 220, ADCs 230, transconductance circuits 400, regulators 500, and other devices, and other components described herein are implemented as, and by, hardware components. Examples of hardware components that may be used to perform the operations described in this application where appropriate include controllers, sensors, generators, drivers, memories, comparators, arithmetic logic units, adders, subtractors, multipliers, dividers, integrators, and any other electronic components configured to perform the operations described in this application. In other examples, one or more of the hardware components that perform the operations described in this application are implemented by computing hardware, for example, by one or more processors or computers. A processor or computer may be implemented by one or more processing elements, such as an array of logic gates, a controller and an arithmetic logic unit, a digital signal processor, a microcomputer, a programmable logic controller, a field-programmable gate array, a programmable logic array, a microprocessor, or any other device or combination of devices that is configured to respond to and execute instructions in a defined manner to achieve a desired result. In one example, a processor or computer includes, or is connected to, one or more memories storing instructions or software that are executed by the processor or computer. Hardware components implemented by a processor or computer may execute instructions or software, such as an operating system (OS) and one or more software applications that run on the OS, to perform the operations described in this application. The hardware components may also access, manipulate, process, create, and store data in response to execution of the instructions or software. For simplicity, the singular term processor or computer may be used in the description of the examples described in this application, but in other examples multiple processors or computers may be used, or a processor or computer may include multiple processing elements, or multiple types of processing elements, or both. For example, a single hardware component or two or more hardware components may be implemented by a single processor, or two or more processors, or a processor and a controller. One or more hardware components may be implemented by one or more processors, or a processor and a controller, and one or more other hardware components may be implemented by one or more other processors, or another processor and another controller. One or more processors, or a processor and a controller, may implement a single hardware component, or two or more hardware components. A hardware component may have any one or more of different processing configurations, examples of which include a single processor, independent processors, parallel processors, single-instruction single-data (SISD) multiprocessing, single-instruction multiple-data (SIMD) multiprocessing, multiple-instruction single-data (MISD) multiprocessing, and multiple-instruction multiple-data (MIMD) multiprocessing.

[0143] The methods that perform the operations described in this application, and illustrated in FIGS. 1-10, are performed by computing hardware, for example, by one or more processors or computers, implemented as described above executing instructions or software to perform the operations described in this application that are performed by the methods. For example, a single operation or two or more operations may be performed by a single processor, or two or more processors, or a processor and a controller. One or more operations may be performed by one or more processors, or a processor and a controller, and one or more other operations may be performed by one or more other processors, or another processor and another controller, e.g., as respective operations of processor implemented methods. One or more processors, or a processor and a controller, may perform a single operation, or two or more operations.

[0144] Instructions or software to control computing hardware, for example, one or more processors or computers, to implement the hardware components and perform the methods as described above may be written as computer programs, code segments, instructions or any combination thereof, for individually or collectively instructing or configuring the one or more processors or computers to operate as a machine or special-purpose computer to perform the operations that be performed by the hardware components and the methods as described above. In one example, the instructions or software include machine code that is directly executed by the one or more processors or computers, such as machine code produced by a compiler. In another example, the instructions or software include higher-level code that is executed by the one or more processors or computers using an interpreter. The instructions or software may be written using any programming language based on the block diagrams and the flow charts illustrated in the drawings and the corresponding descriptions in the specification, which disclose algorithms for performing the operations that are performed by the hardware components and the methods as described above.

[0145] The instructions or software to control computing hardware, for example, one or more processors or computers, to implement the hardware components and perform the methods as described above, and any associated data, data files, and data structures, may be recorded, stored, or fixed in or on one or more non-transitory computer-readable storage media. Examples of a non-transitory computer-readable storage medium include read-only memory (ROM), random-access programmable read only memory (PROM), EEPROM, RAM, DRAM, SRAM, flash memory, non-volatile memory, CD-ROMs, CD-Rs, CD+Rs, CD-RWs, CD+RWs, DVD-ROMs, DVD-Rs, DVD+Rs, DVD-RWs, DVD+RWs, DVD-RAMs, BD-ROMs, BD-Rs, BD-R LTHs, BD-REs, blue-ray or optical disk storage, hard disk drive (HDD), solid state drive (SSD), flash memory, a card type memory such as multimedia card micro or a card (for example, secure digital (SD) or extreme digital (XD)), magnetic tapes, floppy disks, magneto-optical data storage devices, optical data storage devices, hard disks, solid-state disks, and any other device that is configured to store the instructions or software and any associated data, data files, and data structures in a non-transitory manner and provide the instructions or software and any associated data, data files, and data structures to one or more processors and computers so that the one or more processors and computers can execute the instructions. In one example, the instructions or software and any associated data, data files, and data structures are distributed over network-coupled computer systems so that the instructions and software and any associated data, data files, and data structures are stored, accessed, and executed in a distributed fashion by the one or more processors or computers.

[0146] While this disclosure includes specific examples, it will be apparent after an understanding of the disclosure of this application that various changes in form and details may be made in these examples without departing from the spirit and scope of the claims and their equivalents. The examples described herein are to be considered in a descriptive sense only, and not for purposes of limitation. Descriptions of features or aspects in each example are to be considered as being applicable to similar features or aspects in other examples. Suitable results may be achieved if the described techniques are performed in a different order, and/or if components in a described system, architecture, device, or circuit are combined in a different manner, and/or replaced or supplemented by other components or their equivalents.