Optoelectronic Apparatus and Optoelectronic Integration Method

Abstract

An optoelectronic apparatus (200) and an optoelectronic integration method are disclosed, so that bandwidth for signal transmission can be improved, and signal transmission performance is improved. The optoelectronic apparatus (200) includes: a printed circuit board PCB (201), where a first substrate (203) and a second substrate (205) are separately disposed on the PCB (201), an application specific integrated circuit ASIC (202) is disposed on the first substrate (203), and an optoelectronic component (204) is disposed on the second substrate (205); and a flexible printed circuit FPC (206), where a first end of the FPC (206) is disposed on an upper surface of the first substrate (203) and is electrically connected to the ASIC (202), and a second end of the FPC (206) is disposed on the second substrate (205) and is electrically connected to the optoelectronic component (204).

Claims

1. An optoelectronic apparatus, comprising: a printed circuit board (PCB); a first substrate and a second substrate separately disposed on the PCB; an application specific integrated circuit (ASIC) disposed on the first substrate; an optoelectronic component disposed on the second substrate; and a flexible printed circuit (FPC), wherein a first end of the FPC is disposed on an upper surface of the first substrate and is electrically connected to the ASIC, and a second end of the FPC is disposed on the second substrate and is electrically connected to the optoelectronic component.

2. The optoelectronic apparatus according to claim 1, wherein the optoelectronic apparatus further comprises a third substrate disposed on an upper surface of the second substrate, the second end of the FPC is disposed on an upper surface of the third substrate, the third substrate is configured to electrically connect the FPC to the optoelectronic component, and a difference between a dielectric constant of a material of the third substrate and a dielectric constant of a material of the FPC is less than a preset dielectric constant threshold.

3. The optoelectronic apparatus according to claim 2, wherein the upper surface of the third substrate is electrically connected to the second end of the FPC, a lower surface of the third substrate is electrically connected to the upper surface of the second substrate, and the upper surface of the third substrate is electrically connected to the lower surface of the third substrate using at least one through-hole.

4. The optoelectronic apparatus according to claim 3, wherein the upper surface of the third substrate is soldered to the second end of the FPC.

5. The optoelectronic apparatus according to claim 3, wherein the lower surface of the third substrate and the upper surface of the second substrate are soldered using a first ball grid array (BGA).

6. The optoelectronic apparatus according to claim 1, wherein the optoelectronic apparatus further comprises a first conducting wire, and the first conducting wire is configured to electrically connect the second end of the FPC to the second substrate.

7. The optoelectronic apparatus according to claim 1, wherein the first end of the FPC is soldered to the upper surface of the first substrate.

8. The optoelectronic apparatus according to claim 1, wherein the optoelectronic apparatus further comprises a second conducting wire, and the second conducting wire is configured to electrically connect the first end of the FPC to the first substrate.

9. The optoelectronic apparatus according to claim 1, wherein a material of the FPC is an organic material, and a material of the second substrate is ceramic.

10. An optoelectronic apparatus, comprising: a printed circuit board (PCB); a first substrate and a second substrate separately disposed on the PCB; an application specific integrated circuit (ASIC) disposed on the first substrate; an optoelectronic component disposed on the second substrate; a flexible printed circuit (FPC); and a third substrate disposed on an upper surface of the second substrate, wherein a first end of the FPC is disposed on an upper surface of the PCB and is electrically connected to the ASIC disposed on the first substrate, a second end of the FPC is disposed on an upper surface of the third substrate, the third substrate is configured to electrically connect the FPC to the optoelectronic component, and a difference between a dielectric constant of a material of the third substrate and a dielectric constant of a material of the FPC is less than a preset dielectric constant threshold.

11. The optoelectronic apparatus according to claim 10, wherein the upper surface of the third substrate is electrically connected to the second end of the FPC, a lower surface of the third substrate is electrically connected to the upper surface of the second substrate, and the upper surface of the third substrate is electrically connected to the lower surface of the third substrate using at least one through-hole.

12. The optoelectronic apparatus according to claim 11, wherein the upper surface of the third substrate is soldered to the second end of the FPC.

13. The optoelectronic apparatus according to claim 11, wherein the lower surface of the third substrate and the upper surface of the second substrate are soldered using a first ball grid array (BGA).

14. The optoelectronic apparatus according to claim 11, wherein the material of the FPC is an organic material, and a material of the second substrate is ceramic.

15. An optoelectronic apparatus, comprising: a printed circuit board (PCB); a first substrate and a second substrateseparately disposed on the PCB; an application specific integrated circuit (ASIC) disposed on the first substrate; an optoelectronic component disposed on the second substrate; and a flexible printed circuit (FPC) and a conducting wire, wherein a first end of the FPC is disposed on an upper surface of the PCB and is electrically connected to the ASIC disposed on the first substrate, a first end of the conducting wire is disposed on a second end of the FPC, a second end of the conducting wire is disposed on an upper surface of the second substrate, and the conducting wire is configured to electrically connect the FPC to the optoelectronic component.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0065] FIG. 1 is a schematic diagram of a structure of an optoelectronic apparatus 100 according to a conventional technology;

[0066] FIG. 2 is a schematic diagram of a structure of an optoelectronic apparatus 200 according to an embodiment of this application;

[0067] FIG. 3 is a schematic diagram (top view) of a connection between an ASIC and a first substrate according to an embodiment of this application;

[0068] FIG. 4 is a schematic diagram (side view) of a connection between an ASIC and a first substrate according to an embodiment of this application;

[0069] FIG. 5 is a schematic diagram of a structure of an optoelectronic apparatus 300 according to an embodiment of this application;

[0070] FIG. 6 is a schematic diagram (top view) of a connection between a first substrate and an FPC according to an embodiment of this application;

[0071] FIG. 7 is a schematic diagram (side view) of a connection between a first substrate and an FPC according to an embodiment of this application;

[0072] FIG. 8 is a schematic diagram of a structure of an optoelectronic apparatus 400 according to an embodiment of this application;

[0073] FIG. 9 is a schematic diagram (top view) of another connection between a first substrate and an FPC according to an embodiment of this application;

[0074] FIG. 10 is a schematic diagram (side view) of another connection between a first substrate and an FPC according to an embodiment of this application;

[0075] FIG. 11 is a schematic diagram of a structure of an optoelectronic apparatus 500 according to an embodiment of this application;

[0076] FIG. 12 is another schematic diagram of a structure of an optoelectronic apparatus 500 according to an embodiment of this application;

[0077] FIG. 13 is a schematic diagram of a structure of an optoelectronic apparatus 600 according to an embodiment of this application;

[0078] FIG. 14 is a schematic diagram of a structure of an optoelectronic apparatus 700 according to an embodiment of this application;

[0079] FIG. 15 is a schematic diagram of a structure of an optoelectronic apparatus 800 according to an embodiment of this application; and

[0080] FIG. 16 is a schematic diagram of a structure of an optoelectronic apparatus 900 according to an embodiment of this application.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

[0081] The following describes technical solutions of this application with reference to the accompanying drawings.

[0082] FIG. 1 is a schematic diagram (side view) of a structure of an optoelectronic apparatus 100 according to a conventional technology. As shown in FIG. 1, the optoelectronic apparatus 100 includes a PCB 101, an ASIC 102, a first substrate 103, an optoelectronic component 104, a second substrate 105, and an FPC 106. The first substrate 103 and the second substrate 105 are separately disposed on the PCB 101, the ASIC 102 is disposed on the first substrate 103, and the optoelectronic component 104 is disposed on the second substrate 105. A first end of the FPC 106 is disposed on an upper surface of the second substrate 105 and is electrically connected to the optoelectronic component 104, and a second end of the FPC 106 is disposed on an upper surface of the PCB 101 and is electrically connected to the ASIC 102.

[0083] However, in an existing optoelectronic apparatus 100 with an optoelectronic component, the ASIC 102 is electrically connected to the optoelectronic component 104 by using the PCB 101 and the FPC 106; in other words, a signal of the optoelectronic component 104 needs to use the FPC 106, and is transmitted, by using a circuit cable on the PCB 101, to the ASIC 102 disposed on the PCB 101. When a signal is transmitted between the optoelectronic component 104 and the ASIC 102, a passive link experienced by signal transmission is relatively long, and there are a relatively large quantity of soldering nodes. Consequently, loss of the signal in a transmission process is relatively large, and there are a relatively large quantity of parasitic parameters. Therefore, bandwidth for signal transmission may also be limited.

[0084] In addition, in the existing optoelectronic apparatus 100, a pad of the FPC 106 and a pad of the second substrate 105 are soldered by using solder. Because the FPC 106 is usually made of an organic material, and the second substrate 105 is usually made of a ceramic material, dielectric constants of the two materials vary greatly. When the FPC 106 is connected to the optoelectronic component, a packaging mode mismatch usually occurs. Therefore, bandwidth for signal transmission may also be limited.

[0085] In conclusion, in the existing optoelectronic apparatus 100, bandwidth for signal transmission is relatively low, and therefore signal transmission performance is relatively poor.

[0086] For a problem existing in the foregoing existing optoelectronic apparatus 100, FIG. 2 is a schematic diagram (side view) of a structure of an optoelectronic apparatus 200 according to an embodiment of this application.

[0087] As shown in FIG. 2, the optoelectronic apparatus 200 includes a PCB 201, an ASIC 202, a first substrate 203, an optoelectronic component 204, a second substrate 205, and an FPC 206. The first substrate 203 and the second substrate 205 are separately disposed on the PCB 201. The ASIC 202 is disposed on the first substrate 203. The optoelectronic component 204 is disposed on the second substrate 205. A first end of the FPC 206 is disposed on an upper surface of the first substrate 203 and is electrically connected to the ASIC 202, and a second end of the FPC 206 is disposed on an upper surface of the second substrate 205 and is electrically connected to the optoelectronic component 204.

[0088] Based on the optoelectronic apparatus 200 provided in this embodiment of this application, the ASIC 202 and the optoelectronic component 204 may be electrically connected directly by using a circuit cable on the FPC 206. In other words, a signal of the optoelectronic component 204 may be directly transmitted, by using the circuit cable on the FPC 206, to the ASIC 202 disposed on the PCB 201 without using the PCB 201, so that a length of a passive link experienced by signal transmission and a quantity of soldering nodes can be reduced. In this way, parasitic parameters of the signal in a transmission process can be reduced, and loss of the signal can be reduced. Therefore, bandwidth for signal transmission can be improved, and signal transmission performance is improved.

[0089] It should be noted that the PCB is a printed circuit board, and is also referred to as a rigid circuit board. The PCB is a support of an electronic component or a carrier that is electrically connected to the electronic component.

[0090] It should be further noted that the FPC is a flexible printed circuit. The FPC is a highly reliable flexible printed circuit made of a flexible insulating substrate such as polyimide or a polyester film, and is characterized by high wiring density, light weight, small thickness, and good bendability. The FPC is mainly used in an electronic product. As all lines are configured on the FPC, connections of extra line cables can be eliminated, and softness can be improved. In addition, the FPC can absorb an assembly tolerance and strengthen three-dimensional space assembly in limited space to reduce a product volume.

[0091] Optionally, there may be a plurality of types of optoelectronic components 204. This is not limited in this embodiment of this application.

[0092] In a possible implementation, the optoelectronic component 204 may be an optoelectronic chip, and the optoelectronic chip is a core component of optical communication. For example, the optoelectronic chip may be a module that has an optoelectronic signal conversion function. In addition, the optoelectronic chip may further have a function such as modulation. For details, refer to a conventional technology. This is not specifically limited in this embodiment of this application.

[0093] In a possible implementation, that the ASIC 202 is disposed on the first substrate 203 may be understood as that the ASIC 202 is packaged or mounted on the first substrate 203.

[0094] Optionally, the ASIC 202 may be mounted on the first substrate 203 in a plurality of manners. This is not limited in this embodiment of this application.

[0095] In a possible implementation, as shown in FIG. 2, the ASIC 202 and the first substrate 203 may be soldered by using a first ball grid array (BGA) 207.

[0096] For example, FIG. 3 (a top view) and FIG. 4 (a side view) are schematic diagrams of a connection between the ASIC 202 and the first substrate 203. As shown in FIG. 3 and FIG. 4, a first pad 208 is disposed on a lower surface of the ASIC 202, a second pad 209 is disposed on an upper surface of the first substrate 203, and the first pad 208 and the second pad 209 are soldered by using the first BGA 207.

[0097] In a possible implementation, that the optoelectronic component 204 is disposed on the second substrate 205 may be understood as that the optoelectronic component 204 is packaged or mounted on the second substrate 205.

[0098] It should be noted that for a manner of mounting the optoelectronic component 204 on the second substrate 205, refer to a manner of mounting the ASIC 202 on the first substrate 203 described in FIG. 3 and FIG. 4. To avoid repetition, details are not described herein again.

[0099] Optionally, the second substrate 205 may alternatively be a package base or a base. In this embodiment of this application, only the substrate is used as an example for description. However, this embodiment of this application is not limited thereto.

[0100] Optionally, the first end of the FPC may be electrically connected to the first substrate in a plurality of manners. This is not limited in this embodiment of this application.

[0101] A possible manner of electrically connecting the first end of the FPC and the first substrate is described below with reference to FIG. 5 to FIG. 7. It should be noted that for a part that is not described in detail in FIG. 5, refer to descriptions of a corresponding part in FIG. 2. To avoid repetition, details are not described herein again.

[0102] FIG. 5 is a schematic diagram (side view) of a structure of an optoelectronic apparatus 300 according to an embodiment of this application. As shown in FIG. 5, a first end of an FPC 306 and a first substrate 303 are soldered.

[0103] For example, FIG. 6 (a top view) and FIG. 7 (a side view) are schematic diagrams of a connection between a first end of the FPC 306 and the first substrate 303. As shown in FIG. 6 and FIG. 7, a third pad 308 is disposed on an upper surface of the first substrate 303, a fourth pad 309 is disposed on a lower surface of the first end of the FPC 306, and the third pad 308 and the fourth pad 309 are soldered.

[0104] Optionally, the first end of the FPC 306 and the first substrate 303 may be soldered by using a tin-based solder by using an existing PCB or FPC soldering process, for example, a soldering process such as hot bar soldering or laser. This is not limited in this embodiment of this application.

[0105] Another possible manner of electrically connecting the first end of the FPC and the first substrate is described below with reference to FIG. 8 to FIG. 10. It should be noted that for a part that is not described in detail in FIG. 8, refer to descriptions of a corresponding part in FIG. 2. To avoid repetition, details are not described herein again.

[0106] FIG. 8 is a schematic diagram (side view) of a structure of an optoelectronic apparatus 400 according to an embodiment of this application. As shown in FIG. 8, the optoelectronic apparatus 400 further includes a first bonding wire 407, and a first end of an FPC 406 and a first substrate 403 are soldered by using the first bonding wire 407.

[0107] For example, FIG. 9 (a top view) and FIG. 10 (a side view) are schematic diagrams of a connection between a first end of the FPC 406 and the first substrate 403. As shown in FIG. 9 and FIG. 10, a fifth pad 408 is disposed on an upper surface of the first substrate 403, a sixth pad 409 is disposed on an upper surface of the first end of the FPC 406, and the fifth pad 408 and the sixth pad 409 are electrically connected by using the first bonding wire 407.

[0108] Optionally, a second end of the FPC may be electrically connected to the second substrate in a plurality of manners. This is not limited in this embodiment of this application.

[0109] A possible manner of electrically connecting the second end of the FPC and the second substrate is described below with reference to FIG. 11 to FIG. 12. It should be noted that for a part that is not described in detail in FIG. 11 and FIG. 12, refer to descriptions of a corresponding part in FIG. 2, FIG. 5, and/or FIG. 8. To avoid repetition, details are not described herein again.

[0110] FIG. 11 is a schematic diagram (side view) of a structure of an optoelectronic apparatus 500 according to an embodiment of this application. As shown in FIG. 11, the optoelectronic apparatus 500 includes a third substrate 507, a second end of an FPC 506 is disposed on an upper surface of the third substrate 507, a second substrate 505 is disposed on a lower surface of the third substrate 507, the third substrate 507 is configured to electrically connect the FPC 506 to an optoelectronic component 504, and a difference between a dielectric constant of a material of the third substrate 507 and a dielectric constant of a material of the FPC 506 is less than a preset dielectric constant threshold.

[0111] In other words, the material of the third substrate 507 is close to or the same as the material of the FPC 506.

[0112] For example, as shown in FIG. 12, the upper surface of the third substrate 507 is soldered to a lower surface of the second end of the FPC 506, the lower surface of the third substrate 507 is soldered to the upper surface of the second substrate 505 by using a second BGA 508, and the upper surface of the third substrate 507 is electrically connected to the lower surface of the third substrate 507 by using at least one through-hole 509.

[0113] It should be noted that the through-hole is also referred to as a plated hole. In a double-sided substrate and a multi-layer substrate, to connect printed wires between layers, a common hole, that is, a through-hole, is drilled at an intersection of wires that need to be connected to the layers.

[0114] It should be further noted that for a manner of connecting the upper surface of the third substrate 507 to the lower surface of the second end of the FPC 506, refer to a manner of connecting the lower surface of the first end of the FPC 306 to the upper surface of the first substrate 303 in FIG. 6 and FIG. 7. For a manner of connecting the lower surface of the third substrate 507 to the upper surface of the second substrate 505 by using the second BGA 508, refer to the manner of connecting the ASIC 202 to the first substrate 203 by using the first BGA 207 in FIG. 3 and FIG. 4. To avoid repetition, details are not described herein again.

[0115] It should be noted that in a conventional technology, because packaging of the FPC and the ceramic second substrate belongs to a PCB/FPC packaging process, the dielectric constant of the material of the FPC and a material of the ceramic second substrate differ to a relatively large extent. A packaging mode mismatch usually occurs when the FPC is connected to the optoelectronic component. Therefore, bandwidth for signal transmission is limited.

[0116] In this embodiment of this application, the material of the FPC 506 is close to or the same as the material of the third substrate 507, so that a problem of limited bandwidth for signal transmission caused by a material difference between the FPC 506 and the third substrate 507 can be avoided. In addition, because packaging of the third substrate 507 and the second substrate 505 is inter-substrate packaging, a packaging process with higher precision such as solder ball flip chip or copper pillar flip chip may be used, to absorb an assembly tolerance between different materials, so that a problem of limited bandwidth for signal transmission caused by a material difference between the third substrate 507 and the second substrate 505 can be avoided. Therefore, the third substrate 507 is electrically connected to the FPC 506 and the second substrate 505, so that bandwidth for signal transmission can be improved.

[0117] Another possible manner of electrically connecting the second end of the FPC and the second substrate is described below with reference to FIG. 13. It should be noted that for a part that is not described in detail in FIG. 13, refer to descriptions of a corresponding part in FIG. 2, FIG. 5, and/or FIG. 8. To avoid repetition, details are not described herein again.

[0118] FIG. 13 is a schematic diagram (side view) of a structure of an optoelectronic apparatus 600 according to an embodiment of this application. As shown in FIG. 13, the optoelectronic apparatus 600 includes a second bonding wire 607, and a second end of an FPC 606 and a second substrate 605 are soldered by using the second bonding wire 607.

[0119] It should be noted that for a manner of connecting the second end of the FPC 606 to the second substrate 605 by using the second bonding wire 607, refer to a manner of connecting the first end of the FPC 406 to the first substrate 403 by using the first bonding wire 407 in FIG. 9 and FIG. 10. To avoid repetition, details are not described herein again.

[0120] Based on the optoelectronic apparatus 600 provided in this application, the FPC 606 is connected to the second substrate 605 by using the second bonding wire 607; in other words, a soldering process does not need to be used for connection, so that a problem of limited bandwidth for signal transmission caused by a material difference between the FPC 606 and the second substrate 605 in a conventional technology can be avoided.

[0121] It should be noted that the foregoing provided various connection manners between the first end of the FPC and the first substrate and the connection manners between the second end of the FPC and the second substrate may be randomly combined. This is not limited in this embodiment of this application.

[0122] For example, FIG. 14 is a schematic diagram (side view) of a structure of an optoelectronic apparatus 700 according to an embodiment of this application. As shown in FIG. 14, the optoelectronic apparatus 700 further includes a third bonding wire 707 and a fourth bonding wire 708, a first end of an FPC 706 is connected to a first substrate 703 by using the third bonding wire 707, and a second end of the FPC 706 is connected to a second substrate 705 by using the fourth bonding wire 708.

[0123] It should be noted that, for a manner of connecting the first end of the FPC 706 to the first substrate 703 by using the third bonding wire 707 and a manner of connecting the second end of the FPC 706 to the second substrate 705 by using the fourth bonding wire 708, refer to a manner of connecting the first end of the FPC 406 to the first substrate 403 by using the first bonding wire 407 in FIG. 9 and FIG. 10. To avoid repetition, details are not described herein again.

[0124] It should be further noted that for a part that is not described in detail in FIG. 14, refer to descriptions of a corresponding part in FIG. 2. To avoid repetition, details are not described herein again.

[0125] FIG. 15 is a schematic diagram (side view) of a structure of an optoelectronic apparatus 800 according to an embodiment of this application. As shown in FIG. 15, the optoelectronic apparatus 800 includes a PCB 801, an ASIC 802, a first substrate 803, an optoelectronic component 804, a second substrate 805, an FPC 806, and a third substrate 807. The first substrate 803 and the second substrate 805 are separately disposed on the PCB 801. The ASIC 802 is disposed on the first substrate 803. A first end of the FPC 806 is disposed on an upper surface of the PCB 801 and is electrically connected to the ASIC 802 disposed on the first substrate 803, and a second end of the FPC 806 is disposed on an upper surface of the third substrate 807. The second substrate 805 is disposed on a lower surface of the third substrate 807. The third substrate 807 is configured to electrically connect the FPC 806 to the optoelectronic component 804. A difference between a dielectric constant of a material of the third substrate 807 and a dielectric constant of a material of the FPC 806 is less than a preset dielectric constant threshold.

[0126] In other words, the optoelectronic component 804 is connected to the FPC 806 by using an interposer of the third substrate 807, and is electrically connected to the ASIC 802 by using a circuit cable on the PCB 801 by using the FPC 806, and the material of the third substrate 807 is close to or the same as the material of the FPC 806. In this way, a problem of limited bandwidth for signal transmission caused by a material difference between the FPC 806 and the second substrate 805 can be avoided.

[0127] It should be noted that for each part in the optoelectronic apparatus 800 and a connection manner of the parts, refer to the foregoing corresponding descriptions. To avoid repetition, details are not described herein again.

[0128] Optionally, FIG. 16 is a schematic diagram (side view) of a structure of an optoelectronic apparatus 900 according to an embodiment of this application. As shown in FIG. 16, the optoelectronic apparatus 900 includes a PCB 901, an ASIC 902, a first substrate 903, an optoelectronic component 904, a second substrate 905, an FPC 906, and a fifth bonding wire 907. The first substrate 903 and the second substrate 905 are separately disposed on the PCB 901. The ASIC 902 is disposed on the first substrate 903. A first end of the FPC 906 is disposed on an upper surface of the PCB 901 and is electrically connected to the ASIC 902 disposed on the first substrate 903. A first end of the fifth bonding wire 907 is disposed on a second end of the FPC 906, a second end of the fifth bonding wire 907 is disposed on an upper surface of the second substrate 905, and the fifth bonding wire 907 is configured to electrically connect the FPC 906 to the optoelectronic component 904.

[0129] In other words, the optoelectronic component 904 is connected to the FPC 906 by using the fifth bonding wire 907, and is electrically connected to the ASIC 902 by using a circuit cable on the PCB 901 by using the FPC 906. In this way, a problem of limited bandwidth for signal transmission caused by a material difference between the FPC 906 and the second substrate 905 can be avoided.

[0130] The optoelectronic apparatus provided in embodiments of this application is described above with reference to FIG. 2 to FIG. 16. An optoelectronic integration method provided in embodiments of this application is described below with reference to the following steps 1 to 4.

[0131] Step 1: Mount an ASIC on a first substrate.

[0132] Step 2: Mount an optoelectronic component on a second substrate.

[0133] Step 3: Mount the first substrate and the second substrate on a PCB.

[0134] Step 4: Dispose a first end of an FPC on the first substrate and electrically connect the first end of the FPC to the ASIC on the first substrate.

[0135] Step 5: Dispose a second end of the FPC on the second substrate and electrically connect the second end of the FPC to the optoelectronic component on the second substrate.

[0136] It should be noted that for an implementation process of step 4 and step 5, refer to descriptions of a corresponding part in the foregoing apparatus embodiments.

[0137] The foregoing descriptions are merely specific implementations of this application, but are not intended to limit the protection scope of this application. Any variation or replacement readily figured out by a person skilled in the art within the technical scope disclosed in this application shall fall within the protection scope of this application. Therefore, the protection scope of this application shall be subject to the protection scope of the claims.