SEMICONDUCTOR MEMORY DEVICE

Abstract

A memory cell includes a substrate, a floating gate on the substrate, a control gate on the floating gate, a first dielectric layer between the floating gate and the control gate, an erase gate merged with the control gate and disposed on a first sidewall of the floating gate, a second dielectric layer between the floating gate and the erase gate, a select gate on an opposite second sidewall of the floating gate, a spacer between the select gate and the control gate and between the select gate and the floating gate, a source doping region in the substrate and adjacent to the first sidewall of the floating gate, and a drain doping region in the substrate and adjacent to the select gate.

Claims

1. A semiconductor memory device, comprising: a substrate; a plurality of device lines comprising a select gate (SG) line, a control gate (CG) line, an erase gate (EG) line, and a source line elongated in parallel along a first direction, wherein the CG line is disposed between the EG line and the SG line, the EG line is merged with the CG line, and the source line underlies the EG line in the substrate, wherein the plurality of device lines defines a plurality of memory cells; a plurality of drain doping regions of the plurality of memory cells disposed in the substrate and adjacent to the SG line; a plurality of bit line contacts disposed on the plurality of drain doping regions of the plurality of memory cells, respectively; a plurality of source doping regions of the plurality of memory cells electrically coupled to the source line in the substrate and disposed under the EG line; and a plurality of source line contacts disposed on the plurality of source doping regions of the plurality of memory cells, respectively, wherein the plurality of source line contacts is aligned with the plurality of bit line contacts in a second direction that is orthogonal to the first direction.

2. The semiconductor memory device according to claim 1, wherein each of the plurality of memory cells comprises a floating gate disposed under the CG line.

3. The semiconductor memory device according to claim 1, wherein the EG line partially overlaps with the source line when viewed from above.

4. The semiconductor memory device according to claim 2, wherein each of the plurality of source doping regions is disposed adjacent to a first sidewall of the floating gate.

5. The semiconductor memory device according to claim 4 further comprising: a first dielectric layer disposed between the floating gate and the CG line.

6. The semiconductor memory device according to claim 5, wherein the first dielectric layer comprises an oxide-nitride-oxide (ONO) dielectric layer.

7. The semiconductor memory device according to claim 5 further comprising: a second dielectric layer disposed between the floating gate and the EG line.

8. The semiconductor memory device according to claim 7, wherein the second dielectric layer is a silicon oxide layer.

9. The semiconductor memory device according to claim 7, wherein the second dielectric layer is disposed only on the first sidewall of the floating gate.

10. The semiconductor memory device according to claim 7, wherein the first dielectric layer is thicker than the second dielectric layer.

11. A memory cell, comprising: a substrate; a floating gate disposed on the substrate; a control gate disposed on the floating gate; a first dielectric layer disposed between the floating gate and the control gate; an erase gate merged with the control gate and disposed on a first sidewall of the floating gate; a second dielectric layer disposed between the floating gate and the erase gate; a select gate disposed on an opposite second sidewall of the floating gate; a spacer disposed between the select gate and the control gate and between the select gate and the floating gate; a source doping region disposed in the substrate and adjacent to the first sidewall of the floating gate; and a drain doping region disposed in the substrate and adjacent to the select gate.

12. The memory cell according to claim 11, wherein the first dielectric layer is thicker than the second dielectric layer.

13. The memory cell according to claim 12, wherein the first dielectric layer comprises an oxide-nitride-oxide (ONO) dielectric layer.

14. The memory cell according to claim 13, wherein the second dielectric layer is a silicon oxide layer.

15. The memory cell according to claim 11, wherein the erase gate partially overlaps with the source doping region.

16. The memory cell according to claim 11 further comprising: a source line contact disposed on the source doping region; and a bit line contact disposed on the drain doping region.

17. The memory cell according to claim 16 further comprising: an insulating layer between the substrate and the erase gate, wherein the insulating layer has a thickness that increases from the first sidewall of the floating gate to the source line contact.

18. The memory cell according to claim 11, wherein the erase gate is structurally integrated with the control gate.

19. The memory cell according to claim 11, wherein the erase gate, the control gate, the floating gate, and the select gate are composed of polysilicon.

20. The memory cell according to claim 11 further comprising: a select gate oxide layer disposed between the select gate and the substrate; and a floating gate oxide layer disposed between the floating gate and the substrate.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0027] FIG. 1 is a schematic diagram showing a partial layout of a semiconductor memory device according to an embodiment of the present invention.

[0028] FIG. 2 is a schematic cross-sectional view taken along the line I-I′ in FIG. 1.

[0029] FIG. 3 to FIG. 12 are schematic diagrams illustrating a method for fabricating a semiconductor memory device according to an embodiment of the present invention.

DETAILED DESCRIPTION

[0030] In the following detailed description of the disclosure, reference is made to the accompanying drawings, which form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention.

[0031] Other embodiments may be utilized, and structural, logical, and electrical changes may be made without departing from the scope of the present invention. Therefore, the following detailed description is not to be considered as limiting, but the embodiments included herein are defined by the scope of the accompanying claims.

[0032] Please refer to FIG. 1 and FIG.2. FIG. 1 is a partial layout diagram of a semiconductor memory device 1 according to an embodiment of the present invention. FIG. 2 is a cross-sectional view taken along line I-I′ in FIG. 1. As shown in FIG. 1 and FIG. 2, the semiconductor memory device 1 includes a substrate 100, for example, a P-type doped silicon substrate, but not limited thereto. Multiple device lines DL are provided on the substrate 100, including a select gate line SGL, a control gate line CGL, an erase gate line EGL, and a source line SL extending in parallel along the first direction D1.

[0033] According to an embodiment of the present invention, the control gate line CGL is disposed between the erase gate line EGL and the select gate line SGL, and the source line SL is located in the substrate 100 below the erase gate line EGL.

[0034] According to an embodiment of the present invention, the erase gate line EGL and the control gate line CGL are merged together and are structurally integrated.

[0035] It can be seen from FIG. 1 that multiple elongated active areas AA extending along the second direction D2 are provided in the substrate 100. According to an embodiment of the present invention, the source lines SL extending along the first direction D1 and the elongated active regions AA extending along the second direction D2 intersect. According to an embodiment of the present invention, the source line SL may be a heavily doped region, for example, an N.sup.+ heavily doped region, formed in the substrate 100.

[0036] According to an embodiment of the present invention, the device lines DL define a plurality of memory cells MC (formed on each elongated active area AA) spaced apart from each other along their lengths (or the first direction D1).

[0037] According to an embodiment of the present invention, multiple bit line contacts BLC are arranged along the first direction D1, and are respectively electrically connected to the drain doped regions DD of the memory cells MC. The drain doped regions DD are arranged in the substrate and adjacent to the select gate line SGL. According to an embodiment of the present invention, the semiconductor memory device 1 further includes multiple source line contacts SLC, which are respectively disposed on the source doped regions SS of the memory cells MC. The source line contacts SLC are aligned with the bit line contacts BLC, respectively along the second direction D2 that is orthogonal to the first direction D1.

[0038] According to an embodiment of the present invention, the source doped regions SS of the memory cells MC are electrically connected to the source lines SL in the substrate 100 and disposed under the erase gate lines EGL. According to an embodiment of the present invention, as shown in FIG. 1, when viewed from above, the erase gate line EGL partially overlaps with the source line SL.

[0039] According to an embodiment of the present invention, as shown in FIG. 1 and FIG. 2, each memory cell MC further includes a floating gate FG disposed under the control gate line CGL. According to an embodiment of the present invention, the erase gate line EGL, the control gate line CGL, the floating gate FG and the select gate line SGL are all formed of polysilicon. It can be seen from FIG. 2 that the two memory cells MC are mirror-symmetrical structures with respect to the middle source line SL. According to an embodiment of the present invention, each source doped region SS is disposed adjacent to the first sidewall SW1 of the floating gate FG.

[0040] According to an embodiment of the present invention, the semiconductor memory device 1 further includes a first dielectric layer DL1 disposed between the floating gate FG and the control gate line CGL. According to an embodiment of the present invention, for example, the first dielectric layer DL1 includes an oxide-nitride-oxide (ONO) dielectric layer, but is not limited thereto. According to an embodiment of the present invention, the semiconductor memory device 1 further includes a second dielectric layer DL2 disposed between the floating gate FG and the erase gate line EGL.

[0041] According to an embodiment of the present invention, for example, the second dielectric layer DL2 is a silicon oxide layer, but not limited thereto. According to an embodiment of the present invention, the second dielectric layer DL2 is only disposed on the first sidewall SW1 of the floating gate FG. According to an embodiment of the present invention, the first dielectric layer DL1 is thicker than the second dielectric layer DL2.

[0042] According to an embodiment of the present invention, as shown in FIG. 2, the select gate line SGL is disposed on the opposite second sidewall SW2 of the floating gate FG. Spacers SP, for example, silicon nitride spacers, may be provided between the select gate line SGL and the control gate line CGL and between the select gate line SGL and the floating gate FG.

[0043] According to an embodiment of the present invention, the semiconductor memory device 1 further includes an insulating layer IN disposed between the substrate 100 and the erase gate line EGL. The insulating layer IN has a thickness that increases in a direction from the first sidewall SW1 of the floating gate FG to the source line contact SLC. According to an embodiment of the present invention, the select gate line SGL, the control gate line CGL and the erase gate line EGL are surrounded by a dielectric layer IL, and the source line contact SLC and the bit line contact BLC are disposed in the dielectric layer IL.

[0044] FIG. 3 to FIG. 12 are schematic diagrams illustrating a method for fabricating a semiconductor memory device according to an embodiment of the present invention. As shown in FIG. 3, first, a substrate 100 is provided, for example, a P-type doped silicon substrate, but not limited thereto. A trench isolation structure 110 is formed in the substrate 100, which defines the active area AA. After the formation of the trench isolation structure 110, a silicon nitride pad layer (not shown) may be removed to expose the underlying silicon oxide pad layer 102. At this point, the trench isolation structure 110 may protrude from the top surface of the silicon oxide pad layer 102.

[0045] As shown in FIG. 4, a polysilicon layer 120 is then deposited on the substrate 100 in a blanket manner. The polysilicon layer 120 is then etched back. A first dielectric layer DL1, for example, an oxide-nitride-oxide thing (ONO) dielectric layer, is then formed on the polysilicon layer 120.

[0046] As shown in FIG. 5 , using the hard mask pattern HM as an etch hard mask, an etching process is performed to pattern the first dielectric layer DL1, the polysilicon layer 120 and the silicon oxide pad layer 102, thereby forming a floating gate FG and a floating gate oxide layer FGD.

[0047] As shown in FIG. 6, subsequently, spacers SP, such as, but not limited to, silicon nitride spacers, are formed on the sidewalls of the floating gate FG and the hard mask pattern HM. At the same time, a select gate oxide layer SGD is formed on the surface of the substrate 100 adjacent to the floating gate FG.

[0048] As shown in FIG. 7, a photoresist pattern PR1 is formed on the substrate 100. The photoresist pattern PR1 has an opening OP1 exposing a region between the two floating gates FG. An etching process is then performed to remove the spacers SP between the two floating gates FG through the opening OP1. An ion implantation process 300 is then performed, and dopants, for example, N-type dopants, are implanted into the substrate 100 through the opening OP1 to form a source doped region SS and a source line SL. Subsequently, the photoresist pattern PR1 is removed.

[0049] As shown in FIG. 8, a rapid thermal oxidation (RTO) process and a high-temperature oxidation (HTO) process are sequentially performed, and an insulating layer IN, for example, a silicon oxide layer, is formed on the substrate 100 between the two floating gates FG, and a second dielectric layer DL2, for example, a silicon oxide layer, is formed on the first sidewall SW1 of the floating gate FG.

[0050] According to an embodiment of the present invention, the thickness of the insulating layer IN is thinner near the first sidewall SW1 of the floating gate FG, and the thickness gradually increases toward the middle region between the two floating gates FG.

[0051] According to an embodiment of the present invention, the second dielectric layer DL2 is only disposed on the first sidewall SW1 of the floating gate FG. According to an embodiment of the present invention, the first dielectric layer DL1 is thicker than the second dielectric layer DL2.

[0052] As shown in FIG. 9, a dry etching process is then performed to remove the hard mask pattern HM, thereby exposing the first dielectric layer DL1.

[0053] As shown in FIG. 10, subsequently, a polysilicon layer 220 is deposited on the substrate 100 in a blanket manner. The polysilicon layer 220 covers the spacers SP, the first dielectric layer DL1, the second dielectric layer DL2, and the insulating layer IN.

[0054] As shown in FIG. 11, subsequently, a chemical mechanical polishing (CMP) process is performed to planarize the polysilicon layer 220 until the top surfaces of the spacers SP are exposed.

[0055] As shown in FIG. 12, subsequently, a lithography process and an etching process are performed to pattern the polysilicon layer 220, and the select gate SG and the merged control gate CG and the erase gate EG are defined. Subsequently, a drain doped region DD adjacent to the select gate SG is formed. A dielectric layer IL surrounding the select gate SG and the erase gate EG is then formed. Finally, source line contact SLC and bit line contacts BLC are formed by using a lithography process, an etching process and a metallization process.

[0056] As shown in FIG. 12, the memory cell MC of the present invention includes a substrate 100; a floating gate FG on the substrate 100; a control gate CG on the floating gate FG; a first dielectric layer DL1 between the floating gate FG and the control gate CG; an erase gate EG merged with the control gate CG and disposed on the first sidewall SW1 of the floating gate FG; a second dielectric layer DL2 between the floating gate FG and the erase gate EG; a select gate SG on the opposite second sidewall SW2 of the floating gate FG; a spacer SP between the select gate SG and the control gate CG and between the select gate SG and the floating gate FG; a source doped region SS in the substrate 100 and adjacent to the first sidewall SW1 of the floating gate FG; and a drain doped region DD in the substrate 100 and adjacent to the select gate SG.

[0057] According to an embodiment of the present invention, the first dielectric layer DL1 is thicker than the second dielectric layer DL2.

[0058] According to an embodiment of the present invention, the first dielectric layer DL1 includes an oxide-nitride-oxide (ONO) dielectric layer.

[0059] According to an embodiment of the present invention, the second dielectric layer DL2 is a silicon oxide layer.

[0060] According to an embodiment of the present invention, the erase gate EG partially overlaps with the source doped region SS.

[0061] According to an embodiment of the present invention, the memory cell MC further includes a source line contact SLC disposed on the source doped region SS; and a bit line contact BLC disposed on the drain doped region DD.

[0062] According to an embodiment of the present invention, the memory cell MC further includes an insulating layer IN, which is disposed between the substrate 100 and the erase gate EG, wherein the insulating layer IN has a thickness that increases in a direction from the first sidewall SW1 of the floating gate FG to the source line contact SLC.

[0063] According to an embodiment of the present invention, the erase gate EG and the control gate CG are structurally integrated.

[0064] According to an embodiment of the present invention, the erase gate EG, the control gate CG, the floating gate FG and the select gate SG are formed of polysilicon.

[0065] According to an embodiment of the present invention, the memory cell MC further includes a select gate oxide layer SGD disposed between the select gate SG and the substrate 100; and a floating gate oxide layer FGD disposed between the floating gate FG and the substrate 100.

[0066] Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.