SWITCHED CAPACITOR CIRCUIT

Abstract

A switched capacitor circuit, including a metal-oxide-semiconductor field-effect transistor-based switch comprising: a first metal-oxide-semiconductor field-effect transistor having a gate, a source and a drain, wherein the source is connected to a first node and the drain is connected to a second node or wherein the drain is connected to the first node and the source is connected to the second node; a second metal-oxide-semiconductor field-effect transistor having a gate, a source and a drain, wherein the source is connected to the drain and the source and the drain are together connected to the second node; a first capacitor connected between the first node and a third node; and a second capacitor connected between the second node and the third node.

Claims

1. A switched capacitor circuit, comprising a metal-oxide-semiconductor field-effect transistor-based switch comprising: a first metal-oxide-semiconductor field-effect transistor having a gate, a source and a drain, wherein the source is connected to a first node and the drain is connected to a second node or wherein the drain is connected to the first node and the source is connected to the second node; a second metal-oxide-semiconductor field-effect transistor having a gate, a source and a drain, wherein the source is connected to the drain and the source and the drain are together connected to the second node; a first capacitor connected between the first node and a third node; and a second capacitor connected between the second node and the third node.

2. The switched capacitor circuit according to claim 1, designed such that the gate of said first metal-oxide-semiconductor field-effect transistor receives a first gate signal and the gate of said second metal-oxide-semiconductor field-effect transistor receives a second gate signal, wherein the first gate signal and the second gate signal are formed such that the second metal-oxide-semiconductor field-effect transistor switches on after the first metal-oxide-semiconductor field-effect transistor is switched off.

3. The switched capacitor circuit according to claim 1, designed such that the gate of said first metal-oxide-semiconductor field-effect transistor receives a first gate signal and the gate of said second metal-oxide-semiconductor field-effect transistor receives a second gate signal, which is the inverted first gate signal.

4. The switched capacitor circuit according to claim 2, designed such that there is a delay between a falling edge of the first gate signal and a rising edge of the second gate signal and/or between a rising edge of the first gate signal and a falling edge of the second gate signal.

5. The switched capacitor circuit according to claim 1, wherein the first metal-oxide-semiconductor field-effect transistor and the second metal-oxide-semiconductor field-effect transistor are of a same type.

6. The switched capacitor circuit according to claim 1, wherein the second metal-oxide-semiconductor field-effect transistor has a channel length, which is between 90% and 110% of a channel length of the first metal-oxide-semiconductor field-effect transistor or which is substantially equal to a channel length of the first metal-oxide-semiconductor field-effect transistor.

7. The switched capacitor circuit according to claim 1, wherein the second metal-oxide-semiconductor field-effect transistor has a channel width, which is between 40% and 60% of a channel width of the first metal-oxide-semiconductor field-effect transistor or which is substantially equal to half of a channel width of the first metal-oxide-semiconductor field-effect transistor.

8. The switched capacitor circuit according to claim 1, wherein a first capacitance of said first capacitor and a second capacitance of said second capacitor are in the same order of magnitude or substantially equal.

9. The switched capacitor circuit according to claim 1, wherein said first capacitor and/or said second capacitor has a capacitance or have capacitances of at least 10 fF, 32 fF, 100 fF or 320 fF.

10. The switched capacitor circuit according to claim 1, wherein said first capacitor and/or said second capacitor has a capacitance or have capacitances of at least 5 times of a first parasitic capacitance of the first node, of a second parasitic capacitance of the second node and/or of a third parasitic capacitance of the third node.

11. The switched capacitor circuit according to claim 1, configured such that the second node or the third node is maintained at a virtual ground.

12. The switched capacitor circuit according to claim 1, configured as a sample-and-hold circuit, comprising an input buffer connected to the first node and a virtual ground buffer connected to the third node whereby the second node is configured as an output of the sample-and-hold circuit.

13. The switched capacitor circuit according to claim 1, configured as a capacitive feedback amplifier circuit, in particular for a delta modulator, comprising an input buffer connected to the third node and an amplifier and a third capacitor connected in parallel between the first node and the second node, wherein the second node is connected to the input of the amplifier and the first node is configured as an output of the capacitive feedback amplifier circuit.

14. The switched capacitor circuit according to claim 12, wherein said first capacitor and/or said second capacitor has a capacitance or have capacitances of at least 5 times the following value: 1/(2.Math..Math.f.Math.R), wherein f is a gate signal main frequency component of a gate signal supplied to the gate of the first and/or second MOS (1, 2) and R is a small-signal output resistance of said input buffer, a small-signal output resistance of said virtual ground buffer, a small-signal output resistance of said amplifier, or the lowest value of these three small-signal output resistance values.

15. The switched capacitor circuit according to claim 10, wherein said first capacitor and/or said second capacitor has a capacitance or have capacitances of at least 10 times of a first parasitic capacitance of the first node, of a second parasitic capacitance of the second node and/or of a third parasitic capacitance of the third node.

16. The switched capacitor circuit according to claim 10, wherein said first capacitor and/or said second capacitor has a capacitance or have capacitances of at least 20 times of a first parasitic capacitance of the first node, of a second parasitic capacitance of the second node and/or of a third parasitic capacitance of the third node.

17. The switched capacitor circuit according to claim 12, wherein said first capacitor and/or said second capacitor has a capacitance or have capacitances of at least 10 times the following value: 1/(2.Math..Math.f.Math.R), wherein f is a gate signal main frequency component of a gate signal supplied to the gate of the first and/or second MOS and R is a small-signal output resistance of said input buffer, a small-signal output resistance of said virtual ground buffer, a small-signal output resistance of said amplifier, or the lowest value of these three small-signal output resistance values.

18. The switched capacitor circuit according to claim 12, wherein said first capacitor and/or said second capacitor has a capacitance or have capacitances of at least 20 times the following value: 1/(2.Math..Math.f.Math.R), wherein f is a gate signal main frequency component of a gate signal supplied to the gate of the first and/or second MOS and R is a small-signal output resistance of said input buffer, a small-signal output resistance of said virtual ground buffer, a small-signal output resistance of said amplifier, or the lowest value of these three small-signal output resistance values.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Some examples of embodiments of the present invention will be explained in more detail in the following description with reference to the accompanying schematic diagrams, wherein:

[0031] FIG. 1A shows a first MOSFET circuit for minimizing charge injection and clock feedthrough, according to prior art;

[0032] FIG. 1B shows a second MOSFET circuit for minimizing charge injection and clock feedthrough, according to prior art;

[0033] FIG. 2 shows a third MOSFET circuit for minimizing charge injection and clock feedthrough, according to prior art;

[0034] FIG. 3 shows a fourth MOSFET circuit for minimizing charge injection and clock feedthrough, according to prior art;

[0035] FIG. 4 shows a fifth MOSFET circuit for minimizing charge injection and clock feedthrough, according to prior art;

[0036] FIG. 5 shows a MOSFET-based switch, according to one preferred embodiment;

[0037] FIG. 6 shows the switch of FIG. 5 embedded in a switched capacitor circuit, which is configured as a sample and hold circuit;

[0038] FIG. 7 shows a small-signal equivalent circuit of the switched capacitor circuit shown in FIG. 6 for an injected charge;

[0039] FIG. 8 shows the gate signals provided to the first and second MOS and their corresponding rise and fall times;

[0040] FIG. 9 shows the switch of FIG. 5 embedded in a switched capacitor circuit, which is configured as a capacitive feedback amplifier circuit; and

[0041] FIG. 10 shows a small-signal equivalent circuit of the switched capacitor circuit shown in FIG. 9 for an injected charge.

DETAILED DESCRIPTION

[0042] FIG. 5 shows a metal-oxide-semiconductor field-effect transistor-based switch, according to a preferred embodiment. The switch comprises first metal-oxide-semiconductor field-effect transistor 1 (in the following just MOS for short), a second MOS 2, a first capacitor C1, and a second capacitor C2. The first MOS 1, acting as a switch MOS, connects a first node T1 to a second node T2. Either the source or the drain of the first MOS 1 may be connected to the first node T1, so that the other terminal is connected to the second node T2. The second MOS 2, acting as a dummy MOS, has its source connected to its drain and both connected to only the second node T2. The first MOS 1 and the second MOS 2 are of the same type, but are controlled by inverted signals S1 and S2. The first MOS 1 and second MOS 2 can be either N or P type, while only N type is shown as an example hereafter. The second MOS 2 is half the size in terms of the channel area of the first MOS 1. In particular, the second MOS 2 has the same channel length as the first MOS 1, but half the channel width of the first MOS 1. The first node T1 is connected to a third node T3 via the first capacitor C1, while the second node T2 is connected to the third node T3 via the second capacitor C2.

[0043] The functioning principle of the switch shown in FIG. 5 will in the following be explained in connection with two different switched capacitor circuits, shown in the FIGS. 6 and 9.

[0044] FIG. 6 shows a switched capacitor circuit, which is configured as a sample and hold circuit. It may be viewed as a general-purpose sample and hold circuit, where the input signal is supplied to the first node T1 through an input buffer Bi and the output signal is supplied at the second node T2 that samples and holds the analog signal on the second capacitor C2. The third node T3 is the virtual ground terminal driven by a virtual ground buffer Bvg connected to a steady reference signal. Both the input buffer Bi and the virtual ground buffer Bvg are analog buffers.

[0045] The input buffer Bi has a small-signal output resistance of R1:

[00001]$R1=\left(\frac{V_{\mathrm{AP}}}{I_{\mathrm{DS}1}}\right).Math.\left(\frac{V_{\mathrm{AN}}}{I_{\mathrm{DS}1}}\right)$

[0046] Here V.sub.AP and V.sub.AN are the early voltage values of the NMOS and the PMOS inside the input buffer Bi that drive the first node T1, I.sub.DS1 is the drain-source current of the NMOS and the PMOS inside the input buffer Bi that drive the first node T1. is the operator for calculating a total resistance or impedance value of two resistances or impedances connected in parallel.

[0047] Similarly, the virtual ground buffer Bvg has a small-signal output resistance of R2:

[00002]$R2=\left(\frac{V_{\mathrm{AP}}}{I_{\mathrm{DS}2}}\right).Math.\left(\frac{V_{\mathrm{AN}}}{I_{\mathrm{DS}2}}\right)$

[0048] Here V.sub.AP and V.sub.AN are the early voltage values of the NMOS and the PMOS inside the virtual ground buffer Bvg that drive the third node T3, I.sub.DS2 is the drain-source current of the NMOS and the PMOS inside the virtual ground buffer Bvg that drive the third node T3.

[0049] The main frequency component of the first and second switching signals S1 and S2 connected to the gates of the first MOS 1 and the second MOS 2 is f. Therefore, the main frequency component of the charge injected by the first MOS 1 is also f. For the injected charge, the small-signal impedance of the first capacitor C1 is Z1 and the small-signal impedance of the second capacitor C2 is Z2 (here i stands for 1 or 2, and Ci stands for the corresponding capacitance of the first or second capacitor C1, C2):

[00003]$\mathrm{Zi}=\frac{1}{2.Math..Math.f.Math.\mathrm{Ci}}$

[0050] The small-signal equivalent circuit for the injected charge is shown in FIG. 7. The parasitic impedance ZP1, ZP2, or ZP3 (drawn with dashed lines) is the corresponding parasitic impedance between the first, second , or third node T1, T2, or T3 and the small-signal ground, respectively. They are caused by equivalent total parasitic capacitances CP1, CP2, CP3 between each of the three nodes T1, T2, T3 and the small-signal ground (here, i stands for 1, 2, or 3):

[00004]$\mathrm{ZPi}=\frac{1}{2.Math..Math.f.Math.\mathrm{CPi}}$

[0051] The desired values of the capacitances for the first and second capacitors C1 and C2 can be determined by two conditions. The first condition is that the values of Z1 and Z2 must be less than 1/10 (one tenth) of each of the values ZP1, ZP2, and ZP3. Hence, each of the capacitances, which are herein also denoted with C1 and C2, should fulfill the following constraint, where max(CP1, CP2, CP3) represents the largest of the three capacitance values CP1, CP2, and CP3 (here i stands for 1 or 2):

Ci>10.Math.max(CP1, CP2, CP3)

[0052] In practice, the parasitic capacitance values of CP1, CP2, CP3 are themselves influenced by the capacitance values C1 and C2. The two capacitors C1 and C2 are typically built as metal-insulator-metal (MIM) capacitors or metal-oxide-metal (MOM) capacitors. In general, if the values of C1 and C2 are less than 10 fF, the minimum capacitance values of CP1, CP2, CP3 are approximately in the range of 1 fF. Therefore, the values C1 and C2 usually should be at least 10 fF. The values of CP1, CP2, CP3 increase with the values of C1 and C2. By proper layout design, the value of CP1, CP2, CP3 can be kept to less than 1/10 of the values of C1 and C2. Therefore, the impedances Z1 and Z2 are kept to less than 1/10 of the parasitic impedances ZP1, ZP2, ZP3 by a proper layout design of the capacitors C1 and C2.

[0053] Furthermore, the second condition is that the values Z1 and Z2 must also be less than 1/10 of R1 and R2. For low-power sample-and-hold circuits, I.sub.DS1 and I.sub.DS2 usually range between 1 nA and 1 mA. Assuming V.sub.AP and V.sub.AN are both 10V, then R1 and R2 usually range between 5 kOhm and 510.sup.9 Ohm. If I.sub.DS1 and I.sub.DS2 are about 1 mA, then R1 and R2 are about 5 kOhm. Thus, the respective C1 and C2 constraint can be determined by the following formula, where min(R1, R2) represents the smaller of R1 and R2, and f is usually 10 GHz, which means that the switching signals S1 and S2 have rise and fall times of about 100 ps (here i stands for 1 or 2):

[00005]$\mathrm{Ci}>\frac{10}{2.Math..Math.f.Math.\min \left(R1,R2\right)}$

[0054] Therefore, if I.sub.DS1 and I.sub.DS2 are both about 1 mA, C1 and C2 should be at least 32 fF. If I.sub.DS1 and I.sub.DS2 are about 1 nA, R1 and R2 are about 510.sup.9 Ohm. In this case, the second condition only requires C1 and C2 to be larger than 3.210.sup.20 F.

[0055] Overall, the above two conditions require that for low-power sample-and-hold circuits with I.sub.DS1 and I.sub.DS2 ranging between 1 nA and 1 mA, C1 and C2 should be at least 32 fF. However, it is desirable that the above two conditions are not only met, but also exceeded to provide better charge injection cancellation performance (this is explained in more detail further below). For example, better charge injection cancellation can be achieved if Z1 and Z2 are less than 1/100 of ZP1, ZP2, ZP3 as well as R1 and R2, by choosing C1 and C2 to be at least 320 fF and keeping CP1, CP2, CP3 at less than 3.2 fF.

[0056] As a non-restricting example, assuming V.sub.AP and V.sub.AN are both 10V and f is 10 GHz, the following values can be chosen: I.sub.DS1 is 1 A, I.sub.DS2 is 10 A, so that R1 is 5M Ohm, R2 is 500 kOhm, R1 is larger than R2; C1 and C2 are both 100 fF, so that Z1 and Z2 are both about 160 Ohm, less than 1/1000 of R1 and R2. And CP1, CP2, and CP3 are kept less than 5 fF by the layout design, so that Z1 and Z2 are 20 times smaller than each of ZP1, ZP2, and ZP3.

[0057] During the sample phase, the first MOS 1 is on and the second MOS 2 is off. If both the first MOS 1 and the second MOS 2 are of N type, then the gate of the first MOS 1 is at a high voltage (S1=VDD) and the gate of the second MOS 2 is at a low voltage (S2=GND). If both the first MOS 1 and the second MOS 2 are of P type, then the gate of the first MOS 1 is at a low voltage (S1=GND) and the gate of the second MOS 2 is at a high voltage (S2=VDD). Therefore, in the sampling phase, the second node T2, which functions as the output terminal, is connected to the first node T1, which functions as the input terminal, and follows any input signal within the bandwidth of the input buffer (Bi).

[0058] To end the sample phase and enter the hold phase, the first MOS 1 is turned off and then the second MOS 2 is turned on. If both the first MOS 1 and the second MOS 2 are of N type, then the gate of the first MOS 1 transitions from a high voltage (S1=VDD) to a low voltage (S1=GND) and then the gate of the second MOS 2 transitions from a low voltage (S2=GND) to a high voltage (S2=VDD). If both the first MOS 1 and the second MOS 2 are of P type, then the gate of the first MOS 1 transitions from a low voltage (S1=GND) to a high voltage (S1=VDD) and then the gate of the second MOS 2 transitions from a high voltage (S2=VDD) to a low voltage (S2=GND).

[0059] When the first MOS 1 transitions from on state to off state, its residual channel charge is injected into both the first node T1 and the second node T2. For the injected charge, the total impedance between the first node T1 and the small-signal ground is ZT1 and the total impedance between the second node T2 and the small-signal ground is ZT2. Because both Z1 and Z2 are much smaller than R1, R2 and each of ZP1, ZP2 and ZP3, the following relationships hold: ZT1ZT2R1R2ZP1ZP2ZP3.

[0060] The tolerance of this approximate equality depends on the margin by which the design exceeds the previously mentioned two conditions that determine the constraints on C1 and C2. For example, if Z1 and Z2 are about 1/10 of ZP1, ZP2, ZP3, as well as R1 and R2, ZT1 may be different from ZT2 by 10%; whereas if Z1 and Z2 are about 1/100 of ZP1, ZP2, ZP3 as well as R1 and R2, ZT1 may be different from ZT2 by only 1%.

[0061] If ZT1 and ZT2 are approximately equal as seen by the residual channel charge of the first MOS 1, approximately half of the residual channel charge of the first MOS 1 is injected into each of the first node Ti and the second node T2.

[0062] Immediately after the first MOS 1 is turned off, the second MOS 2 starts transitioning from off state to on state as shown in FIG. 8, which shows a first gate signal S1 driving the gate of the first MOS 1 as a solid line and a second gate signal S2 driving the gate of the second MOS 2 as a dashed line. As described above, approximately half of the residual channel charge of the first MOS 1 is injected into the second node T2. Because the second MOS 2 has half the channel area of the first MOS 1, the channel of the second MOS 2 absorbs half of the residual channel charge of the first MOS 1 during the transition of the second MOS 2 from off state to on state. Therefore, after the second MOS 2 is turned on, the charge injected into the second node T2 by the first MOS 1 is approximately fully absorbed by the second MOS 2, achieving effective charge injection cancellation on the output terminal of the circuit. The bigger the margin by which the design exceeds the previously mentioned two conditions that determine the values of C1 and C2, the more effective the charge injection cancellation is.

[0063] Furthermore, because the channel width of the second MOS 2 is half of that of the first MOS 1, the total capacitance between the gate of the second MOS 2 and the second node T2, which is the sum of the gate-source capacitance and the gate-drain capacitance, approximately equals the gate-to-source (or the gate-to-drain, depending on whether the source or the drain of the first MOS 1 is connected to second node T2) capacitance between the first MOS 1 gate and the second node T2. Therefore, the clock feedthrough effect from the first MOS 1 gate signal S1 and the second MOS 2 gate signal S2 also effectively cancel each other on the second node T2.

[0064] Charge injection and clock feedthrough effects on the first node T1 are not of concern, because the first node T1 as the input terminal is driven and hence can eventually overcome these charge injection and clock feedthrough effects. During the hold phase, the first MOS 1 is off and the second MOS 2 is on. The output terminal at the second node T2 holds its voltage signal. R1 is designed to be larger than R2, which means I.sub.DS2 is larger than I.sub.DS1, hence the virtual ground buffer Vbg has larger driving strength and higher bandwidth than the input buffer Bi. Thus, the second node T2 is effectively isolated from the first node T1.

[0065] At the transition from the hold phase to the sample phase, the charge injection and clock feedthrough effects on both the first node T1 and the second node T2 are not of concern, because both the first node T1 and the second node T2 are driven in the sample phase and hence can eventually overcome the charge injection and clock feedthrough effects.

[0066] Single-input capacitive feedback amplifier circuits are used in delta modulator analog-to-digital converters. In the patent publication U.S. Pat. No. 7,728,269B2, titled Photoarray for detecting time-dependent image data, a capacitive feedback amplifier was used to encode a light intensity-dependent analog signal using delta modulation in each photo-sensing pixel. The capacitive feedback amplifier amplifies the difference in the analog signal since a previous reset. The reset switch resets the capacitive feedback amplifier and sets the new reference level to the current analog signal value. However, in practice, the reset switch made of a single MOS introduces charge injection and clock feedthrough whenever it switches off at the end of the reset period. The injected charge and clock feedthrough drive the capacitive feedback amplifier output to deviate from its reset level, leading to significant inaccuracies in the subsequent quantization stage.

[0067] FIG. 9 shows a switched capacitor circuit, which is configured as a capacitive feedback amplifier circuit. In this configuration, the first node T1 acts as an output terminal, connected to the output of the capacitive feedback amplifier. The third node T3 acts as an input terminal, driven by an input buffer Bi, which is an analog buffer, connected to the input signal. The second node T2 acts as a virtual ground terminal connected to the input of an amplifier A.

[0068] The input buffer Bi has a small-signal output resistance of R1:

[00006]$R1=\left(\frac{V_{\mathrm{AP}}}{I_{\mathrm{DS}1}}\right).Math.\left(\frac{V_{\mathrm{AN}}}{I_{\mathrm{DS}1}}\right)$

[0069] Here V.sub.AP and V.sub.AN are the early voltage values of the NMOS and the PMOS inside the input buffer Bi that drive the third node T3, I.sub.DS1 is the drain-source current of the NMOS and the PMOS inside the input buffer Bi that drive the third node T3. As always, is the operator for calculating a total resistance or impedance value of two resistances or impedances connected in parallel.

[0070] The amplifier A has a small-signal output resistance of R2:

[00007]$R2=\left(\frac{V_{\mathrm{AP}}}{I_{\mathrm{DS}2}}\right).Math.\left(\frac{V_{\mathrm{AN}}}{I_{\mathrm{DS}2}}\right)$

[0071] Here V.sub.AP and V.sub.AN are the early voltage values of the NMOS and the PMOS inside the amplifier A that drive the first node T1, I.sub.DS2 is the drain-source current of the NMOS and the PMOS inside the amplifier A that drive the first node T1.

[0072] The main frequency component of the switching signals S1 and S2 connected to the gates of the first MOS 1 and the second MOS 2 is f, therefore, the main frequency component of the injected charge is also f. For the injected charge, the small-signal impedance of the first capacitor C1 is Z1, the small-signal impedance of the second capacitor C2 is Z2, and the small-signal impedance of the third capacitor C3 is Z3 (here i stands for 1, 2 or 3, and Ci stands for the corresponding capacitance of the first, second or third capacitor C1, C2 or C3):

[00008]$\mathrm{Zi}=\frac{1}{2.Math..Math.f.Math.\mathrm{Ci}}$

[0073] The small-signal equivalent circuit for the injected charge is shown in FIG. 10. The parasitic impedance ZP1, ZP2, or ZP3 (drawn with dashed lines) is the corresponding parasitic impedance between the first, second or third node T1, T2, or T3 and the small-signal ground, respectively. They are caused by the equivalent total parasitic capacitance CP1, CP2, CP3 between each of the three nodes T1, T2, T3 and the small-signal ground (here, i stands for 1, 2, or 3):

[00009]$\mathrm{ZPi}=\frac{1}{2.Math..Math.f.Math.\mathrm{CPi}}$

[0074] The desired values of the capacitances for the first and second capacitors C1 and C2 can be determined by two conditions. The first condition is that the values of Z1 and Z2 must be less than 1/10 of each of the values ZP1, ZP2, and ZP3. Hence, each of the capacitances, which are herein also denoted with C1 and C2, should fulfill the following constraint, where max(CP1, CP2, CP3) represents the largest of the three capacitance values CP1, CP2, and CP3 (here i stands for 1 or 2):

Ci>10.Math.max(CP1, CP2, CP3)

[0075] In practice, the parasitic capacitance values of CP1, CP2, CP3 are themselves influenced by the capacitance values C1 and C2. The two capacitors C1 and C2 are typically built as metal-insulator-metal (MIM) capacitors or metal-oxide-metal (MOM) capacitors. In general, if the values of C1 and C2 are less than 10 fF, the minimum capacitance values of CP1, CP2, CP3 are approximately in the range of 1 fF. Therefore, the values C1 and C2 usually should be at least 10 fF. The values of CP1, CP2, CP3 increase with the values of C1 and C2. By proper layout design, the value of CP1, CP2, CP3 can be kept to less than 1/10 of the values of C1 and C2. Therefore, the impedances Z1 and Z2 are kept to less than 1/10 of the parasitic impedances ZP1, ZP2, ZP3 by a proper layout design of the capacitors C1 and C2.

[0076] Furthermore, the second condition is that the values Z1 and Z2 must also be less than 1/10 of R1 and R2. For low-power single-input capacitive feedback amplifier circuits especially implemented as 2D arrays as in U.S. Pat. No. 7,728,269B2, I.sub.DS1 and I.sub.DS2 usually range between 1 pA and 1 A, assuming V.sub.AP and V.sub.AN are both 10V, then R1 and R2 usually range between 5M Ohm and 510.sup.12 Ohm.

[0077] If I.sub.DS1 and I.sub.DS2 are about 1 A, then R1 and R2 are about 5M Ohm. Thus, the respective C1 and C2 constraint can be determined by the following formula, where min(R1, R2) represents the smaller of R1 and R2, and f is usually 10 GHz, which means that the switching signals S1 and S2 have rise and fall times of about 100 ps (here i stands for 1 or 2):

[00010]$\mathrm{Ci}>\frac{10}{2.Math..Math.f.Math.\min \left(R1,R2\right)}$

[0078] Therefore, if I.sub.DS1 and I.sub.DS2 are both about 1 A, C1 and C2 should be at least 3.210.sup.17 F. If I.sub.DS1 and I.sub.DS2 are about 1 pA, R1 and R2 are about 510.sup.12 Ohm. In this case, the second condition only requires C1 and C2 to be larger than 3.210.sup.23 F.

[0079] Overall, the above two conditions require that for low-power single-input capacitive feedback amplifier circuits with I.sub.DS1 and I.sub.DS2 ranging between 1 pA and 1 A, C1 and C2 should be at least 10 fF. However, it is desirable that the above two conditions are not only met, but also exceeded to provide better charge injection cancellation performance (this is explained in more detail further below). For example, better charge injection cancellation can be achieved if Z1 and Z2 are less than 1/100 of ZP1, ZP2, ZP3 as well as R1 and R2, by choosing C1 and C2 to be at least 100 fF and keeping CP1, CP2, CP3 less than 1 fF.

[0080] As a non-restricting example, assuming V.sub.AP and V.sub.AN are both 10V and f is 10 GHz, the following values can be chosen: I.sub.DS1 is 1 nA, I.sub.DS2 is 10 nA, so that R1 is 5 G Ohm, R2 is 500M Ohm, R1 is larger than R2; C1 and C2 are both 100 fF, so that Z1 and Z2 are both about 160 Ohm, less than 1/1000000 of R1 and R2. And CP1, CP2, and CP3 are kept less than 5 fF by the layout design, so that Z1 and Z2 are 20 times smaller than ZP1, ZP2, and ZP3. C3 is 5 fF, so the ratio between C2 and C3 is 20, setting a gain of 20 for the capacitive feedback amplifier.

[0081] During the reset phase, the first MOS 1 is on and the second MOS 2 is off If both the first MOS 1 and the second MOS 2 are of N type, then the gate of the first MOS 1 is at a high voltage (S1=VDD) and the gate of the second MOS 2 is at a low voltage (S2=GND). If both the first MOS 1 and the second MOS 2 are of P type, then the gate of the first MOS 1 is at a low voltage (S1=GND) and the gate of the second MOS 2 is at a high voltage (S2=VDD). Thus, in the reset phase, the potential of the first node T1 is driven to be equal to that of the second node T2. R1 is designed to be larger than R2, which means I.sub.DS2 is larger than Iasi, hence the virtual ground buffer Bvg has larger driving strength and higher bandwidth than the input buffer Bi. Thus, the first node T1 and the second node T2 keep their reset level without being influenced by the input signal.

[0082] To end the reset phase, the first MOS 1 is turned off and then the second MOS 2 is turned on. If both the first MOS 1 and the second MOS 2 are of N type, then the gate of the first MOS 1 transitions from a high voltage (S1=VDD) to a low voltage (S1=GND) and then the gate of the second MOS 2 transitions from a low voltage (S2=GND) to a high voltage (S2=VDD). If both the first MOS 1 and the second MOS 2 are of P type, then the gate of the first MOS 1 transitions from a low voltage (S1=GND) to a high voltage (S1=VDD) and then the gate of the second MOS 2 transitions from a high voltage (S2=VDD) to a low voltage (S2=GND).

[0083] When the first MOS 1 transitions from on state to off state, its residual channel charge is injected into both the first node T1 and the second node T2. For the injected charge, the total impedance between the first node T1 and the small-signal ground is ZT1 and the total impedance between the second node T2 and the small-signal ground is ZT2. Because both Z1 and Z2 are much smaller than R1, R2 and each of ZP1, ZP2 and ZP3, the following relationships hold: ZT1ZT2R1R2ZP1ZP2ZP3.

[0084] The tolerance of the approximate equality depends on the margin by which the design exceeds the previously mentioned two conditions that determine the constraints on C1 and C2. For example, if Z1 and Z2 are about 1/10 of ZP1, ZP2, ZP3, as well as R1 and R2, ZT1 may be different from ZT2 by 10%; whereas if Z1 and Z2 are about 1/100 of ZP1, ZP2, ZP3 as well as R1 and R2, ZT1 may be different from ZT2 by only 1%.

[0085] If ZT1 and ZT2 are approximately equal as seen by the residual channel charge of the first MOS 1, approximately half of the residual channel charge of the first MOS 1 is injected into each of the first node T1 and the second node T2.

[0086] Same as shown in FIG. 8, immediately after the first MOS 1 is turned off, the second MOS 2 then transition from off state to on state. As described previously, approximately half of the residual channel charge of the first MOS 1 is injected into the second node T2. Because the second MOS 2 has half the channel area of the first MOS 1, the channel of the second MOS 2 absorbs half of the residual channel charge of the first MOS 1 during the transition of the second MOS 2 from off state to on state. Therefore, after the second MOS 2 is turned on, the charge injected into the second node T2 by the first MOS 1 is approximately fully absorbed by the second MOS 2, achieving effective charge injection cancellation on the second node T2. The bigger the margin by which the design exceeds the previously mentioned two conditions that determine the values of C1 and C2, the more effective the charge injection cancellation is.

[0087] Furthermore, because the channel width of the second MOS 2 is half of that of the first MOS 1, the total capacitance between the gate of the second MOS 2 and the second node T2, which is the sum of the gate-source capacitance and the gate-drain capacitance, approximately equals the gate-to-source (or the gate-to-drain, depending on whether the source or the drain of the first MOS 1 is connected to second node T2) capacitance between the first MOS 1 gate and the second node T2. Therefore, the clock feedthrough effect from the first MOS 1 gate signal S1 and the second MOS 2 gate signal S2 also effectively cancel each other on the second node T2.

[0088] Charge injection and clock feedthrough effects on the first node T1 are not of concern, because the first node T1 as the output of the amplifier A is driven and hence can eventually overcome the charge injection and clock feedthrough effects.

[0089] During the amplification phase, the first MOS 1 is off and the second MOS 2 is on. The second node T2 holds its signal. The output terminal T2 produces an output signal that amplifies the change in the input signal, within the bandwidth of the capacitive feedback amplifier, by a gain determined by the ratio between C2 and C3.

[0090] At the transition from the amplification phase to the reset phase, the charge injection and clock feedthrough effects on both the second node T2 and the first node T1 are not of concern, because both the second node T2 and the first node T1 are driven in the reset phase and hence can eventually overcome the charge injection and clock feedthrough effects.

REFERENCE NUMERALS

[0091] 1 first metal-oxide-semiconductor field-effect transistor (first MOS) [0092] 2 second metal-oxide-semiconductor field-effect transistor (second MOS) [0093] C1 first capacitor [0094] C2 second capacitor [0095] C3 third capacitor [0096] S1 first gate signal [0097] S2 second gate signal [0098] T1 first node [0099] T2 second node [0100] T3 third node [0101] Bi input buffer [0102] Bvg virtual ground buffer [0103] A amplifier [0104] CP1, CP2, CP3 parasitic capacitances [0105] ZP1, ZP2, ZP3 parasitic impedances