MEMBER FOR SEMICONDUCTOR MANUFACTURING APPARATUS
20230223291 · 2023-07-13
Assignee
Inventors
Cpc classification
International classification
Abstract
A member for semiconductor manufacturing apparatus includes a ceramic plate that has an upper surface including a wafer placement surface and resin porous plugs that have upper surfaces that are exposed from the wafer placement surface. The resin porous plugs are press-fitted and secured in plug insertion holes that extend through the ceramic plate in an up-down direction and allow gas to flow.
Claims
1. A member for semiconductor manufacturing apparatus comprising: a ceramic plate that has an upper surface including a wafer placement surface; and a resin porous plug that has an upper surface that is exposed from the wafer placement surface, that is press-fitted and secured in a plug insertion hole that extends through the ceramic plate in an up-down direction, and that allows gas to flow.
2. The member for semiconductor manufacturing apparatus according to claim 1, wherein the ceramic plate has a conductive base on a lower surface, and wherein the resin porous plug is in contact with the conductive base.
3. The member for semiconductor manufacturing apparatus according to claim 1, wherein the resin porous plug contains a dense columnar solid member that has a diameter smaller than that of the resin porous plug.
4. The member for semiconductor manufacturing apparatus according to claim 1, wherein the resin porous plug contains a dense cylindrical hollow member that has a diameter smaller than that of the resin porous plug, that is inserted from a lower surface of the resin porous plug, and that does not extend through an upper surface of the resin porous plug.
5. The member for semiconductor manufacturing apparatus according to claim 1, wherein the resin porous plug contains a columnar porous member that has porosity higher than that of the resin porous plug.
6. The member for semiconductor manufacturing apparatus according to claim 1, wherein the wafer placement surface has a large number of small projections that support a wafer, and wherein the upper surface of the resin porous plug is lower than upper surfaces of the small projections.
7. The member for semiconductor manufacturing apparatus according to claim 6, wherein the upper surface of the resin porous plug is flush with a reference surface of the wafer placement surface on which the small projections are not formed or is lower than the reference surface by 0.5 mm or less.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
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DETAILED DESCRIPTION OF THE INVENTION
[0025] A preferred embodiment of the present invention will now be described with reference to the drawings.
[0026] The member 10 for semiconductor manufacturing apparatus includes the ceramic plate 20, a cooling plate 30, a metal joining layer 40, and resin porous plugs 50.
[0027] The ceramic plate 20 is a ceramic disk (having, for example, a diameter of 300 mm and a thickness of 5 mm) such as an alumina sintered body or an aluminum nitride sintered body. An upper surface of the ceramic plate 20 is a wafer placement surface 21. The ceramic plate 20 contains an electrode 22. As illustrated in
[0028] The cooling plate 30 is a disk (a disk that has a diameter equal to or larger than the diameter of the ceramic plate 20) that has good thermal conductivity. The cooling plate 30 contains a refrigerant flow path 32 through which refrigerant circulates and gas holes 34 in which gas is supplied to the resin porous plugs 50. The refrigerant flow path 32 is formed in a one-stroke pattern from an inlet to an outlet over the entire cooling plate 30 in a plan view. Each of the gas holes 34 is a hole with a step and has an upper opening edge around which a step portion 34c is located. Examples of the material of the cooling plate 30 include a metal material and a metal matrix composite material (MMC). Examples of the metal material include Al, Ti, Mo, or an alloy thereof. Examples of the MMC include a material containing Si, SiC, and Ti (also referred to as SiSiCTi) and a material obtained by impregnating a SiC porous body with Al and/or Si. A material that has a thermal expansion coefficient close to that of the ceramic plate 20 is preferably selected as the material of the cooling plate 30. The cooling plate 30 is also used as a RF electrode. Specifically, an upper electrode (not illustrated) is disposed above the wafer placement surface 21, and plasma is generated when high-frequency power is supplied between parallel flat plate electrodes that include the upper electrode and the cooling plate 30.
[0029] The metal joining layer 40 joins the lower surface of the ceramic plate 20 and the upper surface of the cooling plate 30 to each other. The metal joining layer 40 is formed by, for example, TCB (Thermal compression bonding). The TCB is a known method of compressing and joining two members in a state in which the two members to be joined interpose a metal joining material therebetween and are heated to a temperature equal to or less than the solidus temperature of the metal joining material. The metal joining layer 40 and the cooling plate 30 according to the present embodiment correspond to a conductive base according to the present invention.
[0030] The resin porous plugs 50 are press-fitted and secured in plug insertion holes 54. The plug insertion holes 54 extend through the ceramic plate 20 and the metal joining layer 40 in an up-down direction and are columnar holes that reach the step portions 34c that are disposed along the upper opening edges of the gas holes 34 of the cooling plate 30 and that are annular. The plug insertion holes 54 are formed at multiple positions (for example, multiple positions equally spaced from each other in a circumferential direction) in the ceramic plate 20. The resin porous plugs 50 are columnar resin porous members that allow the gas to flow in the up-down direction and that are composed of an electrical insulation material. The resin porous plugs 50 can be composed of a commercially available resin porous material such as PTFE, PPS, PEEK, or PEKK. Upper surfaces 50a of the resin porous plugs 50 are exposed from upper openings of the plug insertion holes 54 and are on the same plane as the reference surface 21c. The word “same” includes not only a case of being completely the same but also a case of being substantially the same (for example, a case of being within tolerance) (the same is true for the following description). The resin porous plugs 50 are press-fitted from the upper openings of the plug insertion holes 54 until lower surfaces 50b come in contact with the annular step portions 34c that define lower surfaces of the plug insertion holes 54 and are secured.
[0031] An example of the use of the member 10 for semiconductor manufacturing apparatus thus configured will now be described. The wafer W is first placed on the wafer placement surface 21 with the member 10 for semiconductor manufacturing apparatus installed in a chamber not illustrated. The pressure of the chamber is decompressed by a vacuum pump and is adjusted such that a predetermined degree of vacuum is achieved. A direct voltage is applied to the electrode 22 of the ceramic plate 20 to generate electrostatic attraction force, and the wafer W is attracted and secured to the wafer placement surface 21 (specifically, the upper surface of the seal band 21a and the upper surfaces of the circular small projections 21b). Subsequently, a reactive gas atmosphere at a predetermined pressure (for example, several tens of Pa to several hundreds of Pa) is created in the chamber. In this state, a high-frequency voltage is applied between an upper electrode, not illustrated, on a ceiling portion in the chamber and the cooling plate 30 of the member 10 for semiconductor manufacturing apparatus, and plasma is generated. The surface of the wafer W is processed by the generated plasma. The refrigerant circulates through the refrigerant flow path 32 of the cooling plate 30. Backside gas is introduced into the gas holes 34 from a gas tank not illustrated. Heat conduction gas (such as helium) is used as the backside gas. The backside gas passes through the gas holes 34 and the resin porous plugs 50, is supplied to a space between the back surface of the wafer W and the reference surface 21c of the wafer placement surface 21, and is sealed. The backside gas enables heat conduction between the wafer W and the ceramic plate 20 to be efficient.
[0032] An example of manufacturing the member 10 for semiconductor manufacturing apparatus will now be described with reference to
[0033] The lower surface of the ceramic plate 20 and the upper surface of the cooling plate 30 are joined to each other by using the TCB, and a joined body 94 is obtained (
[0034] Subsequently, the resin porous plugs 50 are prepared. The diameters of the resin porous plugs 50 are slightly larger than the diameters of the plug insertion holes 54. The resin porous plugs 50 are press-fitted from the upper openings of the plug insertion holes 54 until the lower surfaces 50b come in contact with the annular step portions 34c that define the lower surfaces of the plug insertion holes 54 and are secured. The resin porous plugs 50 have higher elasticity than a ceramic material and can be accordingly press-fitted and secured. The resin porous plugs 50 are designed such that the upper surfaces 50a are on the same plane as the reference surface 21c (see
[0035] As for the member 10 for semiconductor manufacturing apparatus described in detail above, the resin porous plugs 50 that allow the gas to flow are press-fitted and secured in the plug insertion holes 54 that extend through the ceramic plate 20 in the up-down direction. For this reason, it is not necessary to fire the resin porous plugs 50 when the resin porous plugs 50 are secured in the plug insertion holes 54. Even through the resin porous plugs 50 are degraded due to the use thereof, the resin porous plugs 50 that are degraded can be easily replaced with new resin porous plugs 50. Accordingly, the member 10 for semiconductor manufacturing apparatus that includes the porous plugs can be provided at low costs.
[0036] In the case where the resin porous plugs 50 are press-fitted and secured at the end of the manufacturing process, a subsequent process of cleaning the resin porous plugs 50 can be omitted.
[0037] The resin porous plugs 50 are in contact with the conductive base (the metal joining layer 40 and the cooling plate 30). In some cases where the resin porous plugs 50 are not in contact with the conductive base, arc discharge occurs between the resin porous plugs 50 and the conductive base. In the case where the resin porous plugs 50 are in contact with the conductive base, however, arc discharge can be inhibited from occurring.
[0038] The upper surfaces 50a of the resin porous plugs 50 are lower than the upper surface of the seal band 21a and the upper surfaces of the circular small projections 21b. For this reason, the upper surfaces 50a of the resin porous plugs 50 do not lift the wafer W.
[0039] The upper surfaces 50a of the resin porous plugs 50 are flush with the reference surface 21c of the wafer placement surface 21. For this reason, the heights of spaces between the lower surface of the wafer W and the upper surfaces 50a of the resin porous plugs 50 can be decreased. Accordingly, arc discharge can be prevented from occurring in the spaces.
[0040] It goes without saying that the present invention is not limited to the embodiment described above and can be carried out in various aspects within the technical scope of the present invention.
[0041] Resin porous plugs 150 to 350 illustrated in
[0042] The resin porous plug 150 in
[0043] The resin porous plug 250 in
[0044] The resin porous plug 350 in
[0045] According to the embodiment described above, the resin porous plugs 50 that have a columnar shape are used. However, resin porous plugs 550 and 650 that have shapes illustrated in
[0046] The resin porous plug 550 in
[0047] The resin porous plug 650 in
[0048] The resin porous plugs 550 and 650 in
[0049] According to the embodiment described above, the upper surfaces 50a of the resin porous plugs 50 and the reference surface 21c of the wafer placement surface 21 are flush with each other but are not particularly limited thereto. For example, as illustrated in
[0050] According to the embodiment described above, an electrostatic electrode is taken as an example of the electrode 22 that is contained in the ceramic plate 20, but this is not a particular limitation. For example, a heater electrode (a resistance heating element) may be contained in the ceramic plate 20, or a RF electrode may be contained therein, instead of or in addition to the electrode 22.
[0051] According to the embodiment described above, the ceramic plate 20 and the cooling plate 30 are joined to each other by the metal joining layer 40. A resin adhesive layer may be used instead of the metal joining layer 40. In this case, the cooling plate 30 corresponds to the conductive base according to the present invention.
[0052] The application claims priority to Japanese Patent Application No. 2022-001652 filed in the Japan Patent Office on Jan. 7, 2022, the entire contents of which are incorporated herein by reference.