METHOD, UNIT AND CIRCUIT FOR IMPLEMENTING BOOLEAN LOGIC BASED ON COMPUTING-IN-MEMORY TRANSISTOR

Abstract

A method, a unit and circuits for implementing Boolean logics based on computing-in-memory transistors. The method is implemented by using the characteristics and the read-write mode of the computing-in-memory transistor; the basic unit consists of a computing-in-memory transistor and a pull resistor; the pull resistor in the basic unit is connected in series with the transistor, and the gate of the transistor is independent; the basic units can implement sixteen Boolean logic operations through different circuit structures and voltage configuration schemes. Compared with the logic circuit structure of the conventional CMOS transistors, the present disclosure can implement more logic operations with fewer transistors, which greatly optimizes circuit density and computing speed caused by data transmission between storage units and process units.

Claims

1. An in-memory computing logic circuit based on computing-in-memory transistors comprises three basic units, wherein a basic unit comprises a computing-in-memory transistor and a pull resistor, the pull resistor is connected in series with the computing-in-memory transistor, a gate of the computing-in-memory transistor is independent, and one end of the pull resistor is connected with a drain of the computing-in-memory transistor; wherein a drain of a first-stage computing-in-memory transistor is connected with a gate of a second-stage basic unit, so that the first-stage basic unit is cascaded with the second-stage basic unit, the second-stage basic unit and a third-stage basic unit share a pull resistor, a drain of a second-stage computing-in-memory transistor is connected with a drain of a third-stage computing-in-memory transistor, and a source of the second-stage computing-in-memory transistor is connected with a source of the third-stage computing-in-memory transistor, so that the second-stage basic unit and the third-stage basic unit are connected in parallel; a gate of the first-stage computing-in-memory transistor and a gate of the third-stage computing-in-memory transistor are input ports of the in-memory computing logic circuit; and the drain voltage of the third-stage computing-in-memory transistor is an output of the in-memory computing logic circuit; wherein the second-stage basic unit and the third-stage basic unit are in parallel structure, a port connected with the pull resistor of the parallel structure and a source of the first-stage computing-in-memory transistor are grounded, a source of the computing-in-memory transistor of the parallel structure and the port connected with the first-stage pull resistor are connected to V.sub.dd; a threshold voltage of the first-stage computing-in-memory transistor is V.sub.t0/V.sub.t−, a threshold voltage of the second-stage computing-in-memory transistor is V.sub.t0, a threshold voltage of the third-stage computing-in-memory transistor is V.sub.t+/V.sub.t0, and the first-stage basic unit implements NOR logic operation; and wherein the in-memory computing logic circuit implements XNOR logic operation of AB+AB; the threshold voltage of the first-stage computing-in-memory transistor and the threshold voltage of the third-stage computing-in-memory transistor correspond to a same logic value denoted by A; and a gate voltage of the first-stage computing-in-memory transistor and a gate voltage of the third-stage computing-in-memory transistor correspond to a same logic value denoted by B.

2. An in-memory computing logic circuit based on computing-in-memory transistors comprising three basic units, wherein the basic unit comprises a computing-in-memory transistor and a pull resistor, the pull resistor is connected in series with the computing-in-memory transistor, and the gate of the computing-in-memory transistor is independent, one end of the pull resistor is connected with the drain of the computing-in-memory transistor; wherein a drain of a first-stage computing-in-memory transistor is connected with the gate of a second-stage basic unit, so that a first-stage basic unit is cascaded with the second-stage basic unit; the second-stage basic unit and a third-stage basic unit share a pull resistor, a drain of the second-stage computing-in-memory transistor is connected with a drain of a third-stage computing-in-memory transistor, and a source of the second-stage computing-in-memory transistor is connected with a source of the third-stage computing-in-memory transistor, so that the second-stage basic unit and the third-stage basic unit are connected in parallel; the gate of the first-stage computing-in-memory transistor and the gate of the third-stage computing-in-memory transistor are input ports of the in-memory computing logic circuit, the drain voltage of the third-stage computing-in-memory transistor is the output of the in-memory computing logic circuit; wherein the second-stage basic unit and the third-stage basic unit are in parallel structure; a source of the computing-in-memory transistor of the parallel structure and a source of the first-stage computing-in-memory transistor are grounded, a port connected with a pull resistor of the parallel structure and a port connected with a first-stage pull resistor are connected to V.sub.dd, a threshold voltage of the first-stage computing-in-memory transistor is V.sub.t0/V.sub.t−, a threshold voltage of the second-stage computing-in-memory transistor is V.sub.t0, a threshold voltage of the third-stage computing-in-memory transistor is V.sub.t+/V.sub.t0, the first-stage basic unit implements NOR logic operation; and wherein the in-memory computing logic circuit implements XOR logic operation of AB+AB; the threshold voltage of the first-stage computing-in-memory transistor and the threshold voltage of the third-stage computing-in-memory transistor correspond to a same logic value denoted by A, a gate voltage of the first-stage computing-in-memory transistor and a gate voltage of the third-stage computing-in-memory transistor correspond to a same logic value denoted by B.

3. The in-memory computing logic circuit according to claim 1, wherein in the basic unit, a threshold voltage (V.sub.t) of the computing-in-memory transistor represents the input A of the basic unit; a gate voltage (V.sub.in) of the computing-in-memory transistor represents the input B of the basic unit, A and B are serial inputs; a drain voltage of the computing-in-memory transistor is an output V.sub.out of the basic unit; an end of the pull resistor that is not connected to the computing-in-memory transistor is a port T1, and the source of the computing-in-memory transistor is a port T2.

4. The in-memory computing logic circuit according to claim 3, wherein in the basic unit, the gate voltage (V.sub.in) and the threshold voltage (V.sub.t) of the computing-in-memory transistor satisfy:
V.sub.t+>V.sub.in+>V.sub.t0>V.sub.in−>V.sub.t− where the gate voltage V.sub.in is modulated between V.sub.in+ and V.sub.in−, and the threshold voltage V.sub.t is modulated between V.sub.t+, V.sub.t0 and V.sub.t−.

5. The in-memory computing logic circuit according to claim 4, wherein the basic unit is configured to implement ten kinds of Boolean logics, consisting of: 1, 0, A, B, Ā, B, AB, A+B, , , modulating the threshold voltage of the computing-in-memory transistor is capable of changing the AND/OR logic relationship of A and B, and the configuration scheme of the port voltages of the basic unit determines whether the in-memory computing logic circuit has a NOT gate function.

6. The in-memory computing logic circuit according to claim 5, wherein a method for implementing the Boolean logics of the basic unit including: a) when a port T1 is grounded and a voltage of port T2 is V.sub.dd, the threshold voltage of the computing-in-memory transistor is V.sub.t0, the logic operation of 0 or 1 is complemented by modulating the gate voltage: when an applied gate voltage is V.sub.in+, which is greater than the threshold voltage V.sub.t0, an output is 1, when the applied gate voltage is V.sub.in−, which is less than the threshold voltage V.sub.t0, an output is 0; b) when the output is irrelated to B, the gate voltage of the computing-in-memory transistor is V.sub.in+ and the threshold voltage is V.sub.t+/V.sub.t−, the logic operation of A is implemented, the logic value of A is related with a modulation of the threshold voltage: when the threshold voltage is V.sub.t+, which is greater than the gate voltage the logic value of A is 0, and when the threshold voltage is V.sub.t−, which is less than the gate voltage the logic value of A is 1; the logic operation of A is implemented by adjusting the port voltage: when the port T2 is grounded and the voltage of the port T1 is V.sub.dd, the NOT operation is performed, an output of Boolean logic is A; c) when the output is irrelated to A, the threshold voltage of the computing-in-memory transistor is V.sub.t0, and the gate voltage is V.sub.in+/V.sub.in−, the logic operation of B is implemented, the logic value of B is related with the modulation of the gate voltage: when the gate voltage is which is greater than the threshold voltage V.sub.t0, the logic value of B is 1, and when the gate voltage is V.sub.in−, which is less than the threshold voltage V.sub.t0, the logic value of B is 0; the logic operation of 173 is implemented by adjusting the port voltage: when the port T2 is grounded and the voltage of the port T1 is V.sub.dd, the NOT operation is performed, an output of Boolean logic is 11; and d) when the output logic is related to both A and B, the applied gate voltage is V.sub.in+/V.sub.in−, that is, the logic value of B is 1/0: d1) when the threshold voltage is V.sub.+/V.sub.t0, that is, the logic value of A is 1/0, two logic operations of , AB are implemented by adjusting the port voltage to configurate the NOT gate function or not; and d2) when the threshold voltage is V.sub.t0/V.sub.t−, the logic value of A is 1/0, two logic operations of , A+B are implemented by adjusting the port voltage to configurate the NOT gate function or not.

7. The in-memory computing logic circuit according to claim 6, wherein by cascading two basic units, four Boolean logics of A+B, Ā+B, AB, ĀB are implemented, the voltage of port T1 is V.sub.dd, the port T2 is grounded, and a gate voltage (V.sub.in1) of a upper-stage computing-in-memory transistor is V.sub.in+/V.sub.in−, a upper-stage basic unit performs the NOT operation, and its output V.sub.out1 is B; the logic operations of A+B are implemented by modulating a threshold voltage of a lower-stage computing-in-memory transistor; a configuration scheme of port voltages of a lower-stage basic unit determines whether to perform the NOT operation to implement the logic operations of Ā+B, ĀB.

8. The in-memory computing logic circuit according to claim 7, wherein a configuration of the NOT gate function achieved by adjusting the port voltage includes: when port T1 is grounded and the voltage of port T2 is V.sub.dd, the basic unit has no NOT gate function, and when the voltage of port T1 is V.sub.dd and port T2 is grounded, the basic unit has a NOT gate function.

9. The in-memory computing logic circuit according to claim 1, wherein the computing-in-memory transistor is a non-volatile three-terminal memory transistor.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0032] FIG. 1 is a logic circuit structure diagram of an in-memory computing basic unit according to the present disclosure;

[0033] FIG. 2 is a structural diagram of a logic circuit consisting of basic units in cascade according to the present disclosure;

[0034] FIG. 3 is a structure diagram of an XNOR circuit consisting of cascaded and parallel basic units according to the present disclosure; and

[0035] FIG. 4 is a structural diagram of an XOR circuit consisting of cascaded and parallel basic units according to the present disclosure.

DESCRIPTION OF EMBODIMENTS

[0036] The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure. The described embodiments are only some of the possible embodiments of the present disclosure, but not all of them. They are intended to provide a basic understanding of the present disclosure, and are not intended to confirm the key or decisive elements of the present disclosure or limit the scope to be protected. It is easy to understand that, according to the technical solutions of the present disclosure, a general technical personnel in this filed can propose other alternative implementations without changing the essential spirit of the present disclosure. Therefore, the following detailed description and drawings are only examples of the technical solutions of the present disclosure, and should not be regarded as the whole solutions of the present disclosure or as a limitation of the technical solutions of the present disclosure.

[0037] The present disclosure relates to a method, a unit and circuits for implementing Boolean logic based on computing-in-memory transistors, which implements the Boolean logic operations by using the characteristics and the read-write mode of the computing-in-memory transistors. The basic unit of the present disclosure consists of a pull resistance and a computing-in-memory transistor whose threshold voltage can be controlled by the external physical field; the threshold voltage and gate voltage of the computing-in-memory transistor represent inputs A and B respectively, A and B are serial inputs. The pull resistor in the basic unit is connected in series with the computing-in-memory transistor, and the gate of the transistor is independent. The basic units can implement sixteen kinds of basic Boolean logic operations through different circuit structures and configuration schemes of port voltage: one basic unit described above can implement ten kinds of basic Boolean logics: 1, 0, A, B, Ā, B, AB, A+B, and , and modulating the threshold voltage of the computing-in-memory transistor can change the AND/OR logic relationship of A and B, the configuration scheme of the port voltages of the basic unit determines whether it has the NOT-gate function; four kinds of logic operations can be implemented through the cascade of two basic units described above, and the cascade mode is that the output port of the previous-stage basic unit is connected with the gate of the next-stage basic unit, this circuit structure can implement four logic operations of A+B, Ā+B, AB and ĀB; two logic operations of XNOR (AB+) and XOR (ĀB+AB) can be implemented through the combination of the cascade circuit.

[0038] As shown in FIG. 1, an in-memory computing basic unit of the present disclosure consists of a pull resistor and a computing-in-memory transistor; the threshold voltage V.sub.t of the computing-in-memory transistor can be controlled by an external physical field, and logic information can be stored by adjusting the input of the threshold voltage. The pull resistor is connected in series with the transistor, and the gate of the transistor is independent. The drain of the computing-in-memory transistor is connected with one end of the pull resistor, and the drain voltage V.sub.t is used as the logic output of the basic unit; the other end of the pull resistor is connected to the port T1, and the source of the computing-in-memory transistor is connected to the port T2. This embodiment adopts ferroelectric-based computing-in-memory transistor.

[0039] The threshold voltage V.sub.t of the ferroelectric-based computing-in-memory transistor represents the input A (V.sub.t can be modulated between V.sub.t+, V.sub.t0 and V.sub.t−); the gate voltage V.sub.in represents the input B (V.sub.in can be modulated between V.sub.in+ and V.sub.in−). A and B are serial inputs, and modulating the threshold voltage V.sub.t of the transistor can implement the logic operation of AND/OR between A and B; In this embodiment, the threshold voltage of the ferroelectric-based computing-in-memory transistor is firstly modulated to realize the input of the value A, and then the gate voltage is applied to realize the input of the value B. Different configuration schemes of port voltages can decide whether to implement the NOT-gate function.

[0040] The threshold voltage V.sub.t and the gate voltage V.sub.in satisfy the following relationship:

V.sub.t+>V.sub.in+>V.sub.t0>V.sub.in−>V.sub.t−

[0041] where the gate voltage V.sub.in is modulated between V.sub.in+ and V.sub.in−, and the threshold voltage V.sub.t is modulated between V.sub.t+, V.sub.t0 and V.sub.t−; V.sub.t0 is the threshold voltage before applying the pulse of programing or erasing. When the gate voltage V.sub.in is greater than the threshold voltage V.sub.t, the transistor is turned on (the logic output is 1); when the gate voltage V.sub.in is less than the threshold voltage V.sub.t, the transistor is turned off (the logic output is 0).

[0042] The present disclosure relates to a method for implementing logic operations based on a single in-memory computing basic unit, which implements ten kinds of Boolean logics through the voltage configuration of the in-memory computing basic unit (according to Table 1), including: 1 0 A B Ā B AB A+B .

[0043] a) When the port T1 is grounded and the voltage of the port T2 is V.sub.dd, the threshold voltage of the ferroelectric-based computing-in-memory transistor is V.sub.t0, the logic operation of 0 or 1 is complemented by modulating the gate voltage: when an applied gate voltage is V.sub.in+, which is greater than the threshold voltage V.sub.t0, the output is 1; when the applied gate voltage is V.sub.in−, which is less than the threshold voltage V.sub.t0, the output is 0;

[0044] b) When the output is irrelated to B, the gate voltage of the ferroelectric-based computing-in-memory transistor is V.sub.in+ and the threshold voltage is V.sub.t+/V.sub.t−, the logic operation of A is implemented, the logic value of A is related with the modulation of the threshold voltage: when the threshold voltage is V.sub.t+, which is greater than the gate voltage V.sub.in+, the logic value of A is 0; when the threshold voltage is V.sub.t−, which is less than the gate voltage V.sub.in+, the logic value of A is 1; the logic operation of Ā is implemented by adjusting the port voltage: when the port T2 is grounded and the voltage of the port T1 is V.sub.dd, the NOT gate function can be achieved, and the output of Boolean logic is Ā;

[0045] c) When the output is irrelated to A, the threshold voltage of the ferroelectric-based computing-in-memory transistor is V.sub.t0, and the gate voltage is V.sub.in+/V.sub.in−, the logic operation of B is implemented, the logic value of B is related with the modulation of the gate voltage: when the gate voltage is V.sub.in+, which is greater than the threshold voltage V.sub.t0, the logic value of B is 1; when the gate voltage is V.sub.in−, which is less than the threshold voltage V.sub.t0, the logic value of B is 0; the logic operation of B is implemented by adjusting the port voltage: when the port T2 is grounded and the voltage of the port T1 is V.sub.dd, the NOT gate function can be achieved, the output of Boolean logic is 173;

[0046] d) When the output is related to both A and B, the applied gate voltage is V.sub.in+/V.sub.in− (i.e. the logic value of B is 1/0):

[0047] d1) When the threshold voltage is V.sub.+/V.sub.t0 (i.e. the logic value of A is 1/0), two logic operations of AB, AB are implemented by adjusting the port voltage: when the port T1 is grounded and the voltage of the port T2 is V.sub.dd, the output of Boolean logic is AB; when the port T2 is grounded and the voltage of the port T1 is V.sub.dd, the NOT gate function can be achieved, the output of Boolean logic is ;

[0048] d2) When the threshold voltage is V.sub.t0/V.sub.t− (i.e. the logic value of A is 1/0), two logic operations of , A+B can be implemented by adjusting the port voltage: when the port T1 is grounded and the voltage of the port T2 is V.sub.dd, the output of Boolean logic is A+B; when the port T2 is grounded and the voltage of the port T1 is V.sub.dd, the NOT gate function can be achieved, the output of Boolean logic is .

TABLE-US-00001 TABLE 1 Configuration schemes of ten Boolean logic operations with adjustable port voltage, gate voltage and threshold voltage Port voltage, Gate voltage, Threshold voltage T1 T2 V.sub.in V.sub.t Boolean 0 GND V.sub.dd V.sub.in− V.sub.t0 logics 1 GND V.sub.dd V.sub.in+ V.sub.t0 A GND V.sub.dd V.sub.in+ V.sub.t+/V.sub.t− (0/1) B GND V.sub.dd V.sub.in+/V.sub.in− (1/0) V.sub.t0 Ā V.sub.dd GND V.sub.in+ V.sub.t+/V.sub.t− (0/1) B V.sub.dd GND V.sub.in+/V.sub.in− (1/0) V.sub.t0 AB GND V.sub.dd V.sub.in+/V.sub.in− (1/0) V.sub.t+/V.sub.t0 (0/1) A + B GND V.sub.dd V.sub.in+/V.sub.in− (1/0) V.sub.t0/V.sub.t− (0/1) V.sub.dd GND V.sub.in+/V.sub.in− (1/0) V.sub.t+/V.sub.t0 (0/1) V.sub.dd GND V.sub.in+/V.sub.in− (1/0) V.sub.t0/V.sub.t− (0/1)

[0049] Taking the implementation of the logic output as an example, specifically, according to the value of the input A, the threshold voltage V.sub.t of the ferroelectric-based computing-in-memory transistor is set to V.sub.t0 or V.sub.t− (i.e. the logic value of A is 0 or 1). According to the value of the input B, the gate voltage is set to V.sub.in+ or V.sub.in− (i.e. logic value of B is 1 or 0). Table 2 shows the Karnaugh map of the logical functions between A and B, and it can be deduced that the logic output is A+B. On this basis, the logic operation of can be implemented by adjusting the port voltage: when the port T2 is grounded and the voltage of the port T1 is V.sub.dd, the NOT gate function can be achieved, and the logic output is .

TABLE-US-00002 TABLE 2 Karnaugh map of logical functions between A and B B 0 1 A (V.sub.in−) (V.sub.in+) 0 0 1 (V.sub.t0) (V.sub.t0 > V.sub.in−) (V.sub.t0 < V.sub.in+) 1 1 1 (V.sub.t−) (V.sub.t− < V.sub.in−) (V.sub.t− < V.sub.in+)

[0050] As shown in FIG. 2, the logic circuit of the present disclosure consists of two in-memory computing basic units in cascade, which can implement more logic operations; the output port of the upper-stage basic unit is connected to the gate of the lower-stage basic unit. The threshold voltage V.sub.t1 of the upper-stage ferroelectric-based computing-in-memory transistor is V.sub.t0, and the gate voltage V.sub.ii is a logic input B. The gate voltage V.sub.in2 of the lower-stage ferroelectric-based computing-in-memory transistor is the output voltage V.sub.out1 of the upper-stage basic unit; the threshold voltage V.sub.t2 of the lower-stage ferroelectric-based computing-in-memory transistor is a logic input A, and the drain voltage V.sub.out2 is taken as the output of the logic circuit. One end of the upper-stage pull resistor, which does not output V.sub.out1, is a port T1, and the source of the upper-stage computing-in-memory transistor is connected to the port T2; one end of the lower-stage pull resistor, which does not output V.sub.out2, is a port T3, and the source of the lower-stage computing-in-memory transistor is connected to the port T4.

[0051] When the voltage of port T1 is V.sub.dd, and the port T2 is grounded, the upper-stage basic unit has the NOT gate function.

[0052] The present disclosure relates to a method for implementing Boolean logic operation based on two cascaded in-memory computing basic units. The logic output is related to both A and B, and four Boolean logic operations are implemented according to Table 3.

[0053] The voltage of port T1 is V.sub.dd, the port T2 is grounded, and the gate voltage V.sub.in1 of the upper-stage computing-in-memory transistor is V.sub.in+/V.sub.in−, an upper-stage basic unit has the NOT gate function at this time, and its output V.sub.out1 is B; by modulating the threshold voltage of the lower-stage computing-in-memory transistor, logic operations of AB, A+B are implemented; the configuration scheme of the port voltages of the lower-stage basic unit (i.e. T3, T4) determines whether to perform the NOT operation on the logic operations of A+B:

[0054] e) When the port T3 is grounded, the voltage of port T4 is V.sub.dd, and the threshold voltage V.sub.t2 of the lower-stage computing-in-memory transistor is V.sub.t+/V.sub.t0, the logic operation of AB can be implemented;

[0055] f) When the port T3 is grounded, the voltage of port T4 is V.sub.dd, and the threshold voltage V.sub.t2 of the lower-stage computing-in-memory transistor is V.sub.t0/V.sub.t−, the logic operation of A+173 can be implemented;

[0056] g) When the voltage of port T3 is V.sub.dd, the port T4 is grounded, and the threshold voltage V.sub.t2 of the lower-stage computing-in-memory transistor is V.sub.t+/V.sub.t0, the logic operation of Ā+B can be implemented;

[0057] h) When the voltage of port T3 is V.sub.dd, the port T4 is grounded, and the threshold voltage V.sub.t2 of the lower-stage computing-in-memory transistor is V.sub.t0/V.sub.t−, the logic operation of ĀB can be implemented.

TABLE-US-00003 TABLE 3 Configuration schemes for implementing four kinds of Boolean logics through the cascade of two basic units Boolean logics A + B Ā + B AB ĀB Port voltage, T1 V.sub.dd V.sub.dd V.sub.dd V.sub.dd Gate voltage, T2 GND GND GND GND Threshold voltage T3 GND V.sub.dd GND V.sub.dd T4 V.sub.dd GND V.sub.dd GND V.sub.in1 V.sub.in+/V.sub.in− V.sub.in+/V.sub.in− V.sub.in+/V.sub.in− V.sub.in+/V.sub.in− V.sub.in2 V.sub.out1 V.sub.out1 V.sub.out1 V.sub.out1 V.sub.t1 V.sub.t0 V.sub.t0 V.sub.t0 V.sub.t0 V.sub.t2 V.sub.t0/V.sub.t− V.sub.t+/V.sub.t0 V.sub.t+/V.sub.t0 V.sub.t0/V.sub.t−

[0058] Taking the implementation of the logic output AB as an example, specifically, a voltage V.sub.dd is applied to port T1 and port T4 respectively, the port T2 and port T3 are grounded; the gate voltage V.sub.in1 of the upper-stage ferroelectric-based computing-in-memory transistor is set to V.sub.in+ or V.sub.in−, when the threshold voltage V.sub.t1 is modulated to V.sub.t0, the output V.sub.out1 of the upper-stage basic unit is 11; when the threshold voltage V.sub.t2 of the lower-stage basic unit is modulated to V.sub.t+ or V.sub.t0, the AND gate function is implemented, and the output of logic circuit is AB.

[0059] As shown in FIG. 3, the present disclosure provides an XNOR circuit consisting of three basic units in cascade and parallel connection. The drain of the first-stage computing-in-memory transistor is connected with the gate of the second-stage basic unit, so that the first-stage basic unit is cascaded with the second-stage basic unit; the second-stage basic unit and the third-stage basic unit share a pull resistor, the drain of the second-stage computing-in-memory transistor is connected with the drain of the third-stage computing-in-memory transistor, and the source of the second-stage computing-in-memory transistor is connected with the source of the third-stage computing-in-memory transistor, so that the second-stage basic unit and the third-stage basic unit are connected in parallel. The gate of the first-stage computing-in-memory transistor and the gate of the third-stage computing-in-memory transistor are input ports of the in-memory computing logic circuit; the drain voltage of the third-stage computing-in-memory transistor is an output of the in-memory computing logic circuit. The threshold voltage of the first-stage computing-in-memory transistor and the threshold voltage of the third-stage computing-in-memory transistor correspond to the same logic value, which are denoted by A; the gate voltage of the first-stage computing-in-memory transistor and the gate voltage of the third-stage computing-in-memory transistor correspond to the same logic value, which are denoted by B.

[0060] For the ferroelectric-based computing-in-memory transistor of the first-stage basic unit, the gate voltage is set to V.sub.in+/V.sub.in−, and the threshold voltage is set to V.sub.t0/V.sub.t−, so that the logic gate 1 is A+B.

[0061] When the source of the first-stage basic unit is grounded and the port voltage of the first-stage pull resistor is V.sub.dd, the NOR operation () can be implemented. Seeing Table 1 for specific operating conditions.

[0062] The output voltage of the ferroelectric-based computing-in-memory transistor of the first-stage basic unit is the gate input of the second-stage basic unit; the threshold voltage of the ferroelectric-based computing-in-memory transistor of the second-stage basic unit is set to V.sub.t0, which implements the function of the input transmission, that is, the logic gate 2 is .

[0063] When the threshold voltage of the ferroelectric-based computing-in-memory transistor of the third-stage basic unit is set to V.sub.t+/V.sub.t0, the logic gate 3 implements the logic operation of AB.

[0064] The second-stage basic unit is connected in parallel with the third-stage basic unit, this parallel structure can implement OR logic operation of the logic gate 2 and logic gate 3.

[0065] Therefore, the whole circuit structure implements the XNOR logic operation, and the logic expression is: +AB=+AB.

[0066] As shown in FIG. 4, the present disclosure provides an XOR circuit based on three basic units connected in cascade and parallel. The first-stage basic unit is cascaded with the second-stage basic unit, and the second-stage basic unit is connected in parallel with the third-stage basic unit. The gate of the first-stage ferroelectric-based computing-in-memory transistor and the gate of the third-stage ferroelectric-based computing-in-memory transistor are taken as input ports; the drain voltage of the third-stage computing-in-memory transistor is the output of the in-memory computing logic circuit. The threshold voltage of the first-stage computing-in-memory transistor and the threshold voltage of the third-stage computing-in-memory transistor correspond to the same logic value, which are denoted by A; the gate voltage of the first-stage computing-in-memory transistor and the gate voltage of the third-stage computing-in-memory transistor correspond to the same logic value, which are denoted by B.

[0067] For the ferroelectric-based computing-in-memory transistor of the first-stage basic unit, the gate voltage is set to V.sub.in+/V.sub.in−, and the threshold voltage is set to V.sub.t0/V.sub.t−, so that the logic gate 1 is A+B. When the source of the first-stage basic unit is grounded and the port voltage of the first-stage pull resistor is V.sub.dd, the NOR operation () can be implemented. Seeing Table 1 for specific operating conditions.

[0068] The output voltage of the ferroelectric-based computing-in-memory transistor of the first-stage basic unit is the gate input of the second-stage basic unit; the threshold voltage of the ferroelectric-based computing-in-memory transistor of the second-stage basic unit is set to V.sub.t0, which implements the function of the input transmission, that is, the logic gate 2 is .

[0069] When the threshold voltage of the ferroelectric-based computing-in-memory transistor of the third-stage basic unit is set to V.sub.t+/V.sub.t0, the logic gate 3 implements the logic operation of AB.

[0070] When the second-stage basic unit is connected in parallel with the third-stage basic unit, the source of the transistor of the parallel structure is grounded and the port voltage connected with the pull resistor is V.sub.dd, the NOR logic operation of the logic gate 2 and logic gate 3 can be implemented.

[0071] Therefore, the whole circuit structure implements the XOR logic operation, and its logic expression is =AB+ĀB.

[0072] The present disclosure has been described in detail above. Compared with the logic circuit structure of the conventional CMOS transistors, the present disclosure can implement more logic operations with fewer transistors; compared with the current Von Neumann computing architecture, it can avoid the delay and power consumption caused by data transmission between storage units and process units, which plays an important role in realizing a new computing architecture, improving computing speed and energy efficiency, and increasing the integrated-circuit density.