ULTRA-LOW JITTER LOW-POWER W/D-BAND PHASE-LOCKED LOOP USING POWER-GATING INJECTION-LOCKED FREQUENCY MULTIPLIERBASED PHASE DETECTOR

Abstract

Proposed are an ultra-low jitter low-power phase-locked loop using a power-gating injection-locked frequency multiplier-based phase detector (PG-ILFM PD) and an operating method thereof. The proposed PG-ILFM PD includes a replica voltage controlled oscillator (R-VCO) configured to cut off the power supply of the R-VCO repeatedly based on a reference signal S.sub.REF and a fundamental sampling phase detector (FSPD) configured to receive an output signal S.sub.ILFM of the R-VCO as a reference signal for sampling and detect a phase error of a main voltage controlled oscillator (M-VCO).

Claims

1. A phase-locked loop comprising: a power-gating injection-locked frequency multiplier-based phase detector (PG-ILFM PD), wherein the PG-ILFM PD comprises: a replica voltage controlled oscillator (R-VCO) configured to cut off the power supply of the R-VCO repeatedly based on a reference signal S.sub.REF; and a fundamental sampling phase detector (FSPD) configured to receive an output signal S.sub.ILFM of the R-VCO as a reference signal for sampling and detect a phase error of a main voltage controlled oscillator (M-VCO).

2. The phase-locked loop of claim 1, further comprising a M-VCO configured to detect the phase error by feeding a final output signal back to the FSPD of the PG-ILFM PD.

3. The phase-locked loop of claim 1, wherein the R-VCO has a structure identical with a structure of the M-VCO and is used to multiply a frequency of the reference signal S.sub.REF.

4. The phase-locked loop of claim 3, wherein the R-VCO is configured to synchronize a phase of the output signal S.sub.ILFM of the R-VCO with the reference signal S.sub.REF regardless of a frequency multiplication factor by outputting an output signal only while the reference signal S.sub.REF is high.

5. The phase-locked loop of claim 3, wherein: the output signal S.sub.IFLM of the R-VCO and an output signal S.sub.VCO of the M-VCO have an identical frequency band, and phase error information detected in the PG-ILFM PD is outputted without a loss of the phase error information, thereby increasing a phase error detection gain.

6. The phase-locked loop of claim 1, further comprising a resampler configured to perform resampling in order to reduce a spur attributable to an output of meaningless information by the PG-ILFM PD while the reference signal S.sub.REF is low.

7. The phase-locked loop of claim 1, further comprising a frequency offset canceller (FOC) configured to remove a frequency deviation between the R-VCO of the PG-ILFM PD and the M-VCO.

8. The phase-locked loop of claim 7, wherein the FOC is configured to alternately operate at a different phase with respect to a resampling operation for phase locking of the phase-locked loop while the reference signal S.sub.REF is high.

9. The phase-locked loop of claim 8, wherein the FOC is configured to perform resampling for reducing a frequency offset of the R-VCO after the resampling operation for the phase locking.

10. The phase-locked loop of claim 6, further comprising a gm amplifier configured to adjust a control voltage of the M-VCO by generating a current proportional to an output signal of the resampler.

11. An operating method of a phase-locked loop comprising a power-gating injection-locked frequency multiplier-based phase detector (PG-ILFM PD), the operating method comprising: outputting, by a replica voltage controlled oscillator (R-VCO) of the PG-ILFM PD, an output signal S.sub.ILFM by repeating a supply and blocking of an input signal based on a reference signal S.sub.REF; and receiving, by a fundamental sampling phase detector (FSPD) of the PG-ILFM PD, the output signal S.sub.ILFM of the R-VCO as a reference signal for sampling and detecting a phase error of a main voltage controlled oscillator (M-VCO).

12. The operating method of claim 11, wherein outputting, by the R-VCO of the PG-ILFM PD, the output signal S.sub.ILFM comprises using the R-VCO having a structure identical with a structure of the M-VCO in order to multiply a frequency of the reference signal S.sub.REF.

13. The operating method of claim 11, further comprising receiving, by the FSPD of the PG-ILFM PD, a final output signal of the M-VCO through feedback in order to detect a phase error.

14. The operating method of claim 12, wherein the R-VCO is configured to synchronize a phase of the output signal S.sub.ILFM of the R-VCO with the reference signal S.sub.REF regardless of a frequency multiplication factor by outputting an output signal only while the reference signal S.sub.REF is high.

15. The operating method of claim 12, wherein: the output signal S.sub.IFLM of the R-VCO and an output signal S.sub.VCO of the M-VCO have an identical frequency band, and phase error information detected in the PG-ILFM PD is outputted without a loss of the phase error information, thereby increasing a phase error detection gain.

16. The operating method of claim 11, further comprising performing, by a resampler, resampling in order to reduce a spur attributable to an output of meaningless information by the PG-ILFM PD while the reference signal S.sub.REF is low.

17. The operating method of claim 11, further comprising removing, by a frequency offset canceller (FOC), a frequency deviation between the R-VCO of the PG-ILFM PD and the M-VCO.

18. The operating method of claim 17, wherein removing, by the FOC, the frequency deviation between the R-VCO of the PG-ILFM PD and the M-VCO comprises alternately operating at a different phase with respect to a resampling operation for phase locking of the phase-locked loop while the reference signal S.sub.REF is high.

19. The operating method of claim 18, wherein resampling for reducing the frequency offset of the R-VCO is performed after the resampling operation for the phase locking.

20. The operating method of claim 16, further comprising adjusting, by a gm amplifier, a control voltage of the M-VCO by generating a current proportional to an output signal of the resampler.

Description

DESCRIPTION OF THE DRAWINGS

[0031] The foregoing aspects and many of the attendant advantages of this disclosure will become more readily appreciated as the same become better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:

[0032] FIG. 1 is a diagram illustrating output phase noise according to a bandwidth of a PLL according to a conventional technology.

[0033] FIG. 2 is a diagram illustrating a phase frequency detector (PFD) according to a bandwidth of a charge-pump PLL according to a conventional technology and a sub-sampling PD (SSPD) and gm noise according to a bandwidth of a PLL in a jitter and sub-sampling PLL (SSPLL) of a charge pump.

[0034] FIG. 3 is a diagram for describing an operation when the SSPLL according to a conventional technology operates in the W-band.

[0035] FIG. 4 is the entire circuit diagram of an ultra-low jitter low-power PLL using a power-gating injection-locked frequency multiplier-based phase detector (PG-ILFM PD) according to an embodiment of the present disclosure.

[0036] FIG. 5 is a diagram for describing a fundamental sampling phase detector (FSPD) according to a conventional technology.

[0037] FIG. 6 is a diagram for describing a method of generating a reference signal according to an embodiment of the present disclosure.

[0038] FIG. 7 is a diagram for describing the PG-ILFM PD according to an embodiment of the present disclosure.

[0039] FIG. 8 illustrates simulation results of a phase error detection gain of the PG-ILFM PD according to an embodiment of the present disclosure.

[0040] FIG. 9 is a flowchart for describing an operating method of an ultra-low jitter low-power PLL using a phase detector based on the PG-ILFM according to an embodiment of the present disclosure.

[0041] FIGS. 10(a), 10(b), 10(c), and 10(d) are diagrams for describing a major operation process of the PLL according to an embodiment of the present disclosure.

[0042] FIGS. 11(a), 11(b), and 11(c) are diagrams for describing an operating process of a frequency offset canceller according to an embodiment of the present disclosure.

DETAILED DESCRIPTION

[0043] While illustrative embodiments have been illustrated and described, it will be appreciated that various changes can be made therein without departing from the spirit and scope of the disclosure.

[0044] The present disclosure proposes a phase-locked loop (PLL) based on a power-gating injection-locked frequency multiplier (PG-ILFM)-based new phase detector (PD) (PG-ILFM PD) in order to generate an ultra-low jitter W-band signal. The proposed PG-ILFM PD is based on high phase noise detection performance, and can significantly reduce noise in a phase detector (PD), a charge pump (CP), a loop filter (LF), etc. within a PLL bandwidth. Accordingly, a PLL bandwidth (BW) can be expanded regardless of in-band noise, and can resultantly significantly reduce noise of a voltage-controlled oscillator (VCO) having a low Q-factor of a W-band. In the present disclosure, a W-band PLL using the proposed PG-ILFM PD can have ultra-low noise performance of 100 fs or less in the corresponding frequency band based on such a technical background. Hereinafter, embodiments of the present disclosure are described in detail with reference to the accompanying drawings.

[0045] FIG. 4 is the entire circuit diagram of an ultra-low jitter low-power PLL using a power-gating injection-locked frequency multiplier-based phase detector (PG-ILFM PD) according to an embodiment of the present disclosure.

[0046] The ultra-low jitter low-power PLL using the proposed PG-ILFM PD include a PG-ILFM PD 410, a resampler (RS) 420, a frequency offset canceller (FOC) 430, a gm amplifier 440, a loop filter (LF) 450, and a main voltage controlled oscillator (M-VCO) 460.

[0047] The PG-ILFM PD 410 according to an embodiment of the present disclosure is a power-gating injection-locked frequency multiplier-based phase detector, and includes a replica voltage controlled oscillator (R-VCO) 411 and a fundamental sampling phase detector (FSPD) 412.

[0048] The R-VCO 411 according to an embodiment of the present disclosure repeats the supply and blocking of an input signal based on a reference signal S.sub.REF.

[0049] The FSPD 412 according to an embodiment of the present disclosure receives an output signal S.sub.ILFM of the R-VCO 411 as a reference signal for sampling, and detects a phase error of the M-VCO 460.

[0050] The M-VCO 460 according to an embodiment of the present disclosure feeds the final output signal back to the FSPD 412 of the PG-ILFM PD 410 so that a phase error is detected.

[0051] The R-VCO 411 according to an embodiment of the present disclosure has the same structure as the M-VCO 460, and is used to multiply the frequency of the reference signal S.sub.REF.

[0052] The R-VCO 411 according to an embodiment of the present disclosure synchronizes the phase of the output signal S.sub.ILFM of the R-VCO 411 with the reference signal S.sub.REF regardless of a frequency multiplier by outputting an output signal only while the reference signal S.sub.REF is high.

[0053] The output signal S.sub.ILFM of the R-VCO 411 and the output signal S.sub.VCO of the M-VCO 460 according to an embodiment of the present disclosure have the same frequency band. Accordingly, a phase error detection gain can be increased because phase error information detected by the PG-ILFM PD 410 is output without a loss of the phase error information.

[0054] The resampler 420 according to an embodiment of the present disclosure performs resampling in order to reduce a spur attributable to the output of meaningless information of the PG-ILFM PD 410 while the reference signal S.sub.REF is low.

[0055] The FOC 430 according to an embodiment of the present disclosure removes a frequency deviation between the R-VCO 411 of the PG-ILFM PD 410 and the M-VCO 460.

[0056] The FOC 430 according to an embodiment of the present disclosure alternately operates at a different phase with respect to a resampling operation for the phase locking of a PLL while the reference signal S.sub.REF is high. In other words, after the resampling operation for the phase locking, the FOC 430 performs resampling for reducing a frequency offset of the R-VCO 411.

[0057] The gm amplifier 440 according to an embodiment of the present disclosure adjusts a control voltage of the M-VCO 460 by generating a current proportional to the output signal of the resampler 420.

[0058] The loop filter (LF) 450 according to an embodiment of the present disclosure may transmit only a frequency signal having a cutoff frequency or less by attenuating a signal having a frequency equal to or higher than a specific cutoff frequency of a signal output by the gm amplifier 440.

[0059] The elements of the ultra-low jitter low-power PLL using the PG-ILFM PD according to an embodiment of the present disclosure are more specifically described with reference to FIGS. 5 to 8.

[0060] FIG. 5 is a diagram for describing a fundamental sampling phase detector (FSPD) according to a conventional technology.

[0061] FIG. 5(a) is a circuit diagram of the FSPD according to a conventional technology. FIG. 5(b) is a timing diagram of an FSPD operation according to a conventional technology. FIG. 5(c) is a diagram for describing frequency characteristics of the FSPD operation according to a conventional technology.

[0062] As described above, in order to form an ultra-low jitter W-band PLL, a phase error detection gain is important. Accordingly, in the present disclosure, the concept of the FSPD which may have a high phase error detection gain even in the W-band is applied.

[0063] In general, in the FSPD according to a conventional technology, a frequency of the reference signal S.sub.REF for sampling a phase error of the output signal S.sub.VCO of the VCO is the same as the frequency band of the VCO.

[0064] In such an operation of the FSPD, as in FIG. 5(b), the reference signal S.sub.REF continuously samples only a specific voltage value of the output signal S.sub.VCO. Any loss of a phase error detection gain does not occur by a pole generated in the FSPD.

[0065] It may be interpreted that a phase error of the output signal S.sub.VCO is down-converted without any change without being attenuated by the pole in a frequency region as in FIG. 5(c). This may have an effect, such as an effect in that two signals of the same frequency band are mixed.

[0066] However, it is difficult to generate a reference signal that practically has very low jitter and also has a high frequency of 100 GHz. In contrast, such a reference signal does not need to be a continuous signal because the signal is used to only detect a phase error of a PLL output unit. Accordingly, the present disclosure proposes a PG-ILFM PD including an R-VCO and an FSPD in order to improve the problems by using such a characteristic.

[0067] FIG. 6 is a diagram for describing a method of generating a reference signal according to an embodiment of the present disclosure.

[0068] FIG. 6(a) is a diagram for describing an injection locked frequency multiplier (ILFM) according to a conventional technology. FIG. 6(b) is a diagram for describing a PG-ILFM structure applied to the present disclosure.

[0069] In the present disclosure, the PG-ILFM structure is applied as a method of generating a reference signal for solving the problems described in FIG. 5, as in FIG. 6(b).

[0070] The ILFM illustrated in FIG. 6(a) according to a conventional technology is a method of injecting a short pulse into a VCO output unit having a continuous output signal, and has a disadvantage in that performance is deteriorated as a frequency multiplier becomes higher.

[0071] In contrast, the PG-ILFM method illustrated in FIG. 6(b) and applied to the present disclosure is a method of repeatedly turning on/off power of a VCO based on a reference signal. In this method, the phase of the output signal S.sub.ILFM of the VCO can be perfectly synchronized with the reference signal SPG regardless of an output frequency and a frequency multiplier thereof.

[0072] As described above, the proposed method itself cannot be disposed at the output stage of a signal generator because it has a discontinuous output signal, but is an optimal structure to be used as a reference signal of 100 GHz.

[0073] FIG. 7 is a diagram for describing a PG-ILFM PD according to an embodiment of the present disclosure.

[0074] FIG. 7(a) is a circuit diagram of the PG-ILFM PD according to an embodiment of the present disclosure. FIG. 7(b) is a timing diagram of an operation of the PG-ILFM PD.

[0075] As described above, the PG-ILFM PD according to an embodiment of the present disclosure includes an R-VCO 710 and an FSPD 720.

[0076] The R-VCO 710 according to an embodiment of the present disclosure repeats the supply and blocking of an input signal based on the reference signal S.sub.REF.

[0077] The FSPD 720 according to an embodiment of the present disclosure receives the output signal S.sub.ILFM of the R-VCO 710 as a reference signal for sampling, and detects a phase error of an M-VCO.

[0078] The M-VCO according to an embodiment of the present disclosure feeds back the final output signal of the FSPD 720 of the PG-ILFM PD so that the FSPD 720 detects a phase error of the M-VCO.

[0079] The R-VCO 710 according to an embodiment of the present disclosure has the same structure as the M-VCO and is used to multiply the frequency of the reference signal S.sub.REF.

[0080] The R-VCO 710 according to an embodiment of the present disclosure outputs the output signal only while the reference signal S.sub.REF is high (Φ.sub.1). While the reference signal S.sub.REF is high (Φ.sub.1), the output signal S.sub.ILFM of the R-VCO 710 samples the phase error of the M-VCO through the FSPD 720. Accordingly, the phase of the output signal S.sub.ILFM of the R-VCO 710 can be synchronized with the reference signal S.sub.REF regardless of a frequency multiplication factor.

[0081] The output signal S.sub.ILFM of the R-VCO 710 and the output signal S.sub.VCO of the M-VCO according to an embodiment of the present disclosure have the same frequency band. Accordingly, a phase error detection gain can be increased because phase error information detected by the PG-ILFM PD is output without a loss of the phase error information.

[0082] FIG. 8 illustrates simulation results of a phase error detection gain of the PG-ILFM PD according to an embodiment of the present disclosure.

[0083] FIG. 8(a) is a circuit diagram of an SSPD according to a conventional technology. FIG. 8(b) is a circuit diagram of the proposed PG-ILFM PD. FIG. 8(c) is a graph for comparing simulation results of the proposed PG-ILFM PD with those of the SSPD.

[0084] Referring to FIG. 8(c), it may be seen, from the simulation results of the SSPD according to a conventional technology and the simulation results of the proposed PG-ILFM PD, that the proposed PG-ILFM PD has a phase error detection gain that is 10 times or more higher than that according to a conventional technology.

[0085] FIG. 9 is a flowchart for describing an operating method of the ultra-low jitter low-power PLL using a PG-ILFM PD according to an embodiment of the present disclosure.

[0086] An operating method of the ultra-low jitter low-power PLL using a PG-ILFM PD including the PG-ILFM PD, the resampler, the FOC, the gm amplifier, the loop filter, and the M-VCO according to an embodiment of the present disclosure includes step 910 of outputting, by the R-VCO of the PG-ILFM PD, the output signal S.sub.ILFM by repeating the supply and blocking of an input signal based on the reference signal S.sub.REF, step 920 of receiving, by the FSPD of the PG-ILFM PD, the output signal S.sub.ILFM of the R-VCO as a reference signal for sampling and detecting a phase error of the M-VCO, step 930 of performing, by the resampler, resampling in order to reduce a spur attributable to the output of meaningless information by the PG-ILFM PD while the reference signal S.sub.REF is low, step 940 of removing, by the FOC, a frequency deviation between the R-VCO of the PG-ILFM PD and the M-VCO, step 950 of adjusting, by the gm amplifier, a control voltage of the M-VCO by generating a current proportional to the output signal of the resampler, and step 960 of receiving, by the FSPD of the PG-ILFM PD, the final output signal of the M-VCO through feedback in order to detect a phase error.

[0087] The PG-ILFM PD according to an embodiment of the present disclosure is a power-gating injection-locked frequency multiplier-based phase detector, and includes the replica voltage controlled oscillator (R-VCO) and the fundamental sampling phase detector (FSPD).

[0088] In step 910, the R-VCO of the PG-ILFM PD outputs the output signal S.sub.ILFM by repeating the supply and blocking of an input signal based on the reference signal S.sub.REF.

[0089] The R-VCO according to an embodiment of the present disclosure has the same structure as the M-VCO, and is used to multiply the frequency of the reference signal S.sub.REF.

[0090] The R-VCO according to an embodiment of the present disclosure synchronizes the phase of the output signal S.sub.ILFM of the R-VCO with the reference signal S.sub.REF regardless of a frequency multiplication factor by outputting an output signal only while the reference signal S.sub.REF is high.

[0091] The output signal S.sub.ILFM of the R-VCO and the output signal S.sub.VCO of the M-VCO according to an embodiment of the present disclosure have the same frequency band. Accordingly, a phase error detection gain can be increased because phase error information detected by the PG-ILFM PD is output without a loss of the phase error information.

[0092] In step 920, the FSPD of the PG-ILFM PD receives the output signal S.sub.ILFM of the R-VCO as a reference signal for sampling and detects a phase error of the M-VCO.

[0093] In step 930, the resampler performs resampling in order to reduce a spur attributable to the output of meaningless information by the PG-ILFM PD while the reference signal S.sub.REF is low.

[0094] In step 940, the FOC removes a frequency deviation between the R-VCO of the PG-ILFM PD and the M-VCO.

[0095] The FOC according to an embodiment of the present disclosure alternately operates at a different phase with respect to a resampling operation for the phase locking of a PLL while the reference signal S.sub.REF is high. In other words, after the resampling operation for the phase locking, the FOC 430 performs resampling for reducing a frequency offset of the R-VCO.

[0096] In step 950, the gm amplifier adjusts a control voltage of the M-VCO by generating a current proportional to the output signal of the resampler. The loop filter according to an embodiment of the present disclosure may transmit only a frequency signal having a cutoff frequency or less by attenuating a signal having a frequency equal to or higher than a specific cutoff frequency of a signal output by the gm amplifier.

[0097] In step 960, the final output signal of the M-VCO is feed back to the FSPD of the PG-ILFM PD so that the FSPD of the PG-ILFM PD detects a phase error.

[0098] FIGS. 10(a), 10(b), 10(c), and 10(d) are diagrams for describing a major operation process of the PLL according to an embodiment of the present disclosure.

[0099] FIG. 10(a) illustrates a circuit path of a major operation of the PLL according to an embodiment of the present disclosure. FIG. 10(b) is a timing diagram of the PG-ILFM PD during the major operation of the PLL. FIG. 10(c) is a timing diagram of resampling during the major operation of the PLL. FIG. 10(d) is the entire timing diagram of the major operation of the PLL.

[0100] Arrows in FIG. 10(a) illustrate directions in which the major operation of the PLL for removing a phase error of the PLL output unit is performed.

[0101] First, referring to FIG. 10(b), the PG-ILFM PD samples the output signal S.sub.VCO of the M-VCO as the low jitter signal S.sub.ILFM. Accordingly, phase error information of the output signal Svco of the M-VCO is directly delivered as the input signal SPD of the resampler (RS).

[0102] However, in this case, since the PG-ILFM PD is turned off while Φ.sub.2, the input signal S.sub.PD of the resampler has meaningless information, so that a spur may be caused. Accordingly, as in FIG. 10(c), the resampler selects only an interval in which the input signal S.sub.PD has meaningful information and delivers the corresponding input signal S.sub.PD as the output signal S.sub.RS of the resampler.

[0103] Referring to FIG. 10(d), if a phase error of S.sub.OUT is not 0 and the phase of the low jitter signal S.sub.ILFM is ahead of an output signal S.sub.OUT (i.e., the output signal S.sub.VCO of the M-VCO), the input signal S.sub.PD samples a voltage lower than an ideal phase locking point.

[0104] Such a voltage of the input signal S.sub.PD is delivered as S.sub.RSI during a window signal S.sub.WIN1. Accordingly, the gm amplifier adjusts a phase error of the PLL by generating a current proportional to a value of S.sub.RS1 in a way that a control voltage V.sub.C_PLL of the M-VCO eliminates the phase error of the PLL.

[0105] In contrast, if the phase error of S.sub.OUT is 0, S.sub.OUT is locked to the low jitter signal S.sub.ILFM and a center phase, and a value of the control voltage is maintained without any change.

[0106] FIGS. 11(a), 11(b), and 11(c) are diagrams for describing an operating process of a frequency offset canceller according to an embodiment of the present disclosure.

[0107] FIG. 11(a) illustrates a circuit path of an operation of the FOC according to an embodiment of the present disclosure. FIG. 11(b) is a timing diagram of resampling during the operation of the FOC. FIG. 11(c) is the entire timing diagram of the operation of the FOC.

[0108] Arrows in FIG. 11(a) illustrate the directions of the operation of the FOC for eliminating a frequency deviation between the R-VCO of the PG-ILFM PD and the M-VCO according to an embodiment of the present disclosure.

[0109] The operation of the FOC according to an embodiment of the present disclosure performs an auxiliary role so that the PLL can stably achieve ultra-low noise performance even in a process, voltage, and tempreature(PVT) change. The proposed PLL and FOC alternately operate at different locations during the phase (Φ.sub.1).

[0110] For the operation of the FOC according to an embodiment of the present disclosure, separately from the main path of the PLL, the FOC further includes another resampler as in FIG. 11(a). The resampler of the FOC according to an embodiment of the present disclosure resamples a value of the input signal S.sub.PD at the location of a window signal S.sub.WIN2. Such a window signal S.sub.WIN2 is also generated by the reference signal S.sub.REF, and a location thereof is behind the window signal S.sub.WIN1. Referring to FIG. 11(b), the resampler of the proposed FOC samples, from the window signal S.sub.WIN2, a frequency offset of the R-VCO present in the PG-ILFM PD, and delivers a corresponding signal as S.sub.RS2.

[0111] FIG. 11(c) illustrates an ideal operation of the proposed FOC. It may be assumed that the PLL has already been locked during an operation of the FOC because a bandwidth of the proposed PLL is much wider than a bandwidth of the FOC.

[0112] In other words, it may be assumed that an output signal S.sub.OUT has been accurately locked to the phase of the output signal S.sub.ILFM during the window signal S.sub.WIN1. At this time, it may be seen that when a frequency offset is present in the R-VCO (Case 1 in FIG. 11(c)), the phase of the output signal S.sub.ILFM gradually becomes distant from an ideal point. As a result, such a frequency offset appears as a difference between the phases of the output signal S.sub.ILFM and the output signal S.sub.OUT during the window signal S.sub.WIN2. Accordingly, the frequency offset can be removed by sampling a value of the input signal S.sub.PD in the portion of the window signal S.sub.WIN2, delivering a corresponding signal as S.sub.RS2, and thus adjusting a control voltage of the R-VCO.

[0113] Through the ultra-low jitter low-power PLL using the PG-ILFM PD according to embodiments of the present disclosure, a high phase error detection gain can be achieved, phase noise within the bandwidth of the PLL can be significantly reduced, and the bandwidth of the PLL can be expanded to the extent that phase noise of the W-band VCO can be sufficiently reduced due to the reduced phase noise within the bandwidth. As a result, ultra-low noise performance can be achieved, and the ultra-low jitter low-power PLL can be used as a local oscillator for generating a carrier wave of a transceiver stage for 6G communication. Furthermore, the ultra-low jitter low-power PLL has a high degree of integration because it is fabricated using a CMOS process compared to an SiGe or InP process frequently used in the existing THz frequency band, and can be implemented with low power because the ultra-low jitter low-power PLL is a frequency multiplier that does not use a frequency divider.

[0114] As described above, although the embodiments have been described in connection with the limited embodiments and the drawings, those skilled in the art may modify and change the embodiments in various ways from the description. For example, proper results may be achieved although the aforementioned descriptions are performed in order different from that of the described method and/or the aforementioned elements, such as the system, configuration, device, and circuit, are coupled or combined in a form different from that of the described method or replaced or substituted with other elements or equivalents.

[0115] Accordingly, other implementations, other embodiments, and the equivalents of the claims fall within the scope of the claims.