A GRAPHENE/GRAPHENE OXIDE DIODE AND A METHOD OF FORMING THE SAME
20240047551 ยท 2024-02-08
Assignee
Inventors
Cpc classification
International classification
H01L29/66
ELECTRICITY
H01L29/16
ELECTRICITY
Abstract
The present invention provides method for forming a diode, the method comprises providing a first graphene layer structure on a first substrate; providing a second graphene layer structure on a second substrate; treating the first graphene layer structure with an oxidant to form a graphene oxide surface thereon; and aligning the second graphene layer structure against the graphene oxide surface of the first graphene layer structure.
Claims
1. A method for forming a diode, the method comprising: providing a first graphene layer structure on a first substrate; providing a second graphene layer structure on a second substrate; treating the first graphene layer structure with an oxidant to form a graphene oxide surface thereon; and aligning the second graphene layer structure against the graphene oxide surface of the first graphene layer structure.
2. The method according to claim 1, wherein the first and second graphene layer structures are retained together mechanically and/or with an intervening adhesive.
3. The method according to claim 1, wherein at least one of the first graphene layer structure and the first substrate, and at least one of the second graphene layer structure and the second substrate, are provided with one or more electrical contacts for connecting the diode to an electrical circuit.
4. The method according to claim 1, wherein the oxidant is an oxidising solution.
5. The method according to claim 1, wherein the first and second graphene layers are provided on the first and second substrates respectively by MOCVD.
6. The method according to claim 1, wherein the method further comprises processing the aligned first and second graphene layer structures to form a plurality of diodes.
7. The method according to claim 1, wherein the first and/or second substrate is selected from silicon, silicon carbide, silicon dioxide, silicon nitride, sapphire and a III-V semiconductor.
8. A diode obtainable by the method according to claim 1, the diode comprising: a first graphene layer structure on a first substrate, the first graphene layer structure having a graphene oxide surface; a second graphene layer structure on a second substrate; wherein the surface of the second graphene layer structure is aligned against and in contact with the graphene oxide surface of the first graphene layer structure.
9. The diode of claim 8, wherein at least one of the first graphene layer structure and the first substrate, and at least one of the second graphene layer structure and the second substrate, have one or more electrical contacts for connecting the diode to an electrical circuit.
10. An electrical circuit comprising the diode of claim 9, wherein the circuit comprises electrical wires attached to the electrical contacts.
11. The method according to claim 1, wherein the first and/or second graphene layer structures are provided on the first and second substrates respectively by liquid exfoliation, solid exfoliation, oxidation-exfoliation-reduction or intercalation-exfoliation.
12. The method according to claim 4, wherein the oxidising solution comprises sulphuric acid, potassium permanganate and sodium nitrate.
Description
FIGURES
[0042] The present invention will now be described further with reference to the following non-limiting Figures, in which:
[0043]
[0044]
[0045]
[0046]
[0047] The graphene oxide surface 20 is in contact with the first graphene layer structure 5. The graphene oxide surface 20 may be held in contact with the first graphene layer structure 5 by an adhesive (not shown).
[0048] Electrical contacts 30 are provided on the first and second graphene layer structures 5, 15. These are connected to electrical traces 35 for connection with a broader electrical circuit (not shown).
[0049] An inert polymer coating 40 is applied around the diode structure to insulate and provide structural integrity to the diode 1.
EXAMPLES
Example 1
[0050] A graphene layer structure is provided on a sapphire wafer. The graphene coated sapphire wafer is cut into pieces no smaller than 2 mm by 5 mm. The aspect ratio of the cut wafers should be such that electrical contacts can be placed onto the wafer whilst also allowing clamping to an equally sized wafer with electrical contacts without the electrical contacts of the two wafers touching.
[0051] Next, 15 mL of sulphuric acid are measured into a beaker followed by 0.06 g of sodium nitrate which is then stirred for 5 minutes. Then, 0.36 g of potassium permanganate (KMnO.sub.4) is added to the mixture and stirred for 5 minutes.
[0052] 2 mL of this mixture is decanted into a vial to which a further 2 mL of sulphuric acid is added before stirring for 1 minute. A cut wafer is then submerged in the solution for 10 seconds. The wafer is removed, rinsed with 2 portions of deionised water and allowed to dry under a nitrogen flow.
[0053] An electrical contact is painted using a conductive silver paint onto the corner of a dried wafer which is then allowed to dry for 10 minutes. The same process is carried out on an untreated wafer.
[0054] The graphene surface of the untreated graphene coated sapphire wafer is aligned and clamped with a clip to the graphene oxide surface of the treated wafer. The alignment is such that the silver electrical contacts are not touching one another and carried with minimal lateral forces applied to the graphene layers which may otherwise shear them off.
[0055] Electrical wires are attached to the electrical contacts for a connection into an electrical circuit and the diode's properties ascertained.
[0056] As used herein, the singular form of a, an and the include plural references unless the context clearly dictates otherwise.
[0057] The foregoing detailed description has been provided by way of explanation and illustration, and is not intended to limit the scope of the appended claims. Many variations in the presently preferred embodiments illustrated herein will be apparent to one of ordinary skill in the art, and remain within the scope of the appended claims and their equivalents.