CIRCUIT WITH TWO DIGITAL-TO-ANALOG CONVERTERS AND METHOD OF OPERATING SUCH THE CIRCUIT

Abstract

A circuit 100 is described comprising (i) a first digital-to-analog converter 110, (ii) a second digital-to-analog converter 111, (iii) a plurality of unit elements 120, and (iv) switching circuitry 130. The switching circuitry 130 is adapted so that in a first switching state 231, a set of unit elements 221 of the plurality of unit elements 120 forms part of the first digital-to-analog converter 110, and in a second switching state 232, the set of unit elements 221 forms part of the second digital-to-analog converter 111. Furthermore, a corresponding method of operating a circuit 100 is described.

Claims

1. A circuit comprising a first digital-to-analog converter; a second digital-to-analog converter; a plurality of unit elements; and switching circuitry adapted so that in a first switching state, a set of unit elements of the plurality of unit elements forms part of the first digital-to-analog converter, and in a second switching state, the set of unit elements forms part of the second digital-to-analog converter.

2. The circuit of claim 1, wherein each of the unit elements of the plurality of unit elements comprises at least one electric component.

3. The circuit of claim 1, wherein the circuit is a pipeline converter, wherein the first digital-to-analog converter forms part of a first stage of the pipeline converter and the second digital-to-analog converter forms part of a second stage of the pipeline converter.

4. The circuit of claim 1, wherein a size of the set of unit elements is indicative of a number of bits processed by the first digital-to-analog converter.

5. The circuit of claim 1, further comprising at least one further digital-to-analog converter, wherein the switching circuitry is adapted so that, for each further digital-to-analog converter, the set of unit elements forms part of the further digital-to-analog converter in a respective further switching state of the switching circuitry.

6. The circuit of claim 1, wherein the set of unit elements forming part of the first digital-to-analog converter in the first switching state is selected based on an input value of an input signal received by the first digital-to-analog converter.

7. The circuit of claim 1, wherein the set of unit elements forming part of the first digital-to-analog converter in the first switching state is selected based on a previous set of unit elements, which formed part of the first digital-to analog converter, when a previous input value of a previous input signal was processed by the first digital-to analog converter.

8. The circuit of claim 1, wherein the switching circuitry is adapted so that, in the first switching state, a further set of unit elements forms part of the second digital-to-analog converter, wherein the set of unit elements and the further set of unit elements are selected such that a first average gain error of the first digital-to-analog converter equals a second average gain error of the second digital-to-analog converter.

9. The circuit of claim 1, wherein subsequent sets of unit elements forming part of the first digital-to-analog converter when subsequent input signals having respective subsequent input values are received by the first digital-to-analog converter, are selected so that respective subsequent deviations from an average error compensate each other.

10. The circuit of claim 1, wherein subsequent sets of unit elements forming part of the first digital-to-analog converter, when subsequent input signals having respective subsequent input values are received by the first digital-to-analog converter are selected to noise shape the gain error of the first digital-to-analog converter.

11. The circuit of claim 1, wherein subsequent further sets of unit elements forming part of the second digital-to-analog converter, when subsequent further input signals having respective subsequent further input values are received by the second digital-to-analog converter, are selected randomly.

12. The circuit of claim 1, wherein the switching circuitry is configured to electrically connect the set of unit elements to the first digital-to-analog converter in a predetermined order, wherein the order is changed for subsequent input signals.

13. The circuit of claim 1, further comprising a control device configured to operate the switching circuitry.

14. A method of operating a circuit, which comprises a plurality of digital-to-analog converters, a plurality of unit elements and switching circuitry, wherein the method comprises the steps of: setting the switching circuitry to a first switching state so that a set of unit elements of the plurality of unit elements forms part of a first digital-to-analog converter of the plurality of digital-to-analog converters; and setting the switching circuitry to the second switching state so that the set of unit elements forms part of a second digital-to-analog converter of the plurality of digital-to-analog converters.

15. The method of claim 14, wherein each of the unit elements of the plurality of unit elements comprises at least one electric component.

16. The method of claim 14, wherein a size of the set of unit elements is indicative of a number of bits processed by the first digital-to-analog converter.

17. The method of claim 14, wherein the set of unit elements forming part of the first digital-to-analog converter in the first switching state is selected based on an input value of an input signal received by the first digital-to-analog converter.

18. The method of claim 14, wherein the set of unit elements forming part of the first digital-to-analog converter in the first switching state is selected based on a previous set of unit elements, which formed part of the first digital-to analog converter, when a previous input value of a previous input signal was processed by the first digital-to analog converter.

19. The method of claim 14, wherein the switching circuitry is adapted so that, in the first switching state, a further set of unit elements forms part of the second digital-to-analog converter, wherein the set of unit elements and the further set of unit elements are selected such that a first average gain error of the first digital-to-analog converter equals a second average gain error of the second digital-to-analog converter.

20. The method of claim 14, wherein subsequent sets of unit elements forming part of the first digital-to-analog converter, when subsequent input signals having respective subsequent input values are received by the first digital-to-analog converter, are selected so that respective subsequent deviations from an average error compensate each other.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0052] FIG. 1 shows a circuit comprising two digital-to-analog converters according to an exemplary embodiment of the present disclosure.

[0053] FIGS. 2 and 3 show an algorithm for selecting subsequent sets of unit elements for a first digital-to-analog converter and a second digital-to-analog converter, respectively, according to an exemplary embodiment of the present disclosure.

[0054] FIGS. 4 and 5 in combination show an algorithm for selecting subsequent sets of unit elements for a first digital-to-analog converter according to an exemplary embodiment of the present disclosure.

[0055] FIGS. 6 and 7 show, for comparison, the output spectrum of a pipeline converter with ideal DACs and input signals of 10 MHz and 380 MHz, respectively.

[0056] FIGS. 8 and 9 show, for comparison, the output spectrum of a pipeline converter with DACs exhibiting unit element mismatch, an input signal of 10 MHz and with no or with a conventional data weight algorithm procedure, respectively.

[0057] FIGS. 10 and 11 show, for comparison, the output spectrum of a pipeline converter with DACs exhibiting unit element mismatch, an input signal of 380 MHz and with no or with a conventional data weight algorithm procedure, respectively.

[0058] FIGS. 12 and 13 show the output spectrum of a pipeline converter with DACs exhibiting unit element mismatch, input signals of 10 MHz and 380 MHz, respectively, and with a data weight algorithm according to an exemplary embodiment of the present disclosure.

[0059] FIG. 14 shows a harmonic distortion (HDx) of an output signal depending on an amount of mismatch between unit elements according to exemplary embodiments of the present disclosure.

[0060] FIG. 15 shows a spurious free dynamic range (SFDR) of an output signal depending on an amount of mismatch between unit elements according to exemplary embodiments of the present disclosure.

[0061] FIG. 16 shows a signal-to-noise ratio (SNR) of an output signal depending on an amount of mismatch between unit elements according to exemplary embodiments of the present disclosure.

[0062] The illustrations in the drawings are schematic. In different drawings, similar or identical elements may be provided with the same reference signs.

DESCRIPTION OF THE DRAWINGS

[0063] FIG. 1 shows a circuit 100 comprising a plurality of digital-to-analog converters 110, 111, 112. Specifically, the circuit 100 comprises a first digital-to-analog converter 110, a second digital-to-analog converter 111, a plurality of unit elements 120, and switching circuitry 130. The switching circuitry is adapted so that in a first switching state 231, a set of unit elements 221 of the plurality of unit elements 120 forms part of the first digital-to-analog converter 110, and in a second switching state 232, the set of unit elements 221 forms part of the second digital-to-analog converter 111. To this effect, the switching circuitry 130 is coupled to the first and second digital-to-analog converters 110, 111. The circuit 100 also comprises further digital-to-analog converters 112, which are also coupled with the switching circuitry 130. The switching circuitry is controlled by control device 140.

[0064] The circuit 100 shown in FIG. 1 is a continuous time pipeline converter 100 having several front-end stages 101, 102, 103 and a back-end stage 104. Each of the first front-end stage 101, the second front-end stage 102 and the further front-end stages 103 comprise a respective digital-to-analog converter 110, 111, 112. The continuous time pipeline converter 100, which is an analog-to-digital converter, receives an overall input signal 115 or a sequence of overall input signals 115 corresponding to respective first stage input signals 105, second stage input signals 106 as well as overall output signals 116. The first stage input signal 105 is converted by a first analog-to-digital converter to an input signal 113 of the first DAC 110. The second stage input signal 106 is converted by a second analog-to-digital converter to a further input signal 114.

[0065] FIG. 1 shows the architecture of a continuous time pipeline converter 100. Each stage 101, 102, 103 consists of a digital to analogue converter (DAC) 110, 111, 112 that generates an analogue output based on the digital input generated by the preceding ADC. The output of the DAC 110, 111, 112 is subtracted from a delayed version of the overall input signal V.sub.in (t) to generate a residue signal. The analogue input signal 105 is delayed by means of continuous time all-pass filter (APF), where the delay provided by the filter matches the delay in the ADC-DAC path. The residue signal (ADC quantization noise, non-linearity and sampling images) is further filtered (LPF) and amplified (G) before it is relayed to the subsequent stages 102, 103, where the same operation is repeated. Finally, the output of the last stage 103 is digitized by a SAR ADC and the final output Y.sub.out is obtained by combining the digital output of each stage 101, 102, 103, 104 in digital compensation filters H.sub.k (z). Ideally, the errors related to the front-end ADCs are cancelled.

[0066] FIGS. 2 and 3 show an algorithm for selecting subsequent sets of unit elements 221 for a first digital-to-analog converter 110 and corresponding subsequent further sets of unit elements 322 for a second digital-to-analog converter 111. The sets of unit elements 221 and corresponding further sets of unit elements 322 each comprise three unit elements 120: U.sub.1, U.sub.2, U.sub.3 or U.sub.4, U.sub.5, U.sub.6. When the switching circuitry is in a first switching state 231, a first set of unit elements U.sub.1, U.sub.2, U.sub.3 forms part of the first digital-to-analog converter 110 and a second set of unit elements U.sub.4, U.sub.5, U.sub.6 forms part of the second digital-to-analog converter 111. When the switching circuitry is in a second switching state 232, the second set of unit elements forms part of the first digital-to-analog converter 110 and the first set of unit elements forms part of the second digital-to-analog converter 111. In the illustrated example, the respective sets of unit elements are selected independently of an input value 217 of an input signal of the first digital-to-analog converter 110 and independently of a further input value 318 of a further input signal of the second digital-to-analog converter 111.

[0067] A first pointer 323 associated with the first DAC 110 and a second pointer 324 also associated with the first DAC 110 memorize a previous usage by the first DAC 110 of unit elements 120 of the first set of unit elements and of unit elements 120 of the second set of unit elements, respectively. The number of unit elements used for subsequent input signals depends on the respective input value 217 corresponding to the number of unit elements that the pointer advances. For example, the pointer advances by one unit element, if the input value 217 is one, and advances by two unit elements, if the input value 217 is two. Similarly, it advances by zero or three unit elements, if the input value 217 is zero or three, respectively. The second DAC 111 is associated with analogous first and second pointers as shown in FIG. 3.

[0068] In FIGS. 2 and 3, some concepts are illustrated for the sake of simplicity considering only two DACs 110, 111 included in a circuit 100, for example in respective front-end stages of a pipeline converter. The linear gain errors of the DACs leak the quantization errors to the output. Consider that each DAC has a linear gain error e.sub.g, such that the linear gain error of the first DAC is e.sub.g1 and the linear gain error of the second DAC is e.sub.g2, etc. Then, the output is given by:

[00001]$V_{\mathrm{out}}=G^4{V}_{\mathrm{in}}\left(1-e_{g1}+e_{g1}{e}_{g2}-e_{g1}{e}_{g2}{e}_{g3}+e_{g1}+e_{g2}{e}_{g3}{e}_{g4}\right)+G^4{Q}_1\left(-e_{g1}+e_{g2}+e_{g1}{e}_{g2}-e_{g2}{e}_{g3}-e_{g1}{e}_{g2}{e}_{g3}+e_{g2}{e}_{g3}{e}_{g4}+e_{g1}{e}_{g2}{e}_{g3}{e}_{g4}\right)+G^3{Q}_2\left(-e_{g2}+e_{g3}+e_{g2}{e}_{g3}-e_{g3}{e}_{g4}-e_{g2}{e}_{g3}{e}_{g4}\right)+G^2{Q}_3\left(-e_{g3}+e_{g4}+e_{g3}{e}_{g4}\right)+G{Q}_4\left(-e_{g4}\right)+Q_{\mathrm{BE}}$

[0069] G is the inter-stage gain and Q.sub.1,2,3,4 are quantization errors of the front-end stages. Q.sub.BE is the quantization error of the back-end stage. The leakage of the front-end quantization errors can be minimized, if the DAC gain errors of the front-end converter are all equal. Then, the output reduces to:

[00002]$V_{\mathrm{out}}=G^4{V}_{\mathrm{in}}\left(1-e_g+e_g^2-e_g^3+e_g^4\right)+G^4{Q}_1{e}_g^4-G^3{Q}_2{e}_g^3+G^2{Q}_3{e}_g^2-G{Q}_4{e}_g+Q_{\mathrm{BE}}$

[0070] The proposed DWA technique is based on the idea of making the linear gain errors of the DACs equal on average by noise shaping the errors that deviate from the average value. More precisely, our goal is to make the gain error of each coarse DAC, i.e. each DAC of the front-end stages, equal to e.sub.g=(e.sub.g1+e.sub.g2+e.sub.g3+e.sub.g4)/4 and noise shape the errors that deviate from this value (e.sub.g1e.sub.g for the first coarse DAC and e.sub.g2e.sub.g for the second coarse DAC, etc). When these errors are turned into white noise, the SFDR (spurious free dynamic range) and HDx (harmonic distortion) of the converter are improved but at the cost of SNR (signal-to-noise ratio). By contrast, when the errors are noise shaped, the SNR can be improved.

[0071] Consider the DAC element array or unit element array of the front-end DACs, i.e. DAC.sub.array, in the following illustrated for a pipeline converter having four stages each with a resolution of two bits:

TABLE-US-00001 U.sub.1 U.sub.2 U.sub.3 U.sub.4 U.sub.5 U.sub.6 U.sub.7 U.sub.8 U.sub.9 U.sub.10 U.sub.11 U.sub.12 [0072] where, the first row U.sub.1, U.sub.2, U.sub.3 represents the elements of the first DAC and the second row U.sub.4, U.sub.5, U.sub.6 represents the elements of the second DAC, etc. The DAC output of the first stage is built up by using the first K unit elements that appear in the first row and the DAC output of the second stage is built up by using the first K unit elements that appear in the second row, etc. For example, if the input of the first stage is 1 then element U.sub.1 is used and if the input of the third stage is 2, then elements U.sub.7 and U.sub.8 are used.

[0073] A DWA technique of an exemplary embodiment works as follows: Firstly, the rows of the DAC.sub.array will be swapped in a specific manner to achieve first order noise shaping of the gain errors. Furthermore, the location of the unit elements in each row will be rearranged to achieve first order noise shaping of the INL errors.

[0074] In the following, firstly, the noise shaping of the INL errors is discussed and then the noise shaping of the gain errors.

[0075] Generally, the INL errors noise shaping of a DAC is done by selecting the elements of the DAC sequentially based on the input and a pointer. Therefore, four pointers are needed, one for each DAC:

p.sub.1(n)=(p.sub.1(n1)+x.sub.1(n1))mod 3

p.sub.2(n)=(p.sub.2(n1)+x.sub.2(n1))mod 3

p.sub.3(n)=(p.sub.3(n1)+x.sub.3(n1))mod 3

p.sub.4(n)=(p.sub.4(n1)+x.sub.4(n1))mod 3

[0076] For the sake of illustration, consider the first two stages only. Basic DWA element selection for the first and second stages is carried out using always the same set of unit elements for each DAC of each stage and a single pointer for each DAC. For example, the set U.sub.1, U.sub.2, U.sub.3 is always used for the first DAC and the set U.sub.4, U.sub.5, U.sub.6 is always used for the second DAC. The respective pointer advances depending on the input value of the respective DAC, e.g. if the input value is 0, 1, 2 or 3 by the same number of unit elements.

[0077] However, in the embodiment illustrated in FIGS. 2 and 3, the DAC output of each stage can be built up by using any row in the DAC.sub.array and therefore, the INL errors that appear at each stage will be different depending on the selected row. In order to maintain the noise shaping, we have to put these errors in a hold state before they can be summed to zero. For example, assume that the first two rows of the DAC.sub.array will be swapped each clock cycle. Then the element selection according to the proposed DWA technique is shown in FIGS. 2 and 3 for the first stage comprising the first DAC 110 and the second stage comprising the second DAC 111, respectively. FIG. 2 shows element selection for the first stage according to the embodiment and FIG. 3 shows element selection for the second stage according to the embodiment.

[0078] An underlying concept is that one has to keep track of all the errors that appear in each stage. As shown in FIG. 2, two different sets of elements appear at the first stage, i.e., elements U.sub.1, U.sub.2 U.sub.3 and elements U.sub.4, U.sub.5, U.sub.6. Therefore, two pointers 323, 324 are needed for each set of element and each pointer 323, 324 has to continue from its last value. This scheme can be further extended to include all four stages. This noise shaping scheme ensures that each set of elements is linearized. This results in residual linear gain errors e.sub.g1, e.sub.g2, e.sub.g3 and e.sub.g4 for each set of elements. Next, with respect to FIGS. 4 and 5, the noise shaping of the gain errors is discussed.

[0079] FIGS. 4 and 5 in combination show an algorithm for selecting subsequent sets of unit elements for a first digital-to-analog converter 110. The algorithm relies on two pointers or finite state machines illustrated in FIGS. 4 and 5, respectively.

[0080] FIG. 4 shows a number of switching states 433: A1, B1, C1, D1, E1, F1, G1, H1, I1, J1, K1, L1. Switching states 433 are chosen based on input values of the first stage or corresponding input values 217 of the first DAC 110 as well as based on arrows between states 433 shown on the left side of FIG. 4. The arrows determine, which subsequent state is chosen based on a previous state as well as on a respective (present) input value 217. For example, if the previous state was A1 and the present input value is 1, then D1 will be selected as (present) state. Each of the states A1, B1, C1, D1, I1, J1, K1, L1 is associated with a respective (gain) error 434. Each of the states E1, F1, G1, H1 is a hold state, for which the second pointer or state machine of FIG. 5 is used to determine the switching state, the set of elements forming part of the first DAC and respective errors.

[0081] Similarly, FIG. 5 shows a number of switching states 433: A2, B2, C2, D2, E2, F2, G2, H2, 12, J2, K2, L2. Switching states 433 are chosen based on input values of the first stage or corresponding input values 217 of the first DAC 110 as well as based on arrows between states 433 shown on the left side of FIG. 5. The arrows determine, which subsequent state is chosen based on a previous state as well as on a respective (present) input value 217. For example, if the previous state was A2 and the present input value is 0, then D2 will be selected as (present) state. Each of the states A2, B2, C2, D2, 12, J2, K2, L2 is associated with a respective (gain) error 434. Each of the states E2, F2, G2, H2 is a hold state, for which the first pointer or state machine of FIG. 4 is used to determine the switching state, the set of elements forming part of the first DAC and respective errors.

[0082] By the algorithm depicted in FIGS. 4 and 5, noise shaping of the gain errors at the first stage is achieved. For the noise shaping of the gain errors, four different options will be discussed in the following: [0083] Option 1: Noise shaping of the gain errors at the first stage. Converting the gain errors at other stages into white noise. [0084] Option 2: Noise shaping of the gain errors at the first and second stages. Converting the gain errors at other stages into white noise. [0085] Option 3: Noise shaping of the gain errors at the first three stages. Converting the gain errors at the last stage into white noise. [0086] Option 4: Noise shaping of the gain errors at all stages.

[0087] In all options listed above, the average gain error of each stage will be made equal to the same value e.sub.g=(e.sub.g1+e.sub.g2+e.sub.g3+e.sub.g4)/4.

[0088] The rows in DAC array are swapped to achieve first order noise shaping of the gain errors. More specifically, the errors are noise shaped that deviate from the common value e.sub.g. When the set of elements U.sub.1, U.sub.2, U.sub.3 is selected for any row, the error is e.sub.g1e.sub.g. when the elements U.sub.4, U.sub.5, U.sub.6 are used in any row, the error is e.sub.g2e.sub.g. Similarly, we have e.sub.g3e.sub.g and e.sub.g4e.sub.g for the set of elements U.sub.7, U.sub.8, U.sub.9 and U.sub.10, U.sub.11, U.sub.12. Based on the selected set of elements and the DAC input, the errors can be written as follows:

y.sub.error[0]=3/4(3e.sub.g1+e.sub.g2+e.sub.g3+e.sub.g4)V.sub.lsb=3E.sub.1

y.sub.error[0]=3/4(e.sub.g13e.sub.g2+e.sub.g3+e.sub.g4)V.sub.lsb=3E.sub.2

y.sub.error[0]=3/4(e.sub.g1+e.sub.g23e.sub.g3+e.sub.g4)V.sub.lsb=3E.sub.3

y.sub.error[0]=3/4(e.sub.g1+e.sub.g2+e.sub.g33e.sub.g4)V.sub.lsb=3E.sub.4

y.sub.error[1]=1/4(3e.sub.g1+e.sub.g2+e.sub.g3+e.sub.g4)V.sub.lsb=E.sub.1

y.sub.error[1]=1/4(e.sub.g13e.sub.g2+e.sub.g3+e.sub.g4)V.sub.lsb=E.sub.2

y.sub.error[1]=1/4(e.sub.g1+e.sub.g23e.sub.g3+e.sub.g4)V.sub.lsb=E.sub.3

y.sub.error[1]=1/4(e.sub.g1+e.sub.g2+e.sub.g33e.sub.g4)V.sub.lsb=E.sub.4

y.sub.error[2]=1/4(3e.sub.g1e.sub.g2e.sub.g3e.sub.g4)V.sub.lsb=E1

y.sub.error[2]=1/4(e.sub.g1+3e.sub.g2e.sub.g3e.sub.g4)V.sub.lsb=E2

y.sub.error[2]=1/4(e.sub.g1e.sub.g2+3e.sub.g3e.sub.g4)V.sub.lsb=E.sub.3

y.sub.error[2]=1/4(e.sub.g1e.sub.g2e.sub.g3+3e.sub.g4)V.sub.lsb=E4

y.sub.error[3]=3/4(3e.sub.g1e.sub.g2e.sub.g3e.sub.g4)V.sub.lsb=3E.sub.1

y.sub.error[3]=3/4(e.sub.g1+3e.sub.g2e.sub.g3e.sub.g4)V.sub.lsb=3E.sub.2

y.sub.error[3]=3/4(e.sub.g1e.sub.g2+3e.sub.g3e.sub.g4)V.sub.lsb=3E.sub.3

y.sub.error[3]=3/4(e.sub.g1e.sub.g2e.sub.g3+3e.sub.g4)V.sub.lsb=3E.sub.4

[0089] E.sub.1 represents the error if the selected set of elements is U.sub.1, U.sub.2, U.sub.3 and E.sub.2 is the error if the set of elements U.sub.4, U.sub.5, U.sub.6 is used, etc. For example, if the DAC input is 0 and the elements U.sub.7, U.sub.8, U.sub.9 are used to produce the output of the DAC, then the error is 3E.sub.3. Note that E.sub.1+E.sub.2+E.sub.3+E.sub.4=0.

[0090] In option 1, to be explained in the following, the objective is to noise shape the gain errors at the first stage and to convert the gain errors at other stages into white noise. First order noise shaping of the gain errors at the first stage can be achieved by making the sum of the errors equal to zero as fast as possible (E.sub.1+E.sub.2+E.sub.3+E.sub.4=0). This will depend on the input of the first stage or input of the first DAC and will be done by using two pointers illustrated in FIGS. 4 and 5, respectively.

[0091] The first pointer illustrated in FIG. 4 is used when the input of the first stage is 1 or 2. The second pointer illustrated in FIG. 5 is used when the input of the first stage is 0 or 3. The pointers decide which row should be used to produce the output of the first stage, i.e., which set of elements will appear at the first row in the DAC.sub.array. Finally, the remaining other rows will be swapped randomly to convert their errors into white noise at the remaining stages. The working of the pointers can be described by finite state machine diagrams. FIGS. 4 and 5 show the finite state machines that illustrate the working of the first and second pointer, respectively.

[0092] When the input of the first stage is 1 or 2, then the first pointer is activated, while the second pointer will be in one of the hold states. Similarly, if the input is 0 or 3, then the second pointer leaves the hold state and the first pointer goes to a hold state. Table 1 below shows the element selection of the first row in DAC.sub.array based on the finite state machines of FIGS. 4 and 5 for arbitrary input values. The unit element sets of the remaining rows in the DAC.sub.array will be assigned randomly.

TABLE-US-00002 TABLE 5 Element selection for the first row in DAC.sub.array. First column represents initial values. First stage Input 2 2 3 2 3 2 1.sup.st pointer J1 K1 G1 (Hold) L1 H1 (Hold) I1 state 2.sup.nd pointer E2 (Hold) E2 (Hold) J2 F2 (Hold) K2 G2 (Hold) state y.sub.error E.sub.1 E.sub.2 3E.sub.1 E.sub.3 3E.sub.2 E.sub.4 First row U.sub.1, U.sub.2, U.sub.3 U.sub.4, U.sub.5, U.sub.6 U.sub.1, U.sub.2, U.sub.3 U.sub.7, U.sub.8, U.sub.9 U.sub.4, U.sub.5, U.sub.6 U.sub.10, U.sub.11, U.sub.12 elements

[0093] In option 1, the first row in DAC.sub.array is chosen based on the value of the first stage input. The other rows are swapped randomly. This results in first order noise shaping of the gain errors at the first stage. However, at other stages the gain errors are turned into white noise.

[0094] In option 2, to be explained in the following, the objective is to noise shape the gain errors of the first and second stages, while converting the gain errors at the third and fourth stages into white noise. In order to noise shape the errors at the second stage, we have to select the set of elements that appears at the second row in DAC.sub.array based on the input of the second stage. Applying the same switching scheme of option 1 to the second stage is not possible because it might happen that the same set of elements is chosen for the first and the second rows, which is not feasible.

[0095] In option 1, the purpose is to add the errors to zero as soon as possible. However, one is not restricted to choose the set of elements according to the finite stage machines in FIGS. 4 and 5 only. The pointer represented by the finite state machine is a simple way to achieve noise shaping, but it is not the only way. For example, assume the state J1 is initially chosen when the input is 2. If the next input is 2, we are not restricted to choose state K1 as shown in FIG. 4. Actually, we can choose any state from the remaining states (K1, L1, I1). Assume, state L1 has been chosen randomly and the next input is 2, then we have to choose one state from the remaining states (K1, I1). We can continue this until all states are chosen and the error sums to zero. Once this happens, we can start again and choose one state from all available states. Consider another example where the input is 1, 1, 2, 2. Assume the state J1 is initially chosen, the next state could be chosen from the remaining states (K1, L1, I1). Assume I1 is chosen. Then the next state could be chosen from states A1 or D1. If A1 is chosen, then the next state should be D1.

[0096] The above concept can be used to noise shape the gain errors at the first and second stages based on their input. Firstly, based on the input of the first stage, we generate all possible states that can be used at the first stage, i.e., all possible set of elements that can be used in the first row in the DAC.sub.array. Also, based on the input of the second stage, we generate all possible sets of elements that can be used in the second row in the DAC.sub.array. Then, we combine all possible options and generate a unique solution. Based on the solution, unit elements are assigned to the rows of the DAC.sub.array. The elements of the third and fourth rows may be selected randomly from the remaining sets of elements.

[0097] For example, assume that unit elements U.sub.4, U.sub.5, U.sub.6 or elements U.sub.10, U.sub.11, U.sub.12 can be used in the first row of DAC.sub.array. Also, assume that only elements U.sub.4, U.sub.5, U.sub.6 can be used in the second row. Then, we choose elements U.sub.10, U.sub.11, U.sub.12 for the first row and elements U.sub.4, U.sub.5, U.sub.6 for the second row. Furthermore, the elements in the third and fourth rows will be chosen randomly from element sets U.sub.1, U.sub.2, U.sub.3 and U.sub.7, U.sub.8, U.sub.9. However, it can happen that there is only one possible set of unit elements for the first and the second stages and that this set is the same. For example, the set U.sub.1, U.sub.2, U.sub.3 is the only possible solution that needs to be used in the first and second rows. In this case, we choose this set for the first stage and we choose random unit element sets for the other stages. In other words, we always give priority to the first stage as it is more important than the second stage.

[0098] For options 3 and 4, the concept of option 2 is extended to include the third and fourth stages. Specifically, for option 3, sets of elements are selected so that the gain errors at the first three stages are noise-shaped, while the gain error of the last stage is converted into white noise. For option 4, all sets of elements are selected so that the gain errors are noise shaped at all stages, if possible. In general, priority for selecting sets of elements is given to the first stage and then to the second stage, etc.

[0099] Finally, option 5 is an algorithm, where the gain errors of all stages are converted into white noise. This can be achieved by randomly swapping or assigning sets of elements to all rows of the DAC.sub.array, including the first row.

[0100] FIGS. 6 and 7 show, for comparison, the output spectrum of pipeline converters with ideal DACs and input signals or full scale input tones of frequencies 10 MHz and 380 MHz, respectively.

[0101] In practice, the DACs will not be ideal, but will exhibit errors caused by mismatching between its unit elements. The actual value of each unit element is assumed to follow a Gaussian distribution with certain standard deviation a. The DAC errors due to element mismatch can be viewed as introducing constant gain error e g and an additive error term e.sub.DAC [n] that is a deterministic non-linear function of the DAC input n. First order DWA algorithms aim to make e.sub.DAC [n] uncorrelated with the DAC input while ensuring that e.sub.DAC [n] has a first-order high pass shape. This means that the PSD (power spectral density) of e.sub.DAC [n] should be zero at =0 rad/s and that the PSD is free of spurious tones and rises at 20 dB/decade as increases from zero.

[0102] A general and direct method to realize DWA is, where the DAC elements are selected sequentially by means of a pointer p(n). The pointer points to the next available unused DAC element and is described by the following equation:

p(n),(p(n1)+x(n1))mod N

where x(n) is the DAC input and N is the number of DAC elements. This cyclic selection of DAC elements ensures that the DAC INL errors quickly sum to zero. Therefore, the DAC distortion moves to high frequencies. However, this direct realization of DWA does not make e.sub.DAC [n] completely uncorrelated with the DAC input. As a result, the DAC output might show spurious tones and nonlinear artifacts. This tonal behavior depends on the input frequency and amplitude. Tones may be suppressed by methods such as BIDWA, dither, RnDWA, RDWA, etc. The general DWA algorithm or any variation of it aims to linearize the DAC by noise shaping the INL errors. However, after the linearization, the DAC will exhibit a linear gain error e g that cannot be eliminated by any element selection technique.

[0103] FIGS. 8 and 9 show, for comparison, the output spectrum of pipeline converters with DACs exhibiting unit element mismatch and an input signal of 10 MHz resulting from no data weight algorithm procedure or with a conventional data weight algorithm procedure, respectively. In this example, element mismatch of =0.1% has been introduced to all DACs. In comparison with FIG. 6, for example harmonic distortion (HDx) has degraded, which slightly improves when employing the conventional DWA algorithm as shown in FIG. 9.

[0104] FIGS. 8 and 9 shows the output spectrum for a 10 MHz input tone, with and without applying the conventional DWA technique, when DAC element mismatch of =0.1% is introduced to all DACs. As shown in FIG. 8, mismatch in DAC elements causes harmonic distortion at the output and degrades the linearity performance of the converter. After applying the conventional DWA technique, as shown in FIG. 9, the linearity performance of the converter is still poor. The conventional DWA technique linearizes the DACs. However, the resulting gain error of the DACs leaks the quantization errors of the front-end ADCs to the output and therefore, reduces the linearity performance of the converter.

[0105] FIGS. 10 and 11 show, for comparison, the output spectrum of pipeline converters with DACs exhibiting mismatch and an input signal of 380 MHz resulting from no data weight algorithm procedure or with a conventional data weight algorithm procedure, respectively. In this example, element mismatch of =0.1% has been introduced to all DACs. In comparison with FIG. 7, for example spurious free dynamic range measure (SFDR) has degraded, which slightly improves when employing the conventional DWA algorithm as shown in FIG. 11.

[0106] The simulations shown in FIGS. 8 and 9 are repeated for input signal with frequency of 380 MHz. The results are shown in FIGS. 10 and 11. As shown, applying the conventional DWA technique to the DACs is not improving the SFDR performance of the converter as the SFDR is still limited by the linear gain errors of the DACs.

[0107] FIGS. 12 and 13 show the output spectrum of pipeline converters with DACs exhibiting mismatch and input signals of 10 MHz and 380 MHz, respectively, resulting from a data weight algorithm according to an exemplary embodiment of the present disclosure. As above, element mismatch of =0.1% has been introduced to all DACs. The DWA technique described as option 1 with respect to FIGS. 4 and 5 has been used. The output spectrum shows no spurious tones and nonlinear distortion. This is reflected in the harmonic distortion measure of the graph shown in FIG. 12 and the SFDR measure of the graph shown in FIG. 13.

[0108] FIG. 14 shows a harmonic distortion (HDx) of an output signal depending on an amount of mismatch between unit elements. Full scale input tone is applied at 10 MHz. All options 1 to 5, as introduced with respect to FIGS. 4 and 5 above, show an improvement with respect to no DWA 1451 or conventional DWA 1452. Option one 1453 and options two to four 1454 show additional improvement over option five 1455. The proposed DWA clearly improves the HDx performance of the converter with option one 1453 being only slightly degraded in comparison with options two to four 1454.

[0109] FIG. 15 shows a spurious free dynamic range (SFDR) of an output signal depending on an amount of mismatch between unit elements. Full scale input tone is applied at 380 MHz. All algorithms according to options 1 to 5 show an improvement with respect to no DWA 1451 or conventional DWA 1452. Option one 1453 and options two to four 1454 show additional improvement over option five 1455, at least for larger amounts of mismatch. The proposed DWA clearly improves the SFDR performance of the converter, with option one 1453 being only slightly degraded in comparison with options two to four 1454.

[0110] FIG. 16 shows a signal-to-noise ratio (SNR) of an output signal depending on an amount of mismatch between unit elements. Full scale input tone is applied at 10 MHz. The algorithms of options one to four 1453, 1454 show an improvement in signal-to-noise ratio with respect to option five 1455, with the signal-to-noise ratio of option one 1453 being only slightly degraded in comparison with options two to four 1454. Summarizing from FIGS. 14 to 16, option 1 appears sufficient as the other options 2 to 4 do not noticeably improve the performance of the converter.

[0111] In this specification, embodiments have been presented in terms of a selected set of details. However, a person of ordinary skill in the art would understand that many other embodiments may be practiced which include a different selected set of these details. It is intended that the following claims cover all possible embodiments.

REFERENCE NUMERALS

[0112] 100 circuit [0113] 101 first stage [0114] 102 second stage [0115] 103 further stage [0116] 104 back-end stage [0117] 105 first stage input signal [0118] 106 second stage input signal [0119] 110 first DAC [0120] 111 second DAC [0121] 112 further DAC [0122] 113 input signal [0123] 114 further input signal [0124] 115 overall input signal [0125] 116 overall output signal [0126] 120 unit element [0127] 130 switching circuitry [0128] 140 control device [0129] 217 input value (of first DAC) [0130] 221 set of unit elements [0131] 231 first switching state [0132] 232 second switching state [0133] 318 further input value (of second DAC) [0134] 322 further set of unit elements [0135] 323 first pointer [0136] 324 second pointer [0137] 433 switching state [0138] 434 associated error [0139] 1451 no DWA [0140] 1452 conventional DWA [0141] 1453 option 1 [0142] 1454 options 2 to 4 [0143] 1455 option 5