PACKAGE SUBSTRATE WITH EMBEDDED DEVICE, AND MANUFACTURING METHOD THEREFOR

Abstract

A package substrate with an embedded device and a manufacturing method therefor are disclosed. The method includes: manufacturing a third circuit layer and a target on a temporary carrier plate, and laminating a third dielectric layer; placing a device to be embedded on the third dielectric layer which is then covered with a second dielectric layer; laminating a second copper foil and manufacturing a second circuit layer, a second copper pillar, and a third copper pillar; laminating a first dielectric layer and a first copper foil sequentially, and removing the temporary carrier plate; laminating a fourth dielectric layer on the third circuit layer; laminating a fourth copper foil on the fourth dielectric layer; and manufacturing a fourth circuit layer and a fourth copper pillar through the fourth copper foil, and manufacturing a first circuit layer and a first copper pillar through the first copper foil.

Claims

1. A manufacturing method for a package substrate with an embedded device, comprising: manufacturing a third circuit layer and a target on an upper surface of a temporary carrier plate, and laminating a third dielectric layer on the third circuit layer and the target; placing a device to be embedded on the third dielectric layer and covering the device to be embedded with a second dielectric layer, wherein a pin of the device to be embedded is arranged opposite to the third dielectric layer; laminating a second copper foil on an upper surface of the second dielectric layer, and manufacturing a second circuit layer, a second copper pillar, and a third copper pillar through the second copper foil; laminating a first dielectric layer on the second circuit layer, the second copper pillar, and the third copper pillar, laminating a first copper foil on an upper surface of the first dielectric layer, and removing the temporary carrier plate; laminating a fourth dielectric layer on a lower surface of the third circuit layer, and laminating a fourth copper foil on a lower surface of the fourth dielectric layer; and manufacturing a fourth circuit layer and a fourth copper pillar through the fourth copper foil, and manufacturing a first circuit layer and a first copper pillar through the first copper foil; or, manufacturing a target on a temporary carrier plate, and laminating a third dielectric layer on the target; placing a device to be embedded on the third dielectric layer and covering the device to be embedded with a second dielectric layer, wherein a pin of the device to be embedded is attached to the third dielectric layer; laminating a second copper foil on an upper surface of the second dielectric layer, and manufacturing a third circuit layer through the second copper foil; covering the third circuit layer with a first dielectric layer, laminating a first copper foil on an upper surface of the first dielectric layer, and removing the temporary carrier plate to expose a lower surface of the third dielectric layer; manufacturing a second circuit layer, a second copper pillar and a third copper pillar on the lower surface of the third dielectric layer; laminating the fourth dielectric layer on the second circuit layer, the second copper pillar and the third copper pillar, and laminating a fourth copper foil on a lower surface of the fourth dielectric layer; and manufacturing a first circuit layer and a first copper pillar through the first copper foil, and manufacturing a fourth circuit layer and a fourth copper pillar through the fourth copper foil.

2. The manufacturing method for a package substrate with an embedded device according to claim 1, wherein the manufacturing a second circuit layer, a second copper pillar and a third copper pillar through the second copper foil comprises: manufacturing a second via hole and a third via hole, wherein the second via hole penetrates through the third dielectric layer and the second dielectric layer; manufacturing a second metal seed layer on the second copper foil, the second via hole and the third via hole; and manufacturing the second circuit layer, the second copper pillar and the third copper pillar on the second metal seed layer.

3. The manufacturing method for a package substrate with an embedded device according to claim 1, wherein the manufacturing a first circuit layer and a first copper pillar through the first copper foil comprises: manufacturing a first via hole; manufacturing a first metal seed layer on the first copper foil and the first via hole; and manufacturing the first circuit layer and the first copper pillar on the first metal seed layer.

4. The manufacturing method for a package substrate with an embedded device according to claim 1, wherein the manufacturing a second circuit layer, a second copper pillar and a third copper pillar on the lower surface of the third dielectric layer comprises: manufacturing a second via hole and a third via hole on the lower surface of the third dielectric layer, wherein the second via hole penetrates through the third dielectric layer and the second dielectric layer; manufacturing a second metal seed layer on the lower surface of the third dielectric layer, the second via hole and the third via hole; and manufacturing the second circuit layer, the second copper pillar and the third copper pillar on the second metal seed layer.

5. The method for manufacturing the package substrate with an embedded device according to claim 1, wherein the laminating a third dielectric layer on the third circuit layer and the target comprises: laminating a viscous dielectric layer on the third circuit layer and the target, wherein the viscous dielectric layer is used for fixing the device to be embedded.

6. The manufacturing method for a package substrate with an embedded device according to claim 2, wherein the manufacturing a second metal seed layer on the second copper foil, the second via hole and the third via hole comprises: manufacturing the second metal seed layer on the second copper foil, the second via hole and the third via hole using a chemical deposition method or a physical sputtering method.

7. The manufacturing method for a package substrate with an embedded device according to claim 1, wherein a thickness of the first dielectric layer is the same as a thickness of the fourth dielectric layer.

8. The manufacturing method for a package substrate with an embedded device according to claim 1, wherein the laminating a third dielectric layer on the third circuit layer and the target comprises: laminating the third dielectric layer on the third circuit layer and the target by a vacuum laminator or a laminating machine.

9. The manufacturing method for a package substrate with an embedded device according to claim 4, wherein the manufacturing a second circuit layer, a second copper pillar and a third copper pillar on the second metal seed layer comprises: manufacturing the second circuit layer, the second copper pillar and the third copper pillar on the second metal seed layer using an improved semi-additive method or a tenting method.

10. A package substrate with an embedded device, manufactured by the manufacturing method for a package substrate with an embedded device according to claim 1.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0031] FIG. 1 is a schematic diagram showing steps of a manufacturing method for a package substrate with an embedded device according to an embodiment of the present application;

[0032] FIG. 2 is a schematic diagram showing steps of a manufacturing method for a package substrate with an embedded device according to another embodiment of the present application;

[0033] FIG. 3 is a schematic structural diagram showing a manufacturing process of a package substrate with an embedded device according to an embodiment of the present application; and

[0034] FIG. 4 is a schematic structural diagram showing a manufacturing process of a package substrate with an embedded device according to another embodiment of the present application.

DETAILED DESCRIPTION

[0035] The embodiments of the present application will be described in detail below with reference to the drawings, and the principles and processes of the manufacturing method for a package substrate with an embedded device in the embodiments of the present application are described below.

[0036] Referring to FIG. 1 and FIG. 2, a manufacturing method for a package substrate with an embedded device according to the present application includes the following steps of: [0037] S1. manufacturing a third circuit layer and a target on a temporary carrier plate, and laminating a third dielectric layer on the third circuit layer and the target; [0038] S2. placing a device to be embedded on the third dielectric layer and covering the device to be embedded with a second dielectric layer, where a pin of the device to be embedded is arranged opposite to the third dielectric layer; [0039] S3. laminating a second copper foil on an upper surface of the second dielectric layer, and manufacturing a second circuit layer, a second copper pillar, and a third copper pillar through the second copper foil; [0040] S4. laminating a first dielectric layer on the second circuit layer, the second copper pillar, and the third copper pillar, laminating a first copper foil on an upper surface of the first dielectric layer, and removing the temporary carrier plate; [0041] S5. laminating a fourth dielectric layer on a lower surface of the third circuit layer, and laminating a fourth copper foil on a lower surface of the fourth dielectric layer; and [0042] S6. manufacturing a fourth circuit layer and a fourth copper pillar through the fourth copper foil, and manufacturing a first circuit layer and a first copper pillar through the first copper foil.

[0043] Alternatively, the manufacturing method may include the following steps of: [0044] S11. manufacturing a target on a temporary carrier plate, and laminating a third dielectric layer on the target; [0045] S12. placing a device to be embedded on the third dielectric layer and covering the device to be embedded with a second dielectric layer, where a pin of the device to be embedded is attached to the third dielectric layer; [0046] S13. laminating a second copper foil on an upper surface of the second dielectric layer, and manufacturing a third circuit layer through a second copper foil; [0047] S14. covering the third circuit layer with a first dielectric layer, laminating a first copper foil on an upper surface of the first dielectric layer, and removing the temporary carrier plate to expose a lower surface of the third dielectric layer; [0048] S15. manufacturing a second circuit layer, a second copper pillar and a third copper pillar on the lower surface of the third dielectric layer; [0049] S16. laminating a fourth dielectric layer on the second circuit layer, the second copper pillar and the third copper pillar, and laminating a fourth copper foil on a lower surface of the fourth dielectric layer; and [0050] S17. manufacturing a first circuit layer and a first copper pillar through the first copper foil, and manufacturing a fourth circuit layer and a fourth copper pillar through the fourth copper foil.

[0051] In some embodiments of the present application, the first circuit layer is disposed at an uppermost portion of the entire package substrate, and the fourth circuit layer is located at a lowermost portion of the substrate. The second circuit layer is a circuit layer directly connected to the embedded device, and the second circuit layer is further connected to the first circuit layer. The third circuit layer is a circuit layer connected to the second circuit layer and connected to the fourth circuit layer, the first dielectric layer is a dielectric layer carrying the first circuit layer, the fourth dielectric layer is a dielectric layer carrying the fourth circuit layer, the third dielectric layer is a dielectric layer for fixing the device to be embedded, and the second dielectric layer is a dielectric layer covering the entire embedded device. The first dielectric layer and the fourth dielectric layer may be made of a PP material (a polypropylene material), and the third dielectric layer may be made of a dielectric material having viscosity to fix the embedded device. The second dielectric layer may be made of a fiberglass-free dielectric material. The first circuit layer and the second circuit layer may be connected by means of the first copper pillar. The second circuit layer is a circuit layer connected to the embedded device, and the second circuit layer may be connected to the embedded device by means of the second copper pillar. The third circuit layer may be connected to the second circuit layer by means of the third copper pillar passing through the second dielectric layer covering the embedded device and the third dielectric layer for fixing the embedded device. The fourth circuit layer is connected to the third circuit layer through a fourth copper pillar. In the manufacturing process, the first copper foil, the second copper foil, the third copper foil and the fourth copper foil used for manufacturing the circuits may be tightly attached to the corresponding dielectric layer by laminating.

[0052] Further, in S3, the manufacturing a second circuit layer, a second copper pillar and a third copper pillar through the second copper foil may include: [0053] S111. manufacturing a second via hole and a third via hole, where the second via hole penetrates through the third dielectric layer and the second dielectric layer; [0054] S112. manufacturing a second metal seed layer on the second copper foil, the second via hole and the third via hole; and [0055] S113. manufacturing the second circuit layer, the second copper pillar and the third copper pillar on the second metal seed layer.

[0056] The second via hole and the third via hole may be manufactured in the second copper foil and the second dielectric layer through laser drilling, where the second via hole needs to penetrate through the second dielectric layer and the third dielectric layer, and the third circuit layer needs to be exposed from the second via hole, so as to facilitate subsequent manufacturing of the third copper pillar for connecting the third circuit layer and the second circuit layer, and when the third via hole is manufactured, the pin of the embedded device needs to be exposed from the third via hole. After drilling, a seed layer needs to be formed on the second via hole, the third via hole and the drilled copper foil, and the seed layer may be used for subsequent manufacturing of the second circuit layer. After the metal seed layer is completed, the second circuit layer may be made on the seed layer. In addition, it should be noted that the number of the third via hole and the third copper pillar may be determined according to the pin of the embedded device, while the number of the second via hole and the second copper pillar may be selected according to specific circuit function in practical application, which may be one or more, and is not limited here.

[0057] Further, in S6, the manufacturing a first circuit layer and a first copper pillar through the first copper foil may include: [0058] S211. manufacturing a first via hole; [0059] S212. manufacturing a first metal seed layer on the first copper foil and the first via hole; and [0060] S213. manufacturing the first circuit layer and the first copper pillar on the first metal seed layer.

[0061] In the present application, the first via hole needs to penetrate through the entire first dielectric layer, while one or more first via holes may be provided according to the specific actual application. The first via hole may be manufactured by a laser drilling process. After the first via hole is manufactured, the first metal seed layer is covered on the first copper foil and the first via hole, the metal seed layer needs to completely cover the drilled first copper foil and the first via hole, and the metal seed layer may be manufactured using a chemical deposition method or a physical sputtering method. After the manufacturing of the metal seed layer is completed, the first circuit layer and the first copper pillar need to be manufactured through the metal seed layer.

[0062] Further, in S15, the manufacturing a second circuit layer, a second copper pillar and a third copper pillar on the lower surface of the third dielectric layer may include: [0063] S221. manufacturing a second via hole and a third via hole on the lower surface of the third dielectric layer, where the second via hole penetrates through the third dielectric layer and the second dielectric layer; [0064] S222. manufacturing a second metal seed layer on the lower surface of the third dielectric layer, the second via hole and the third via hole; and [0065] S223. manufacturing the second circuit layer, the second copper pillar and the third copper pillar on the second metal seed layer.

[0066] The second via hole and the third via hole may be manufactured through laser drilling on the lower surface of the third dielectric layer, where the second via hole needs to penetrate through the second dielectric layer and the third dielectric layer, and the third circuit layer needs to be exposed from the second via hole, so as to facilitate subsequent manufacturing of the third copper pillar for connecting the third circuit layer with the second circuit layer, and when the third via hole is manufactured, the pin of the embedded device needs to be exposed from the third via hole. After drilling, a seed layer needs to be formed on the second via hole, the third via hole and the drilled copper foil, and the seed layer may be used for subsequent manufacturing of the second circuit layer. After the metal seed layer is completed, the second circuit layer may be made on the seed layer.

[0067] Further, the second metal seed layer is manufactured on the second copper foil, the second via hole and the third via hole using a chemical deposition method or a physical sputtering method.

[0068] In some embodiments of the present application, the second metal seed layer may be manufactured using a chemical deposition method or a physical sputtering method. Further, the chemical deposition method may be chemical vapor deposition with a copper material, while the physical sputtering may be a vacuum magnetron sputtering technology for plating a copper film on the dielectric layer.

[0069] Further, in some embodiments of the present application, a thickness of the first dielectric layer is the same as a thickness of the fourth dielectric layer.

[0070] The first dielectric layer and the fourth dielectric layer may be laminated with a corresponding circuit layer by using a laminating process. Since the laminated dielectric layer has a certain transverse stress, it can avoid the warping issues caused by an asymmetric structure if the thickness of the first dielectric layer and the thickness of the fourth dielectric layer are the same. In addition, the thickness of the first dielectric layer and the thickness of the fourth dielectric layer may also be similar. When the thicknesses of the two dielectric layers are similar, a thickness difference of the two dielectric layers may not exceed 0.05 mm.

[0071] Further, in some embodiments of the present application, the third dielectric layer may also be made by a laminating process. When laminating the third dielectric layer, which is made of a viscous material, it is necessary to stick a protective film on one side surface of the third dielectric layer for fixing the embedded device, and the protective film needs to be peeled off before placing the embedded device after laminating.

[0072] Further, the third dielectric layer may be laminated on the third circuit layer and the target by a vacuum laminator or laminating machine.

[0073] Further, the second circuit layer, the second copper pillar and the third copper pillar may be manufactured on the second metal seed layer by an MSAP process (modified semi-additive process) or the Tenting process.

[0074] With reference to FIG. 3 and FIG. 4, two manufacturing methods of the package substrate with an embedded device according to the present application are described below.

[0075] One method may refer to FIG. 3.

[0076] Referring to a of FIG. 3, a temporary carrier plate 1001 includes a copper foil and a carrier which may be peeled off from each other. Firstly, a third circuit layer 1002 and a target 1003 are manufactured on the temporary carrier plate 1001, and a third dielectric layer 1004 is laminated on the third circuit layer 1002 and the target 1003. The third dielectric layer 1004 is a viscous dielectric layer, which can fix a subsequent embedded device. The target 1003 may be used for positioning the embedded device. The third dielectric layer 1004 may be laminated by a vacuum laminator or a laminating machine. The third circuit layer 1002 may be manufactured by an MSAP process.

[0077] Then, referring to b of FIG. 3, a device to be embedded 1005 is placed on the third dielectric layer 1004 and a second dielectric layer 1006 is covered on the device to be embedded 1005. A pin of the device to be embedded 1005 is arranged opposite to the third dielectric layer 1004, the pin of the device to be embedded 1005 faces upwards, a body of the device to be embedded 1005 is bonded with the third dielectric layer 1004, and the target can position the device to be embedded 1005 when placing the device. The second dielectric layer 1006 needs to completely cover the device to be embedded 1005.

[0078] Then, referring to c of FIG. 3, a second copper foil 1007 is laminated on an upper surface of the second dielectric layer 1006, and a second circuit layer 1008, a second copper pillar 1009 and a third copper pillar 1010 are manufactured through the second copper foil 1007. The second copper pillar 1009 needs to penetrate through the second dielectric layer 1006 and the third dielectric layer 1004. The third copper pillar 1010 may be electrically connected to the second circuit layer 1008 and the third circuit layer 1002, and the second copper pillar 1009 may be electrically connected to the second circuit layer 1008 and the device to be embedded 1005 between the second circuit layer 1008 and the third circuit layer 1002.

[0079] Then, referring to d of FIG. 3, a first dielectric layer 1011 is laminated and covered on the second circuit layer 1008, a first copper foil 1012 is laminated on an upper surface of the first dielectric layer 1011, and the temporary carrier plate 1001 is removed. The first dielectric layer 1011 needs to completely cover the second circuit layer 1008, the second copper pillar 1009 and the third copper pillar 1010. After the first copper foil 1012 is laminated, the temporary carrier plate 1001 may be removed by physical peeling off and etching.

[0080] Then, referring to e of FIG. 3, after removing the temporary carrier plate 1001, a fourth dielectric layer 1013 is laminated on a lower surface of the third circuit layer 1002. A fourth copper foil 1014 is laminated on a lower surface of the fourth dielectric layer 1013. When the fourth dielectric layer 1013 is laminated, a dielectric layer made of a PP material with the same thickness as that of the first dielectric layer 1011 may be selected, and a warping phenomenon caused by asymmetry during laminating can be avoided with the same thickness.

[0081] Finally, referring to f of FIG. 3, after the fourth copper foil is laminated, a fourth circuit layer 1015 and a fourth copper pillar 1016 may be manufactured through the fourth copper foil 1014, and the first circuit layer 1017 and the first copper pillar 1018 may be manufactured through the first copper foil 1012. The first circuit layer 1017 and the fourth circuit layer 1015 may be manufactured at the same time, and the first copper pillar 1018 and the fourth copper pillar 1016 may also be manufactured at the same time. Alternatively, the first circuit layer 1017 may be manufactured first and then the fourth circuit layer 1015 may be manufactured, and finally the first copper pillar 1018 and the fourth copper pillar 1016 may be manufactured. The sequence of steps of the process is not limited here.

[0082] In the sub-figures a to f of FIG. 3, only some layers and devices newly added in each manufacturing step are labeled, and the layers and devices already appearing in the previous step are not labeled.

[0083] Another method may refer to FIG. 4.

[0084] Referring to a of FIG. 4, a target 2002 is manufactured on a temporary carrier plate 2001 first, and a third dielectric layer 2003 is laminated on the target 2002.

[0085] Then, referring to b of FIG. 4, a device to be embedded 2004 is placed on the third dielectric layer 2003 and a second dielectric layer 2005 is covered on the device to be embedded 2004. A pin of the device to be embedded 2004 is attached to the third dielectric layer 2003.

[0086] Then, referring to c of FIG. 4, a second copper foil 2006 is laminated on an upper surface of the second dielectric layer 2005, and a third circuit layer 2007 is manufactured through the second copper foil 2006.

[0087] Then, referring to d of FIG. 4, a first dielectric layer 2008 is covered on the third circuit layer 2007, a first copper foil 2009 is laminated on an upper surface of the first dielectric layer 2008, and the temporary carrier plate 2001 is removed to expose a lower surface of the third dielectric layer 2003.

[0088] Then, referring to e of FIG. 4, a second circuit layer 2010, a second copper pillar 2011 and a third copper pillar 2012 are manufactured on the lower surface of the third dielectric layer 2003.

[0089] Then, referring to f of FIG. 4, a fourth dielectric layer 2013 is laminated to cover the second circuit layer 2010, the second copper pillar 2011 and the third copper pillar 2012 from below the substrate, and a fourth copper foil 2014 is laminated on a lower surface of the fourth dielectric layer 2013.

[0090] Finally, referring to g in FIG. 4, a first circuit layer 2015 and a first copper pillar 2016 are manufactured through the first copper foil 2009, and a fourth circuit layer 2017 and a fourth copper pillar 2018 are manufactured through the fourth copper foil 2014.

[0091] It should be noted that in the subfigures a to g of FIG. 4, only some layers and devices newly added in each manufacturing step are labeled, and the layers and devices already appearing in the previous step are not labeled.

[0092] In addition, the embodiments of the present application also provide a package substrate with an embedded device which may be manufactured and obtained by the manufacturing method for a package substrate with an embedded device in any of the embodiments mentioned above.

[0093] In some alternative embodiments, the functions/operations mentioned in the block diagrams may occur out of the order noted in the operation diagram. For example, two blocks shown in succession may, in fact, be executed substantially concurrently or the blocks may sometimes be executed in the reverse order, depending on the functionality/operation involved. In addition, the embodiments presented and described in the flowchart of the present application are provided by way of example, with the purpose of providing a more comprehensive understanding of the technology. The disclosed methods are not limited to the operations and logic flows presented herein. Alternative embodiments are contemplated in which the order of the various operations is changed and the sub-operations described as a part of a general operation is performed independently.

[0094] In the description of this specification, the description with reference to the terms such as one embodiment/implementation, another embodiment/implementation, or some embodiments/implementations means that the specific features, structures, materials or characteristics described in connection with the embodiment or implementation are included in at least one embodiment or implementation of the present application. In the specification, the schematic representation of the above terms does not necessarily mean the same embodiment or implementation. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or implementations in a suitable manner.

[0095] Although the embodiments of the present application have been shown and described, those of ordinary skills in the art should understand that: various changes, amendments, substitutions and modifications can be made to these embodiments without departing from the principles and purposes of the present application, and the scope of the present application is limited by the claims and equivalents thereof.

[0096] The foregoing describes the preferred embodiments of the present application in detail, but the present application is not limited to the embodiments, those of ordinary skills in the art can make various equal deformations or replacements without departing from the gist of the present application, and these equal deformations or replacements shall all fall within the scope limited by the claims of the present application.