Constant level-shift buffer amplifier circuits

Abstract

A push-pull dynamic amplifier is operable in reset and amplification phases. The amplifier includes first NMOS and PMOS input transistors that are electrically coupled to a first input terminal and a first output terminal. Second NMOS and PMOS input transistors are electrically coupled to a second input terminal and a second output terminal. First and second reset switches are electrically coupled to the first and second output terminals, respectively. A power supply switch is electrically coupled to the first and the second PMOS transistors, and a ground switch is electrically coupled to the first and the second NMOS transistors. During the reset phase, the reset switches are closed and the power supply switch and the ground switch are opened. During the amplification phase, the reset switches are opened and the power supply switch and the ground switch are closed.

Claims

1. A level-shifting buffer amplifier producing a level shift between input and output terminals, comprising: a current source; a first transistor electrically coupled to the input terminal and the output terminal; a second transistor electrically coupled to the input terminal and the current source; and a variable resistance electrically coupled to the first transistor and the output terminal, wherein a resistance of the variable resistance is a first function of a voltage at a control terminal, wherein the level shift is a second function of the voltage at the control terminal.

2. The buffer amplifier of claim 1, wherein a threshold voltage of the first transistor is lower than a threshold voltage of the second transistor.

3. The buffer amplifier of claim 2, further comprising a third transistor electrically coupled to the first and the second transistors, providing a negative feedback.

4. The buffer amplifier of claim 3, wherein the first transistor is an NMOS transistor.

5. The buffer amplifier of claim 3, wherein the first transistor is a PMOS transistor.

6. A level-shifting buffer amplifier, comprising: an input terminal and an output terminal a first transistor having a back-gate terminal; and a current source; a second transistor electrically coupled to the first transistor and the current source, providing a negative feedback, wherein: the first transistor is a fully-depleted silicon-on-insulator transistor, and a control voltage is applied to the back-gate terminal to provide a constant level shift between the input and the output terminals.

7. The buffer amplifier of claim 6, wherein the first transistor is an NMOS transistor.

8. The buffer amplifier of claim 6, wherein the first transistor is a PMOS transistor.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) For a fuller understanding of the nature and advantages of the present concepts, reference is made to the following detailed description of preferred embodiments and in connection with the accompanying drawings. In the drawings, like reference characters generally refer to like features (e.g., functionally-similar and/or structurally-similar elements).

(2) FIG. 1 is a schematic diagram of a source follower buffer amplifier circuit according to the prior art.

(3) FIG. 2 is a schematic diagram of a flipped source follower buffer amplifier circuit according to the prior art.

(4) FIG. 3 is a schematic diagram of a level shifting buffer amplifier circuit according to one or more embodiments.

(5) FIG. 4 is a schematic diagram of a level shifting buffer amplifier circuit according to the first embodiment of the invention using an NMOS transistor as a variable resistor.

(6) FIG. 5 is a schematic diagram of the first embodiment of a level shifting buffer amplifier circuit according to the first embodiment of the invention using a PMOS transistor as a variable resistor.

(7) FIG. 6 is a schematic diagram of a level shifting buffer amplifier circuit according to a second embodiment of the invention.

(8) FIG. 7 is a schematic diagram of a level shifting buffer amplifier circuit according to a third embodiment of the invention.

(9) FIG. 8 is a schematic diagram of a level shifting buffer amplifier circuit according to a fourth embodiment of the invention.

(10) FIG. 9 is a schematic diagram of a level shifting buffer amplifier circuit according to a fifth embodiment of the invention.

(11) FIG. 10 is a schematic diagram of a level shifting buffer amplifier circuit according to a sixth embodiment of the invention.

(12) FIG. 11 is a diagram of a control loop to keep the level shift constant in level shifting buffer amplifier circuits according to various embodiments of the invention.

(13) FIG. 12 is an illustration of one embodiment of a combination of a difference amplifier and an integrator in a control loop shown in FIG. 11.

(14) FIG. 13 illustrates an embodiment of an amplifier with a variable resistance implemented in a NMOS transistor.

(15) FIG. 14 illustrates an embodiment of an amplifier with a variable resistance implemented in a PMOS transistor.

(16) FIG. 15 illustrates an embodiment comprising a source follower with a variable threshold transistor.

(17) FIG. 16 illustrates an embodiment comprising a FSF with a variable threshold transistor.

(18) FIG. 17 illustrates an embodiment comprising a feedback control loop.

(19) FIG. 18 illustrates a switching circuit portion comprising a differential switched-capacitor integrator.

DETAILED DESCRIPTION

(20) The following discussion illustrates detailed descriptions of various concepts related to, and embodiments of, inventive apparatus relating to constant level-shift buffer amplifier circuits. It should be appreciated that various concepts introduced above and discussed in greater detail below may be implemented in any of numerous ways, as the disclosed concepts are not limited to any particular manner of implementation. Examples of specific implementations and applications are provided primarily for illustrative purposes.

(21) As is evident from Equations (1) and (4), prior art source follower buffer amplifiers' level shift varies a great deal across PVT. The inventors have recognized that it is advantageous to provide a control for the level shift to make it constant (or less variable), for example, over PVT variation.

(22) FIG. 3. shows an exemplary buffer amplifier 30 comprising an NMOS input transistor M1, a current source I, and a variable resistor R.sub.var.

(23) The variable resistor R.sub.var provides an IR voltage drop such that the level shift is given by:

(24) $\begin{array}{cc}{V}_{LS}=V_{GS1}+\left(I+I_O\right)R_{var}=V_T+\sqrt{\frac{2\left(I+I_O\right)}{{}_n{C_{\mathrm{OX}}\left(\frac{W}{L}\right)}_1}}+\left(I+I_O\right)R_{\mathrm{var}}& \left(5\right)\end{array}$
where V.sub.GS1 is the gate-to-source voltage of M1,

(25) ${\left(\frac{W}{L}\right)}_1$
is the width (W) over length (L) ratio of M1.

(26) As can be seen in Equation (5), it will be possible to adjust the value of R.sub.var to counter the variations of V.sub.T and

(27) $\sqrt{\frac{2\left(I+I_O\right)}{{}_n{C_{\mathrm{OX}}\left(\frac{W}{L}\right)}_1}}$
without changing the bias current I.

(28) In some applications, it may be advantageous to adjust both R.sub.var and I for more flexibility in the adjustment.

(29) FIG. 4 illustrates a level shifting buffer amplifier according to one or more embodiments wherein the variable resistor R.sub.var of the previous example is substituted by an NMOS transistor MR1. We note that in this and other present embodiments and examples, the substitution or replacement of a transistor in place of a resistor, e.g., a variable resistance, is intended broadly as would be understood by those skilled in the art. Therefore, the description of a resistor or variable resistor to comprise such other components (e.g., NMOS or PMOS transistors) is intended to convey a general ability to insert or replace the resistance or variable resistance of one such element with the other as best suits a given implementation.

(30) The NMOS transistor MR1 is biased in the triode region so that its ON resistance R.sub.ON functions as R.sub.var, which is controlled by the control voltage V.sub.CONT applied at the gate of MR1.

(31) $\begin{array}{cc}{R}_{var}=R_{ON}\frac{1}{{}_n{C_{\mathrm{OX}}\left(\frac{W}{L}\right)}_{R1}\left(V_{\mathrm{CONT}}-V_S-V_T\right)}& \left(6\right)\end{array}$
where

(32) 0${\left(\frac{W}{L}\right)}_{R1}$
is the W over L ratio of MR1, V.sub.CONT is the control voltage applied to the gate of MR1, and V.sub.S the voltage at the source of MR1, which is the output voltage V.sub.O.

(33) The variable-resistance embodiments of FIGS. 3 and 4 can result in higher output resistances and lower voltage gains than the prior art LSBA of FIG. 1. The variable resistor R.sub.var is in series with the resistance into the source of M1, increasing the output resistance to:

(34) $\begin{array}{cc}{R}_o\frac{1}{g_{m1}}+R_{var}& \left(7\right)\end{array}$
Since R.sub.var is a function of the output voltage according to Equation (6), it can be shown that the incremental gain is further reduced from Equation (2) by the factor of

(35) $1+\frac{R_{\mathrm{var}}I}{V_{\mathrm{GSR}1}-V_T}$
giving:

(36) $\begin{array}{cc}{a}_v=\frac{1}{1+\frac{1}{g_{m1}}\left(\frac{1}{r_{o1}}+\frac{1}{R_{out}}\right)}.Math.\frac{1}{1+\frac{R_{\mathrm{var}}I}{V_{\mathrm{GSR}1}-V_T}}& \left(8\right)\end{array}$
where V.sub.GR1 is the gate-to-source voltage of MR1.

(37) FIG. 5 illustrates a level shifting buffer amplifier according to one or more embodiments wherein the former variable resistor R.sub.var is substituted by a PMOS transistor MR2. The PMOS transistor MR2 is biased in the triode region so that its ON resistance R.sub.ON functions as R.sub.var, which is controlled by the control voltage V.sub.CONT:

(38) $\begin{array}{cc}{R}_{var}=R_{ON}\frac{1}{{}_n{C_{\mathrm{OX}}\left(\frac{W}{L}\right)}_{R2}.Math.V_{\mathrm{CONT}}-V_S-V_T.Math.}& \left(9\right)\end{array}$
where

(39) ${\left(\frac{W}{L}\right)}_{R2}$
is the W over L ratio of MR2, V.sub.CONT is the control voltage applied to the gate of MR2, and V.sub.S the voltage at the source of MR2.

(40) The output resistance of the embodiment of the present invention in FIG. 3 with the variable resistance in FIG. 5 is given by:

(41) $\begin{array}{cc}{R}_o\frac{1}{g_{m1}}+R_{var}& \left(10\right)\end{array}$
The incremental gain in this case, however, is increased by a factor of

(42) $1+\frac{R_{\mathrm{var}}I}{.Math.V_{\mathrm{GSR}2}-V_T.Math.}:$

(43) $\begin{array}{cc}{a}_v=\frac{1+\frac{R_{\mathrm{var}}I}{.Math.V_{\mathrm{GSR}2}-V_T.Math.}}{1+\frac{1}{g_{m1}}\left(\frac{1}{r_{o1}}+\frac{1}{R_{out}}\right)}& \left(11\right)\end{array}$
where V.sub.GSR2 is the gate-to-source voltage of MR2.

(44) Since this gain is closer to 1 than the LSBA circuit using the variable resistor in FIG. 4, the embodiment of the variable resistor in FIG. 5 may be a preferred embodiment for some applications.

(45) FIG. 6 shows another embodiment of the present invention, based on the FSF in FIG. 2, further including a variable resistor R.sub.var. The level shift is given by

(46) $\begin{array}{cc}{V}_{LS}=V_{GS1}+{\mathrm{IR}}_{var}=V_T+\sqrt{\frac{2I}{{}_n{C_{\mathrm{OX}}\left(\frac{W}{L}\right)}_1}}+{\mathrm{IR}}_{var}& \left(12\right)\end{array}$
where V.sub.GS1 is the gate-to-source voltage of M1,

(47) 0${\left(\frac{W}{L}\right)}_1$
is the W over L ratio of M1.

(48) Again, the variable resistor R.sub.var can be substituted or implemented by an NMOS transistor as in FIG. 7, or by a PMOS transistor as in FIG. 8, where the resistance R.sub.var is given by Equation (6) and Equation (9), respectively.

(49) In some aspects, the embodiments in FIGS. 6-8 compared with the embodiments in in FIGS. 3-5 eliminate or reduce the effect of the load current, and the output resistance is also reduced due to the negative feedback provided by M2. The output resistance is given by:

(50) $\begin{array}{cc}{R}_o\frac{\frac{1}{g_{m1}}+R_{var}}{g_{m2}{r}_{o1}}& \left(13\right)\end{array}$
where g.sub.m1 and g.sub.m2 are the transconductance of M1 and M2, respectively, and r.sub.o1 is the output resistance of M1. The incremental gains of the LSBA in FIG. 7 is given by

(51) $\begin{array}{cc}{a}_v=\frac{1}{1+\frac{1}{g_{m1}{r}_{o1}}}.Math.\frac{1}{1+\frac{R_{\mathrm{var}}I}{V_{\mathrm{GSR}1}-V_T}}& \left(14\right)\end{array}$
where V.sub.GSAR1 is the gate-to-source voltage of MR1.

(52) The incremental gain of the LSBA in FIG. 8 is given by

(53) $\begin{array}{cc}{a}_v=\frac{1+\frac{R_{\mathrm{var}}I}{V_{\mathrm{GSR}2}-V_T}}{1+\frac{1}{g_{m1}{r}_{o1}}}& \left(15\right)\end{array}$
where V.sub.GSR2 is the gate-to-source voltage of MR2.

(54) The incremental gain of the circuit in FIG. 8 is higher than that in FIG. 7, and may be preferred for some applications.

(55) FIG. 9 illustrates another embodiment of the present invention. It comprises a parallel connection of a first source follower M1 and a second source follower M2 with a series variable resistor R.sub.VAR. Preferably, M1 and M2 have two different threshold voltages such that V.sub.T1>V.sub.T2, where V.sub.T1 is the threshold voltage of M1 and V.sub.T2 is the threshold voltage of M2. In one example, M1 may be a standard V.sub.T device and M2 may be a low V.sub.T device. In another example, M1 may be a high V.sub.T device and M2 may be a standard V.sub.T device. In yet another example, M1 may be a high V.sub.T device and M2 maybe a low V.sub.T device. As R.sub.var is varied, the amount of level shift is varied. When R.sub.var is very small, the voltage drop IR.sub.var across R.sub.var is small. In this case, most of the current I+I.sub.O flows through M2 because V.sub.T2 is lower, and M1 is nearly OFF. In this case, the level shift is determined by the gate-to-source voltage V.sub.GS2 of M2:

(56) $\begin{array}{cc}{V}_{LS}=V_{GS2}+{\mathrm{IR}}_{var}{V}_{GS2}=V_{T2}+\sqrt{\frac{2\left(I+I_O\right)}{{}_n{C_{\mathrm{OX}}\left(\frac{W}{L}\right)}_2}}& \left(16\right)\end{array}$
where V.sub.GS2 is the gate-to-source voltage of M2, and

(57) ${\left(\frac{W}{L}\right)}_2$
is tne W over L ratio of M2. The output resistance is determined by g.sub.m2 of M2:

(58) $\begin{array}{cc}{R}_o\frac{1}{g_{m2}}+R_{var}\frac{1}{g_{m2}}& \left(17\right)\end{array}$

(59) On the other hand, if R.sub.var is very large, most of the bias current I is steered to M1, and M2 is nearly OFF. In this case, the level shift is determined by the gate-to-source voltage V.sub.GS1 of M1:

(60) $\begin{array}{cc}{V}_{LS}{V}_{GS1}=V_{T1}+\sqrt{\frac{2\left(I+I_O\right)}{{}_n{C_{\mathrm{OX}}\left(\frac{W}{L}\right)}_1}}& \left(18\right)\end{array}$
where V.sub.GS1 is the gate-to-source voltage of M1,

(61) ${\left(\frac{W}{L}\right)}_1$
is the W over L ratio of M1. The output resistance is determined by g.sub.m1 of M2:

(62) $\begin{array}{cc}{R}_o\frac{1}{g_{m1}}& \left(19\right)\end{array}$
By varying R.sub.var in between these two extremes, the level shift can be varied continuously between the values given in Equations (14) and (16). Therefore, the range of level shift is given by

(63) 0$\begin{array}{cc}{V}_{T2}+\sqrt{\frac{2\left(I+I_O\right)}{{}_n{C_{\mathrm{OX}}\left(\frac{W}{L}\right)}_2}}{V}_{\mathrm{LS}}{V}_{T1}+\sqrt{\frac{2\left(I+I_O\right)}{{}_n{C_{\mathrm{OX}}\left(\frac{W}{L}\right)}_1}}& \left(20\right)\end{array}$
Again, the variable resistor R.sub.var can be implemented by an NMOS transistor as shown in FIG. 10 or by a PMOS transistor as shown in and FIG. 11.

(64) The adjustability, which is the difference between the upper and lower bounds of the level shift is given by

(65) $\begin{array}{cc}{V}_{\mathrm{LS}}{V}_{T1}-V_{T2}+\sqrt{\frac{2\left(I+I_O\right)}{{}_n{C_{\mathrm{OX}}\left(\frac{W}{L}\right)}_1}}-\sqrt{\frac{2\left(I+I_O\right)}{{}_n{C_{\mathrm{OX}}\left(\frac{W}{L}\right)}_2}}& \left(21\right)\end{array}$
If sizes of M1 and M2 are equal, the adjustability reduces to the difference between the threshold voltages:

(66) $\begin{array}{cc}{V}_{\mathrm{LS}}{V}_{T1}-V_{T2}& \left(22\right)\end{array}$
However, making

(67) ${\left(\frac{W}{L}\right)}_2>{\left(\frac{W}{L}\right)}_1$
gives wider adjustability. In addition, if transistors with different threshold voltages are not available, V.sub.T1 and V.sub.T2 are equal, unequal sizing between M1 and M2 gives the adjustability of

(68) $\begin{array}{cc}{V}_{\mathrm{LS}}\sqrt{\frac{2\left(I+I_O\right)}{{}_n{C}_{\mathrm{OX}}\left\{{\left(\frac{W}{L}\right)}_1+{\left(\frac{W}{L}\right)}_2\right\}}}-\sqrt{\frac{2\left(I+I_O\right)}{{}_n{C_{\mathrm{OX}}\left(\frac{W}{L}\right)}_2}}& \left(23\right)\end{array}$

(69) FIG. 12 illustrates another embodiment of the present invention. It comprises a FSF with a parallel connection of a first source follower M1 and a second source follower M2 with a series variable resistor R.sub.VAR. Preferably, M1 and M2 have two different threshold voltages such that V.sub.T1>V.sub.T2, where V.sub.T1 is the threshold voltage of M1 and V.sub.T2 is the threshold voltage of M2. In one example, M1 may be a standard V.sub.T device and M2 may be a low V.sub.T device. In another example, M1 may be a high V.sub.T device and M2 may be a standard V.sub.T device. In yet another example, M1 may be a high V.sub.T device and M2 maybe a low V.sub.T device. As R.sub.var is varied, the amount of level shift is varied. When R.sub.var is very small, the voltage drop IR.sub.var across R.sub.var is small. In this case, most of the current I flows through M2, and M1 is nearly OFF. In this case, the level shift is determined by the gate-to-source voltage V.sub.GS2 of M2:

(70) $\begin{array}{cc}{V}_{\mathrm{LS}}=V_{\mathrm{GS}2}+{\mathrm{IR}}_{\mathrm{var}}{V}_{\mathrm{GS}2}=V_{T2}+\sqrt{\frac{2I}{{}_n{C_{OX}\left(\frac{W}{L}\right)}_2}}& \left(24\right)\end{array}$
where V.sub.GS2 is the gate-to-source voltage of M2,

(71) ${\left(\frac{W}{L}\right)}_2$
is the W over L ratio of M2. The output resistance is significantly reduced by the factor of g.sub.m2r.sub.o1 by the negative feedback provided by M3 as in the FSF, and is given by:

(72) $\begin{array}{cc}{R}_o\frac{\frac{1}{g_{m2}}+R_{var}}{g_{m3}{r}_{o1}}\frac{1}{g_{m3}{r}_{o1}{g}_{m2}}& \left(25\right)\end{array}$

(73) On the other hand, if R.sub.var is very large, most of the bias current I is steered to M1, and M2 is nearly OFF. In this case, the level shift is determined by the gate-to-source voltage V.sub.GS1 of M1:

(74) $\begin{array}{cc}{V}_{\mathrm{LS}}{V}_{\mathrm{GS}1}=V_{T1}+\sqrt{\frac{2I}{{}_n{C_{\mathrm{OX}}\left(\frac{W}{L}\right)}_1}}& \left(26\right)\end{array}$
where V.sub.GS1 is the gate-to-source voltage of M1,

(75) ${\left(\frac{W}{L}\right)}_1$
is the W over L ratio of M1. The output resistance is given by:

(76) 0$\begin{array}{cc}{R}_o\frac{1}{g_{m3}{r}_{o1}{g}_{m1}}& \left(27\right)\end{array}$

(77) By varying R.sub.var in between these two extremes, the level shift can be varied continuously between the values given in Equations (14) and (16). Therefore, the range of level shift is given by

(78) $\begin{array}{cc}{V}_{T2}+\sqrt{\frac{2I}{{}_n{C_{\mathrm{OX}}\left(\frac{W}{L}\right)}_2}}{V}_{\mathrm{LS}}{V}_{T1}+\sqrt{\frac{2I}{{}_n{C_{\mathrm{OX}}\left(\frac{W}{L}\right)}_1}}& \left(28\right)\end{array}$
Again, the variable resistor R.sub.var can be implemented by an NMOS transistor or a PMOS transistor, as shown in FIG. 13 and FIG. 14, respectively.

(79) The adjustability, which is the difference between the upper and lower bounds of the level shift is given by

(80) $\begin{array}{cc}{V}_{\mathrm{LS}}{V}_{T1}-V_{T2}+\sqrt{\frac{2I}{{}_n{C_{\mathrm{OX}}\left(\frac{W}{L}\right)}_1}}-\sqrt{\frac{2I}{{}_n{C_{\mathrm{OX}}\left(\frac{W}{L}\right)}_2}}& \left(29\right)\end{array}$

(81) If sizes of M1 and M2 are equal, the adjustability reduces to the difference between the threshold voltages:
V.sub.LS=V.sub.T1V.sub.T2(30)
However, making

(82) ${\left(\frac{W}{L}\right)}_2>{\left(\frac{W}{L}\right)}_1$
gives wider adjustability. In addition, if transistors with different threshold voltages are not available, V.sub.T1 and V.sub.T2 are equal, unequal sizing between M1 and M2 gives the adjustability of

(83) $\begin{array}{cc}{V}_{\mathrm{LS}}\sqrt{\frac{2I}{{}_n{C}_{\mathrm{OX}}\left\{{\left(\frac{W}{L}\right)}_1+{\left(\frac{W}{L}\right)}_2\right\}}}-\sqrt{\frac{2I}{{}_n{C_{\mathrm{OX}}\left(\frac{W}{L}\right)}_2}}& \left(31\right)\end{array}$

(84) FIG. 15 illustrates another embodiment of the present invention. It comprises a source follower with a variable threshold transistor M1. The threshold voltage of M1 is controlled by changing the control voltage V.sub.cont. In one example, the variable threshold transistor M1 is implemented in fully-depleted silicon-on-insulator (FDSOI) technology. The control voltage V.sub.cont is applied to the back-gate voltage of the transistor. The FDSOI technology is superior to bulk CMOS technology for this embodiment because the threshold voltage can be varied by a large amount, by as much as a few hundred millivolts.

(85) FIG. 16 illustrates another embodiment of the present invention. It comprises a FSF with a variable threshold transistor M1. The threshold voltage of M1 is controlled by changing the control voltage V.sub.cont. In one example, the variable threshold transistor M1 is implemented in fully-depleted silicon-on-insulator (FDSOI) technology. The control voltage V.sub.cont is applied to the back-gate voltage of the transistor.

(86) FIG. 17 illustrates a feedback control loop to keep the level shift constant across PVT variations. A difference circuit 500 produces a difference between the level shift V.sub.LS and a reference voltage V.sub.REF. Th reference voltage V.sub.REF is preferably independent of PVT variations. The reference voltage V.sub.REF can be produced, for example, by a bandgap reference source. The difference V.sub.LSV.sub.REF is integrated by an integrator 502. The output of the integrator drives the control voltage V.sub.cont, in the various embodiments of the present invention. In one example, the difference circuit 500 and the integrator 502 are implemented by a differential switched-capacitor integrator shown in FIG. 18. Its operation is controlled by two non-overlapping clock phases, .sub.1 and .sub.2. When .sub.1 is high switches S1 and S2 are ON, and S3 and S4 are OFF. The input voltage and the output voltage of the buffer, the difference of which is equal to V.sub.LS, are sampled across the sampling capacitor C.sub.S during this phase. When .sub.2 is high switches S3 and S4 are ON, and S1 and S2 are OFF, applying the reference voltage V.sub.REF on the lower plate of C.sub.S. It can be shown that the resulting change of the integrator output voltage V.sub.o is given by
V.sub.o=V.sub.INV.sub.OUT=V.sub.LSV.sub.REF(32)
If V.sub.LS is larger than V.sub.REF, the integrator output voltage keeps increasing after each clock cycle by V.sub.o, because V.sub.o is positive. This increases the control voltage V.sub.cont. In the embodiments where the variable resistor is implemented by an NMOS transistor, this reduces R.sub.var, and thus V.sub.LS. Therefore, this negative feedback reduces V.sub.LS such that V.sub.LS=V.sub.REF. In other embodiments, the control voltage needs to be reduced if V.sub.LS is larger than V.sub.REF. In these embodiments, a polarity inversion of the integrator output voltage is necessary. This can be accomplished for example, by using an inverting amplifier coupled to the output of the integrator, or by using a fully-differential integrator.

(87) While various inventive embodiments have been described and illustrated herein, those of ordinary skill in the art will readily envision a variety of other means and/or structures for performing the function and/or obtaining the results and/or one or more of the advantages described herein, and each of such variations and/or modifications is deemed to be within the scope of the inventive embodiments described herein. More generally, those skilled in the art will readily appreciate that all parameters, dimensions, materials, and configurations described herein are meant to be exemplary and that the actual parameters, dimensions, materials, and/or configurations will depend upon the specific application or applications for which the inventive teachings is/are used. Those skilled in the art will recognize, or be able to ascertain using no more than routine experimentation, many equivalents to the specific inventive embodiments described herein. As a specific example, it may be desired to use PMOS input transistors in the amplifier circuits in FIGS. 3-16 instead of the NMOS input transistors as shown in the exemplary figures. Such flipped configurations will be appreciated by those who are skilled in the art. It is, therefore, to be understood that the foregoing embodiments are presented by way of example only and that, within the scope of the appended claims and equivalents thereto, inventive embodiments may be practiced otherwise than as specifically described. Inventive embodiments of the present disclosure are directed to each individual feature, system, article, material, kit, and/or method described herein. In addition, any sensible combination of two or more such features, systems, articles, materials, kits, and/or methods, if such features, systems, articles, materials, kits, and/or methods are not mutually inconsistent, is included within the inventive scope of the present disclosure.

(88) Also, the invention described herein may be embodied as a method. The acts performed as part of the method may be ordered in any suitable way. Accordingly, embodiments may be constructed in which acts are performed in an order different than illustrated, which may include performing some acts simultaneously, even though shown as sequential acts in illustrative embodiments.

(89) The invention should not be considered limited to the particular embodiments described above, but rather should be understood to cover all aspects of the invention as fairly set out in the attached claims. Various modifications, equivalent processes, as well as numerous structures to which the invention may be applicable, will be apparent to those skilled in the art to which the invention is directed upon review of this disclosure. The claims are intended to cover such modifications and equivalents.