CASCADED INTEGRATOR-COMB (CIC) DECIMATION FILTER WITH INTEGRATION RESET TO SUPPORT A REDUCED NUMBER OF DIFFERENTIATORS

Abstract

A cascaded integrator-comb (CIC) decimation filter includes N integrator stages, N1 differentiator stages, and a decimator coupled to receive an integrated signal that is output from the N integrator stage and generate a decimated signal that is input to the N1 differentiator stages. The decimator periodically asserts an integration reset signal. A last integrator stage of the N integrator stages is reset in response to assertion of the integration reset signal.

Claims

1. A cascaded integrator-comb (CIC) decimation filter, comprising: N integrator stages coupled in series; a decimator having an input coupled to receive an integrated signal that is output from the N integrator stages coupled in series; N1 differentiator stages coupled in series and configured to receive a decimated signal that is output from the decimator; wherein the N integrator stages coupled in series include a last integrator stage in the series having an output generating the integrated signal; and wherein the last integrator stage is controlled to be periodically reset.

2. The CIC decimation filter of claim 1, wherein the last integrator stage responds to being periodically reset by accumulating a zero value instead of a delayed value.

3. The CIC decimation filter of claim 1, wherein the N integrator stages operate at a first sampling frequency of an input digital signal and wherein the N1 differentiator stages operate at a second sampling frequency of an output digital signal.

4. The CIC decimation filter of claim 3, wherein the decimator effectuates a rate change from the first sampling frequency to the second sampling frequency.

5. The CIC decimation filter of claim 1, wherein the decimator is configured to periodically assert a reset signal which causes the last integrator stage to be periodically reset.

6. The CIC decimation filter of claim 5, wherein the reset signal is asserted in conjunction with each output of a sample of the decimated signal.

7. The CIC decimation filter of claim 5, wherein the reset signal is asserted at a same rate as a rate change implemented by the decimator.

8. The CIC decimation filter of claim 1, wherein the last integrator stage includes a feedback delay element, and wherein the periodic reset of the last integrator stage causes an output of the feedback delay element to be set to zero.

9. A cascaded integrator-comb (CIC) decimation filter, comprising: N integrator stages coupled in series; a decimator having an input coupled to receive an integrated signal that is output from the N integrator stages coupled in series and configured to periodically output samples of a decimated signal and periodically assert an integration reset signal; and N1 differentiator stages coupled in series and configured to receive the decimated signal that is output from the decimator; wherein the integration reset signal is applied to a last integrator stage of said N integrator stages coupled in series to cause a feedback delay element of the last integrator stage to be reset to zero.

10. The CIC decimation filter of claim 9, wherein said one integrator stage is a last integrator stage of said N integrator stages coupled in series.

11. The CIC decimation filter of claim 9, wherein the N integrator stages operate at a first sampling frequency of an input digital signal and wherein the N1 differentiator stages operate at a second sampling frequency of an output digital signal.

12. The CIC decimation filter of claim 11, wherein the decimator effectuates a rate change from the first sampling frequency to the second sampling frequency.

13. The CIC decimation filter of claim 9, wherein the integration reset signal is asserted in conjunction with each output of a sample of the decimated signal.

14. The CIC decimation filter of claim 9, wherein the integration reset signal is asserted at a same rate as a rate change implemented by the decimator.

15. A method, comprising: integrating samples of an input digital signal to generate an integration signal; decimating samples of the integration signal to generate a decimation signal; differentiating samples of the decimation signal; and periodically resetting the integration signal.

16. The method of claim 15, wherein periodically resetting comprises accumulating a zero value instead of a delayed value.

17. The method of claim 15, further comprising: periodically generating an integration reset signal at a same rate as the samples of the integration signal are being decimated to generate the decimation signal; and wherein periodically resetting comprises resetting the integration signal in response to each integration reset signal.

18. The method of claim 15, wherein integrating operates at a first sampling frequency of the input digital signal and wherein differentiating operates at a second sampling frequency of an output digital signal.

19. The method of claim 18, wherein decimating effectuates a rate change from the first sampling frequency to the second sampling frequency.

20. The method of claim 19, wherein periodically resetting is performed at a same rate as the rate change.

21. The method of claim 15, wherein periodically resetting comprises resetting a feedback delay signal of an integration operation to zero.

22. The method of claim 21, wherein the feedback delay signal is reset to zero in response to each decimated signal sample output.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0019] For a better understanding of the embodiments, reference will now be made by way of example only to the accompanying figures in which:

[0020] FIG. 1 shows a schematic view of a conventional N-stage cascaded integrator-comb (CIC) decimation filter;

[0021] FIG. 2 shows a schematic view of a conventional integrator stage within the CIC decimation filter of FIG. 1;

[0022] FIG. 3 shows a schematic view of a conventional differentiator stage within the CIC decimation filter of FIG. 1;

[0023] FIG. 4 graphically illustrates operation of the CIC decimation filter of FIG. 1;

[0024] FIG. 5 shows a schematic view of an improved N-stage cascaded integrator-comb (CIC) decimation filter with a reduced number of differentiators;

[0025] FIG. 6 graphically illustrates operation of the CIC decimation filter of FIG. 5; and

[0026] FIG. 7 shows a schematic view of a last integrator stage within the CIC decimation filter of FIG. 5.

DETAILED DESCRIPTION

[0027] Reference is now made to FIG. 5 which shows a schematic view of an N-stage cascaded integrator-comb (CIC) decimation filter 50. While the conventional CIC decimation filter 10 as shown in FIG. 1 includes an equal number of stages of integrators 12 and differentiators (or combs) 16, the CIC decimation filter 50 as shown in FIG. 5 is instead implemented with an unequal number of stages. More specifically, the CIC decimation filter 50 includes N integration stages and N1 differentiation stages. The integration stages are provided by N integrators 52(1) to 52(N) and the differentiation stages are provided by N1 differentiators 56(1) to 56(N1).

[0028] The N stages of integrators 52(1) to 52(N) are connected in cascade series with the (first) integrator 52(1) in the string having an input configured to receive an input signal IN (where the input signal IN is a digital signal and the integrators operate at a sampling frequency of the input digital signal). The output of the integrator 52(1) is coupled to the input of the next integrator 52(2) stage in the string, and this connectivity is repeated across the string of included integrators. The output of the (last) integrator 52(N) stage in the string produces an integration signal 60 that is applied to the input of a rate changer in the form of a decimator 54 (also referred to in the art as a down-sampler). The decimator 54 operates to decimate the integration signal 60 and generate a decimated signal 62. As an example, the decimator 54 may select for output as the decimated signal 62 every D-th sample of the integration signal 60 so as to provide a down sampling rate of D. The N1 stages of differentiators 56(1) to 56(N1) are connected in cascade series with the (first) differentiator 56(N1) stage in the string having an input configured to receive the decimated signal 62. The output of the differentiator 56(N1) is coupled to the input of the next differentiator 56(N2) stage in the string, and this connectivity is repeated across the string of included differentiators. The output of the (last) differentiator 56(1) stage in the string produces an output signal OUT which is the result of filtering the input signal IN (where the output signal OUT is a digital signal and the differentiators operate at a sampling frequency of the output digital signal). The down sampling rate of D effectuates the rate change from the sampling frequency of the input digital signal to the sampling frequency of the output digital signal.

[0029] Each integrator 52, except for the last integrator 52(N), may be implemented as shown schematically in FIG. 2 with respect to integrator 12. FIG. 7 shows a schematic view of the last integrator 52(N). The last integrator 52(N) is substantially the same as the integrator 12 of FIG. 2, except that the delay element 38 is resettable to zero in response to a reset signal 70. In response to assertion of the reset signal 70, the feedback delay signal 34 is set to zero, and thus the output of the adder 30 when this occurs would be zero plus the input signal 32.

[0030] Each differentiator 56 may be implemented as shown schematically in FIG. 3 with respect to differentiator 16.

[0031] The reset signal 70 is generated by the decimator 54 once every D counts of the decimation operation. In other words, the reset signal 70 is asserted each time the decimator 54 outputs a new sample of the decimated signal 62. In response to the assertion of the reset signal 70, the last integrator 52(N) is reset and the integration signal 60 output from the last integrator 52(N) has a feedback delay contribution of zero. The implementation of the reset operation may be accomplished, as discussed herein with respect to an integrator of the type shown in FIG. 7, by resetting a data register associated with the feedback loop of the integrator 52(N) to zero so that next sample of the integration signal 60 is zero plus the output of the (N1)-th integrator in the string.

[0032] It will be noted that the last integrator 52(N) in the string has a non-modulo implementation which is different from the modulo integrator operation of the integrators 12 of the CIC decimation filter 10 of FIG. 1. The resetting of the last integrator 52(N) every D-th samples will preclude an overflow from occurring.

[0033] Let XNin be the signal at the input of the first integrator 52 in the string, and let n be the index of the samples of the signal x. XNin may be represented as:

XNin=x(0), x(1), x(2), . . . , x(n), . . . , x(n+k),

[0034] Let XNint be the integration signal 60 at the output of the last integrator 52(N). It will be remembered that the last integrator 52(N) is reset once every D counts. XNint may be represented as:

[0035] For counts 0 to D; XNint=x(0), x(0)+x(1), x(0)+x(1)+x(2), . . . , x(0)+x(1)+ . . . +x(D)

[0036] For counts D+1 to 2D; XNint=x(D+1), x(D+1)+x(D+2), x(D+1)+x(D+2)+x(D+3), . . . , x(D+1)+x(D+2)+ . . . +x(2D).

[0037] For counts 2D+1 to 3D; XNint=x(2D+1), x(2D+1)+x(2D+2), x(2D+1)+x(2D+2)+x(2D+3), . . . , x(2D+1)+x(2D+2)+ . . . +x(3D). And so on.

[0038] Let XND be the decimated signal 62 at the output of the decimator 54. The decimator 54 functions to output every D-th sample of the signal XNint, which would represent the integration signal 20 at the samples where n=0, D, 2D, . . . .

XND=X(0), X(D), X(2D),

[0039] where:

X(0)=XNint(0)=x(0),

X(D)=XNint(D)=x(1)+ . . . +x(D),

X(2D)=XNint(2D)=x(D+1)+x(D+2)+ . . . +x(2D),

X(3D)=XNint(3D)=x(2D+1)+x(2D+2)+ . . . +x(3D),

[0040] and so on.

[0041] This may also be represented as follows:

XND=.sub.n=0.sup.Dx(n)x(0), .sub.n=D.sup.2Dx(n).sub.n=0.sup.Dx(n),

[0042] Notably, this XND output is equal to the XNout output from the first differentiator 16(N) of the of the CIC decimation filter 10 of FIG. 1.

[0043] The foregoing may be graphically represented as shown in FIG. 6. The graph very generally shows an example of the accumulated values of the last integrator 52(N) in the string at reference 72. The integration operation is reset every D-th sample and the integration starts over again from the current input signal value. Because of this, the last integrator 52(N) output will always represent the difference between consecutive D-th samples. It will be recalled that the calculation of this different is the function performed by the first differentiator 16(N) of the CIC decimation filter 10 of FIG. 1. Due to the resetting of the last integrator 52(N) as provided by the CIC decimation filter 50 of FIG. 5, it is possible to eliminate the need for the first differentiator 16(N) in the conventional CIC decimator filter 10 and this is why the CIC decimation filter 50 of FIG. 5 includes only (N1) differentiators 56.

[0044] It will be noted that the example shown in FIG. 7 is correct for the case of a monotonically rising input signal only. This is, of course, just one of many possibilities (rising, falling, mixed, etc.) and thus is only an example presented to illustrate the concept of the effect of periodically resetting the last integrator.

[0045] The implementation of the CIC decimation filter 50 of FIG. 5 provides a number of advantages over prior art CIC implementations. The advantages include: a) there is no need for an extra data path; b) there is no control penalty; c) the circuit occupies less space and operates at a reduced power level; d) there is support for multiple decimation rate modes (i.e., D can be programmed to any value without area penalty as only the time of reset is being altered and the remainder of the circuit stays the same); e) there is an elimination of one differentiator in comparison to prior art CIC filters; and f) performance is identical to the prior art CIC filter at least because the system transfer function is same.

[0046] The system of FIG. 5 can be implemented in any suitable hardware, software, firmware, or a combination thereof, without departing from the scope of the invention.

[0047] The system may include a processor and a memory, the memory having the computer executable instructions for executing a process for implementing the CIC filtering operation. The computer executable instructions, in whole or in part, may also be stored on a computer readable medium separated from the system on which the instructions are executed. The computer readable medium may include any volatile or non-volatile storage medium such as flash memory, compact disc memory, and the like.

[0048] While the invention has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are considered illustrative or exemplary and not restrictive; the invention is not limited to the disclosed embodiments. Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims.