Method for compiling a quantum circuit on a trapped-ion quantum processor

Abstract

A method for compiling a quantum circuit on a trapped-ion quantum processor includes: obtaining a quantum circuit containing a first predetermined category of two-qubit quantum gates, and/or one-qubit quantum gates; a separation of the quantum circuit into local layers, and entangling layers; compiling the local layers; compiling the entangling layers, separate from the step of compiling the local layers, transforming the quantum gates of those entangling layers so that they contain only collective or entangling N-qubit quantum gates of a third predetermined category, one-qubit quantum gates of a fourth predetermined category; and a step of grouping together the compiled local layers and the compiled entangling layers into a compiled quantum circuit.

Claims

1. A method for compiling a quantum circuit comprising a number of qubits greater than 10, preferably greater than 20, and preferably greater than 30, on a trapped-ion quantum processor, comprising: potentially a prior step of transforming the quantum circuit so that the quantum circuit no longer contains anything except at least one of: a first predetermined category of two-qubit quantum gates, one-qubit quantum gates, a step of separating said quantum circuit into: local layers comprising only one-qubit quantum gates, entangling layers comprising only at least one of: two-qubit quantum gates of the first category, one-qubit quantum gates of a second predetermined category, a step of compiling the local layers, a step of compiling the entangling layers, separate from the step of compiling the local layers, the step of compiling the entangling layers transforming the quantum gates of those entangling layers so that they contain only: collective or entangling N-qubit quantum gates of a third predetermined category, one-qubit quantum gates of a fourth predetermined category, a step of grouping together the compiled local layers and the compiled entangling layers into a compiled quantum circuit.

2. The method for compiling a quantum circuit on a trapped-ion quantum processor according to claim 1, wherein the step of compiling the entangling layers also transforms the quantum gates of those entangling layers so that: all or at least some of those collective or entangling quantum gates simultaneously apply to at least three qubits, advantageously simultaneously apply to the majority of qubits, and even more advantageously simultaneously apply to all the qubits.

3. The method for compiling a quantum circuit on a trapped-ion quantum processor according to claim 2, wherein the step of compiling the entangling layers comprises: a breakdown of each entangling layer into a phase polynomial, a direct recomposition in the form of quantum gates of the third category and the fourth category of quantum gates without going through a form of quantum gates of the first category of quantum gates.

4. The method for compiling a quantum circuit on a trapped-ion quantum processor according to claim 2, wherein the step of compiling the local layers comprises: a breakdown of each local matrix of a local layer into a sequence of quantum gates with a rotation along the Z-axis, a rotation along the X-axis, and a rotation along the Z-axis, a sub-breakdown of the rotation along the X-axis into a sequence of Hadamard quantum gates, with a Hadamard rotation along the Z-axis, a sub-sub-breakdown of the Hadamard gate into a sequence of quantum gates with a rotation along the Z-axis, a rotation along the X-axis, and a rotation along the Z-axis, all three rotations having an angle of pi or pi/2, a sharing between qubits, of rotation gates along the X-axis with an angle of pi/2.

5. The method for compiling a quantum circuit on a trapped-ion quantum processor according to claim 2, further comprising: a prior step of transforming the quantum circuit so that it no longer contains anything except at least one of: a first predetermined category of two-qubit quantum gates, and/or one-qubit quantum gates.

6. The method for compiling a quantum circuit on a trapped-ion quantum processor according to claim 2, wherein, during the step of compiling the entangling layers: the number of collective or entangling quantum gates of the third category of quantum gates in the compiled entangling layers is minimized as a priority relative to the minimization of the quantum gates of the fourth category.

7. The method for compiling a quantum circuit on a trapped-ion quantum processor according to claim 2, wherein: the first predetermined category of two-qubit quantum gates comprises: diagonal two-qubit quantum gates, CNOT quantum gates, the second predetermined category of one-qubit quantum gates comprises: diagonal one-qubit gates, the third predetermined category of collective or entangling N-qubit quantum gates comprises: Molmer-Sorensen N-qubit entangling gates, collective gates rotating along the X-axis, the fourth predetermined category of one-qubit quantum gates comprises: local phase shifts along the Z-axis.

8. The method for compiling a quantum circuit on a trapped-ion quantum processor according to claim 1, wherein the step of compiling the entangling layers comprises: a breakdown of each entangling layer into a phase polynomial, a direct recomposition in the form of quantum gates of the third category and the fourth category of quantum gates without going through a form of quantum gates of the first category of quantum gates.

9. The method for compiling a quantum circuit on a trapped-ion quantum processor according to claim 8, wherein the step of compiling the local layers comprises: a breakdown of each local matrix of a local layer into a sequence of quantum gates with a rotation along the Z-axis, a rotation along the X-axis, and a rotation along the Z-axis, a sub-breakdown of the rotation along the X-axis into a sequence of Hadamard quantum gates, with a Hadamard rotation along the Z-axis, a sub-sub-breakdown of the Hadamard gate into a sequence of quantum gates with a rotation along the Z-axis, a rotation along the X-axis, and a rotation along the Z-axis, all three rotations having an angle of pi or pi/2, a sharing between qubits, of rotation gates along the X-axis with an angle of pi/2.

10. The method for compiling a quantum circuit on a trapped-ion quantum processor according to claim 8, further comprising: a prior step of transforming the quantum circuit so that it no longer contains anything except at least one of: a first predetermined category of two-qubit quantum gates, and/or one-qubit quantum gates.

11. The method for compiling a quantum circuit on a trapped-ion quantum processor according to claim 8, wherein, during the step of compiling the entangling layers: the number of collective or entangling quantum gates of the third category of quantum gates in the compiled entangling layers is minimized as a priority relative to the minimization of the quantum gates of the fourth category.

12. The method for compiling a quantum circuit on a trapped-ion quantum processor according to claim 8, wherein: the first predetermined category of two-qubit quantum gates comprises: diagonal two-qubit quantum gates, CNOT quantum gates, the second predetermined category of one-qubit quantum gates comprises: diagonal one-qubit gates, the third predetermined category of collective or entangling N-qubit quantum gates comprises: Molmer-Sorensen N-qubit entangling gates, collective gates rotating along the X-axis, the fourth predetermined category of one-qubit quantum gates comprises: local phase shifts along the Z-axis.

13. The method for compiling a quantum circuit on a trapped-ion quantum processor according to claim 1, wherein the step of compiling the local layers comprises: a breakdown of each local matrix of a local layer into a sequence of quantum gates with a rotation along the Z-axis, a rotation along the X-axis, and a rotation along the Z-axis, a sub-breakdown of the rotation along the X-axis into a sequence of Hadamard quantum gates, with a Hadamard rotation along the Z-axis, a sub-sub-breakdown of the Hadamard gate into a sequence of quantum gates with a rotation along the Z-axis, a rotation along the X-axis, and a rotation along the Z-axis, all three rotations having an angle of pi or pi/2, a sharing between qubits, of rotation gates along the X-axis with an angle of pi/2.

14. The method for compiling a quantum circuit on a trapped-ion quantum processor according to claim 13, further comprising: a prior step of transforming the quantum circuit so that it no longer contains anything except at least one of: a first predetermined category of two-qubit quantum gates, and/or one-qubit quantum gates.

15. The method for compiling a quantum circuit on a trapped-ion quantum processor according to claim 13, wherein, during the step of compiling the entangling layers: the number of collective or entangling quantum gates of the third category of quantum gates in the compiled entangling layers is minimized as a priority relative to the minimization of the quantum gates of the fourth category.

16. The method for compiling a quantum circuit on a trapped-ion quantum processor according to claim 1, further comprising: a prior step of transforming the quantum circuit so that it no longer contains anything except at least one of: a first predetermined category of two-qubit quantum gates, one-qubit quantum gates.

17. The method for compiling a quantum circuit on a trapped-ion quantum processor according to claim 16, wherein, during the step of compiling the entangling layers: the number of collective or entangling quantum gates of the third category of quantum gates in the compiled entangling layers is minimized as a priority relative to the minimization of the quantum gates of the fourth category.

18. The method for compiling a quantum circuit on a trapped-ion quantum processor according to claim 1, wherein, during the step of compiling the entangling layers: the number of collective or entangling quantum gates of the third category of quantum gates in the compiled entangling layers is minimized as a priority relative to the minimization of the quantum gates of the fourth category.

19. The method for compiling a quantum circuit on a trapped-ion quantum processor according to claim 1, wherein: the first predetermined category of two-qubit quantum gates comprises: diagonal two-qubit quantum gates, CNOT quantum gates, the second predetermined category of one-qubit quantum gates comprises: diagonal one-qubit gates, the third predetermined category of collective or entangling N-qubit quantum gates comprises: Molmer-Sorensen N-qubit entangling gates, collective gates rotating along the X-axis, the fourth predetermined category of one-qubit quantum gates comprises: local phase shifts along the Z-axis.

20. A method for compiling a quantum circuit comprising a number of qubits greater than 10, preferably greater than 20, and preferably greater than 30, on a trapped-ion quantum processor, comprising: a step of breaking down all or some of the quantum circuit into one or more phase polynomials, a step of directly recomposing said all or some of the quantum circuit into the form of entangling Molmer-Sorensen quantum gates without going through the form of CNOT quantum gates, a step of grouping together the recomposed quantum gates to obtain a compiled circuit; returning the compiled quantum circuit.

Description

BRIEF DESCRIPTION OF THE FIGURES

(1) Other features, details, and advantages of the invention will become apparent upon reading the detailed description below and analyzing the attached Figures, in which:

(2) FIG. 1 shows a flowchart of the main steps of a method for compiling a quantum circuit on a trapped-ion quantum processor according to one embodiment of the invention.

(3) FIG. 2a shows a representation of a quantum circuit comprising two-qubit quantum gates of the first predetermined category and one-qubit quantum gates, before the separation of the quantum circuit into local and entangling layers.

(4) FIG. 2b shows a directed acyclic graph of the quantum circuit of FIG. 2b, used in one particular embodiment of the invention to separate the quantum circuit into local and entangling layers.

(5) FIG. 3a shows a pseudo-code for the extraction of the local layers according to one embodiment of the invention.

(6) FIG. 3b shows a pseudo-code for the extraction of the entangling layers according to one embodiment of the invention.

(7) FIG. 4 shows a pseudo-code of a Gaussian elimination used for the recomposition of the entangling layers according to one embodiment of the invention.

(8) FIG. 5 shows an example recomposition of an entangling layer into a quantum circuit comprising only collective or entangling N-qubit quantum gates of a third predetermined category and one-qubit quantum gates of a fourth predetermined category

(9) FIG. 6 shows another example recomposition of an entangling layer into a quantum circuit comprising only collective or entangling N-qubit quantum gates of a third predetermined category and one-qubit quantum gates of a fourth predetermined category.

(10) FIG. 7 shows an example quantum circuit derived from compiling a local layer.

DESCRIPTION OF THE EMBODIMENTS

(11) Reference is now made to FIG. 1, in which the main steps of a method for compiling a quantum circuit on a trapped-ion quantum processor are depicted.

(12) In the step of obtaining S1, a quantum circuit is obtained. The quantum circuit is advantageously composed of two-qubit quantum gates of a first predetermined category of quantum gates, and/or one-qubit quantum gates.

(13) More specifically, the quantum circuit is advantageously composed of CNOT quantum gates and any diagonal two-qubit quantum gates, forming the quantum gates of the first predetermined category, and/or one-qubit quantum gates.

(14) A step of transformation S2 may potentially be applied to the quantum circuit. The step of transformation S2 is applied when the quantum circuit is composed of quantum gates other than those of the first predetermined category or one-qubit quantum gates. The step of transformation S2 comprises a transformation of the quantum circuit in order for that quantum circuit to no longer contain anything except quantum gates of the first predetermined category of quantum gates, and/or one-qubit quantum gates.

(15) In the event that the quantum gate comprises only quantum gates of the first predetermined category of quantum gates, and/or one-qubit quantum gates, the step of separation S3 is implemented directly after the step of obtaining S1.

(16) A step of separation S3 is then implemented. The step of separation S3 comprises the separation of the quantum circuit into local layers and entangling layers. The local layers comprise only one-qubit quantum gates. The entangling layers comprise only two-qubit quantum gates of the first category and/or one-qubit quantum gates of a second category.

(17) The one-qubit quantum gates of the second category are any one-qubit diagonal quantum gates.

(18) The step of separation S3 comprises the generating of a directed acyclic graph associated with the quantum circuit.

(19) FIG. 2a shows one example quantum circuit with three qubits q0, q1 and q2, comprising fourteen quantum operations, i.e. fourteen quantum gates. FIG. 2b shows the directed acyclic graph corresponding to the quantum circuit of FIG. 2a, the directed acyclic graph making it possible to represent the dependencies between the quantum operations. Thus, in that graph, the peaks represent quantum gates 1 to 14, and the crests represent the dependencies between the quantum gates.

(20) FIGS. 2a and 2b are purely illustrative, as a quantum circuit that comprises a far larger number of qubits, such as greater than 10 qubits, preferably greater than 20 qubits, and preferably greater than 30 qubits, can be used. A quantum circuit comprising a much larger number of quantum gates can also be used.

(21) Based on the directed acyclic graph, the separation of the quantum circuit into local layers and entangling layers is performed. More specifically, the separation is done by successively constructing the largest local layer based on the last entangling layer. This is repeated until all the quantum gates are included in one local or entangling layer.

(22) The separation may be done sequentially, i.e. starting with gate 1 and continuing to gate 14.

(23) FIG. 3a shows a pseudo-code implemented for the separation of the circuit into local layers. In that pseudo-code, the function get_succ returns the first gate succeeding the quantum gate g on the qubit q. In other words, the quantum gates succeeding the quantum gate g on the qubit q are grouped into a local layer, as long as those quantum gates are local quantum gates, meaning one-qubit quantum gates.

(24) FIG. 3b shows a pseudo-code implemented for the separation of the circuit into entangling layers. In that pseudo-code, the function get_pred returns the first gate preceding the gate g on the qubit q and the function successors_ent returns the list of entangling quantum gates succeeding g, for all qubits.

(25) In other words, the entangling layers may comprise one-qubit quantum gates, such as diagonal one-qubit quantum gates, in addition to entangling two-qubit quantum gates, which cannot be included in the local layers.

(26) Steps S4 and S5 illustrate the compiling of the entangling layers. Steps S4 and S5 are intended to obtain a quantum circuit that comprises only quantum gates of a third category and of a fourth category of quantum gates. The quantum gates of the third category and of the fourth category of quantum gates correspond to quantum gates that can be executed on a trapped-ion quantum processor.

(27) In particular, the quantum gates of the third category comprise

(28) Molmer-Sorensen N-qubit entangling gates and collective gates rotating along the X-axis. The quantum gates of the fourth category comprise local phase shifts along the Z-axis (or rotating along the Z-axis).

(29) The step of breaking down the entangling layers S4 comprises the breaking down of the entangling layers into phase polynomials.

(30) More specifically, at this stage of the method, the entangling layers comprise only two-qubit quantum gates of the first category and/or one-qubit quantum gates of the second category, meaning CNOT quantum gates and/or diagonal one-qubit quantum gates.

(31) Any circuit containing such quantum gates may be written as follows:
U|x.sub.1 . . . x.sub.n>=e.sub.1n.sup.ip(x . . . x)|h(x.sub.1 . . . x.sub.n>,

(32) Where h is linear and p is of the form:
P(x.sub.i . . . x.sub.n)=σθ.sub.i.f.sub.ix(x.sub.1 . . . x.sub.n),

(33) And where the fi are linear functions.

(34) In order to determine h, a matrix H comprising 0s and 1s, of dimensions N×N is constructed, where N is the number of qubits in the entangling layer. The matrix H is initialized to the identity, meaning as a matrix comprising a diagonal of 1.

(35) In order to determine the linear functions fi, a hash table F is constructed. The hash table F hashes the elements of the matrix H to floats.

(36) A plurality of execution models is then defined. In particular, when reading the quantum gates of the entangling layer, when: the quantum gate is a CNOT quantum gate from the qubit i to the qubit j, then H[j]=H[j] XOR H[i], where XOR corresponds to XOT bit by bit by two sequences of bits, the quantum gate is a rotation along Z by angle a on qubit i, then: F[H[i]] is empty, then F[H[i]]=a, otherwise, F[H[i]]=F[H[i]]+a, the quantum gate is a controlled phase of angle a from qubit i to qubit j, then: F[H[i] XOR H[j]]+=−a/2, F[H[i]]+=a/2, F[H[j]]+=a/2.

(37) Once these execution models have been implemented, the matrix H is broken down into a series of operations corresponding to a sequence of quantum gates using Gaussian elimination.

(38) FIG. 4 shows the pseudo-code implemented for the Gaussian elimination applied to matrix H.

(39) Gaussian elimination makes it possible to obtain a sequence O of operations that break down the matrix H. Each operation in that sequence O is a set of CNOT gates that share the same control qubit. Those gates are commonly called CNOT fan-out gates. Gaussian elimination is applied to each row 0 to N of the matrix H, respectively to each iteration J=0 to J=N−1. By iteratively applying Gaussian elimination to each row of the matrix H, a CNOT fan-out sequence with a linear size equal to N is obtained.

(40) Next, a step of recomposing the entangling layers S5 is performed. This step of recomposing the entangling layers S5 comprises the recomposition of the entangling layers so that they comprise only Molmer-Sorensen entangling quantum gates, collective quantum gates rotating along the X-axis, and quantum gates with local phase shifts along the Z-axis.

(41) This recomposition is performed directly. More specifically, this means that the quantum circuit comprising only Molmer-Sorensen entangling quantum gates, collective quantum gates rotating along the X-axis, and quantum gates with local phase shifts along the Z-axis is obtained directly after the step of breakdown S4, without going through another form of quantum gate (particularly CNOT quantum gates).

(42) Once the CNOT fan-out sequence has been obtained in the step of decomposition S4, a linear number of tables H0, H1, . . . , HN, corresponding to the matrix H at each iteration j=0 to j=N of the Gaussian elimination is obtained.

(43) A plurality of execution models is determined for the step of recomposition. In particular: if a row Hk[j] appears in the matrix F, a Z-rotating quantum gate with angle F[Hk[j]] is added to the qubit j after the iCNOT fan-out number k, If an entry F[b] does not appear anywhere in the sequence of Hi, where Hi belongs to the tables H0, H1, HN: and if there is a table Hk and two qubits c and t such that Hk[c] XOR Hk[t]==b, where b is a chosen table, then phase F[b] is inserted via a heuristic described below, if there is no such table Hk, the phase is inserted at the end of the sequence O of operations such that: a set of CNOT quantum gates sharing the same target qubit (commonly called a CNOT fan-in) is inserted, whose control qubits are all those for which a bit equal to 1 is present in b except for a qubit y, that qubit y being the target qubit, a Z-rotating quantum gate with angle F[b] is inserted on qubit y, insertion of the same CNOT fan-in.

(44) The remaining phases are inserted based on a heuristic using PHASES fan-out quantum gates. A PHASE fan-out is a set of controlled-phase quantum gates of the form:
cos(angle/2)I−isin(angle/2)ZZ

(45) The PHASES fan-outs share the same control qubit. Those PHASES fan-outs are inserted such that: for each phase F[b] there exists k, c, t as above; if c is already being used as a control qubit during insertion of a phase in Hk via a PHASE fan-out, then a phase from c to t with an angle F[b] is inserted into the corresponding PHASE fan-out, otherwise, a new PHASE fan-out with a single phase from c to t where the angle is F[b] is inserted.

(46) The same is done with t, if t is already in use.

(47) FIG. 6 is an example recomposition of a CNOT fan-out quantum gate with two target qubits, into a quantum circuit comprising only Molmer-Sorensen entangling quantum gates, collective quantum gates rotating along the X-axis, and local phase shifts along the Z-axis.

(48) FIG. 7 shows a recomposition of a PHASES fan-out into a quantum circuit comprising only Molmer-Sorensen entangling quantum gates, collective quantum gates rotating along the X-axis, and local phase shifts along the Z-axis.

(49) During the recomposition of the circuits, the number of Molmer-Sorensen entangling gates and collective quantum gates rotating along the X-axis is minimized as a priority, as those gates are the most costly in terms of execution time and accuracy of the quantum circuit.

(50) The number of Molmer-Sorensen entangling gates and collective quantum gates rotating along the X-axis may be constant.

(51) Steps S6 to S9 then illustrate the compiling of local layers. The compiling of the local layers is meant to obtain a quantum circuit comprising only quantum gates rotating along the Z-axis and rotating along the X-axis. Advantageously, the quantum gates rotating along the X-axis are collective, meaning that a quantum gate rotating along the X-axis can be shared among multiple qubits of the quantum circuit, and even more advantageously among all qubits.

(52) The compiling of the local layers comprises a step of breaking down the local layers S6. The step of breaking down the local layers S6 comprises a calculation of the local matrices U to be applied to each qubit. Those local matrices U are broken down into quantum gates rotating along the X-axis, along the Z-axis and along the X-axis. The ZXZ breakdown makes it possible to obtain three angles a, b and c such that: U=Rz(a)Rx(b)Rz(c), where Rz and Rx correspond to the one-qubit rotations around the Z and X axes.

(53) A first step of sub-breakdown S7 is then implemented. The first step of sub-breakdown S7 comprises the sub-breakdown of the quantum gates rotating along the X-axis into Hadamard P quantum gates, with a Hadamard rotation along the Z-axis. P

(54) Next, a second step of sub-breakdown S8 is implemented. The second step of sub-breakdown S8 uses the identity Rx(b)=P Rz(b), where P is a Hadamard gate, and P=Rz(pi/2) Rx(pi/2) Rz(pi/2). Each local matrix may thereby be formulated as follows:
U=Rz(a+pi/2)Rx(pi/2)Rz(b+pi)Rx(pi/2)Rz(c+pi/2)

(55) Finally, a step of sharing S9 is implemented. The step of sharing collectivizes the quantum gates rotating along the X-axis to all qubits. This is because the Rx in the formula do not depend on the local matrix U because they are of the fixed angle pi/2. Thus, based on each local matrix U1 . . . UN, a quantum circuit comprising gates rotating along the Z axis and collective gates rotating along the X axis may be obtained, as shown in FIG. 8.

(56) The method for compiling according to the invention comprises a step of grouping S10, during which the compiled local and entangling layers are concatenated to obtain the quantum circuit that can be compiled on the trapped-ion quantum processor.

(57) That quantum circuit therefore comprises only gates that can be executed by the trapped-ion quantum processor. More specifically, that quantum circuit comprises collective quantum gates rotating along the X-axis, Molmer-Sorensen entangling quantum gates, and quantum gates with local phase shifts along the Z-axis.

(58) An additional step of reducing the size of the quantum circuit may also be performed. In particular, at most two quantum gates collectively rotating along the X-axis may follow each other without redundancies. It is thereby possible to merge quantum circuits containing more than two collective rotations along the X-axis and then break them down again using a method chosen beforehand, thereby producing a more concise compilable quantum circuit.

(59) As an example, a comparison table showing the results of the various methods of the prior art compared with the results of the method according to the invention is described below.

(60) TABLE-US-00001 TABLE 1 Circuit Method (1) Method (2) Method (3) Method (4) QFA-5 30 23 52 36 QFA-10 135 53 112 76 QFA-15 315 83 172 116 QFA-20 570 113 232 156 QFA-n 3{circumflex over ( )}(n(n-1)/2) 6n-7 12n-8 8n-4 QFT-5 10 7 16 16 QFT-10 45 17 36 36 QFT-15 105 27 56 56 QFT-20 190 37 76 76 QFT-n n(n-1)/2 2n-3 4n-4 4n-4

(61) The first column, “method (1)”, shows the results of the first prior art described. The second column, “method (2)”, shows the results of the first prior art described, wherein the compilation is done manually, by making reductive assumptions such as the semi-locality of the Molmer-Sorensen gates or the reduction of the force of interaction between the qubits during the application of a Molmer-Sorensen gate. The third column, “method (3)”, corresponds to the same implementation, without the reductive assumptions described above. The fourth column, “method (4)”, corresponds to the method according to the invention.

(62) The result means the number of quantum gates comprised within the quantum circuit compiled by the corresponding method.

(63) The first row corresponds to an implementation of a quantum Fourier transform on a quantum circuit with 5, 10, 15, 20 qubits. The next row corresponds to that same implementation for a quantum circuit with n qubits.

(64) The third row corresponds to an implementation of a quantum Fourier adder on a quantum circuit with 5, 10, 15, 20 qubits. The next row corresponds to that same implementation for a quantum circuit with n qubits.

(65) It therefore appears that the quantum circuits compiled by the first method comprise an exponential number of quantum gates, thereby increasing the execution time and reducing the accuracy of the circuit.

(66) Additionally, the results from columns 2 and 3 cannot be verified by experimentation, given that the method is manual.

(67) Thus, the method according to the invention makes it possible to generate more concise quantum circuits than those generated by the prior art, while offering a fully automated method.

LIST OF DOCUMENTS CITED

Non-patent Literature

(68) For all useful purposes, the following non-patent element(s) has/have been cited:

(69) nplcitl1: Compiling quantum algorithms for architectures with multi-qubit gates, Martinez et al;

(70) nplcit2: Basic circuit compilation techniques for an ion-trap quantum machine, Maslov and Use of global interactions in efficient quantum circuit constructions, Maslov and Nam.