Component carrier with blind hole filled with an electrically conductive medium and fulfilling a minimum thickness design rule

Abstract

A component carrier with a stack including an electrically insulating layer structure and an electrically insulating structure has a tapering blind hole formed in the stack and an electrically conductive plating layer extending along at least part of a horizontal surface of the stack outside of the blind hole and along at least part of a surface of the blind hole. A minimum thickness of the plating layer at a bottom of the blind hole is at least 8 μm. A demarcation surface of the plating layer in the blind hole and facing away from the stack extends laterally outwardly from the bottom of the blind hole towards a lateral indentation and extends laterally inwardly from the indentation up to an outer end of the blind hole. An electrically conductive structure fills at least part of a volume between the plating layer and an exterior of the blind hole.

Claims

1. A component carrier, comprising: a stack comprising at least one electrically conductive layer structure and/or at least one electrically insulating layer structure; a tapering blind hole formed in the stack; and an electrically conductive plating layer extending along at least part of a horizontal surface of the stack outside of the blind hole and along at least part of a surface of the blind hole; wherein a minimum thickness of the plating layer at a bottom of the blind hole is at least 8 μm, wherein a demarcation surface of the plating layer in the blind hole and facing away from the stack extends laterally outwardly from the bottom of the blind hole towards a lateral indentation and then extends laterally inwardly from the indentation up to an outer end of the blind hole, wherein an electrically conductive structure filling at least part of a volume between the plating layer and an exterior of the blind hole.

2. The component carrier according to claim 1, comprising one of the following features: wherein a ratio between a minimum thickness of the plating layer on the horizontal surface of the stack and the minimum thickness of the plating layer at the bottom of the blind hole is in a range between 15% and 40%; wherein a ratio between a minimum thickness of the plating layer on the horizontal surface of the stack and the minimum thickness of the plating layer at the bottom of the blind hole is in a range between 20% and 60%; wherein a ratio between a minimum thickness of the plating layer on the horizontal surface of the stack and the minimum thickness of the plating layer at the bottom of the blind hole is in a range between 20% and 85%.

3. The component carrier according to claim 1, wherein a part of the electrically conductive plating layer is formed along and on at least part of a horizontal surface of the electrically conductive layer structure outside of the blind hole and extending along at least part of the surface of the blind hole.

4. The component carrier according to claim 1, wherein the component carrier comprises at least one of the following features: wherein the minimum thickness of the plating layer at the bottom of the blind hole is at least 25 μm, and wherein the minimum thickness of the plating layer at the bottom of the blind hole is in a range between 8 μm and 12 μm.

5. The component carrier according to claim 1, wherein the bottom of the blind hole is at least partially delimited by one of the at least one electrically conductive layer structure.

6. The component carrier according to claim 1, wherein one of the at least one electrically conductive layer structure: has a window defining an outer end of the blind hole; and/or defines at least part of the horizontal surface of the stack outside of the blind hole.

7. The component carrier according to claim 1, wherein a minimum thickness of the plating layer on the horizontal surface of the stack is in a range between 2 μm and 3 μm.

8. The component carrier according to claim 1, comprising an electrically conductive seed layer lining at least part of the blind hole and being arranged between the stack and the plating layer.

9. The component carrier according to claim 1, comprising at least one of the following features: wherein a diameter of an outer end of the blind hole is not more than 100 μm; wherein a diameter of the bottom of the blind hole is in a range between 50 μm and 80 μm.

10. The component carrier according to claim 1, comprising at least one of the following features: wherein the electrically insulating layer structure is a core; wherein the plating layer also covers at least part of sidewalls of the stack delimiting the blind hole.

11. The component carrier according to claim 1, wherein the electrically conductive structure comprises at least one further plating structure or layer.

12. The component carrier according to claim 1, wherein the electrically conductive structure comprises a dip at an upper side of the component carrier above the blind hole.

13. The component carrier according to claim 1, wherein the electrically conductively structure comprises fills the blind hole completely.

14. The component carrier according to claim 1, comprising at least one of the following features: wherein the plating layer forms an electrically conductive trace for contacting at least one component being surface mounted on the component carrier and/or being embedded in the component carrier; wherein the minimum thickness of the plating layer at a bottom of the blind hole is not more than 40 μm; wherein one or more of at least one of the at least one electrically conductive layer structure, the plating layer and the electrically conductive structure is patterned for defining at least one electrically conductive trace; wherein no metal foil is arranged between the electrically insulating layer structure of the stack and the electrically conductive plating layer; wherein the electrically conductive plating layer is a curved layer not extending entirely horizontally but extending with two edges in a cross-sectional view.

15. The component carrier according to claim 1, comprising at least one of the following features: the component carrier comprises at least one component embedded in and/or surface mounted on the component carrier, wherein the at least one component is selected from a group consisting of an electronic component, an electrically non-conductive and/or electrically conductive inlay, a heat transfer unit, a light guiding element, an energy harvesting unit, an active electronic component, a passive electronic component, an electronic chip, a storage device, a filter, an integrated circuit, a signal processing component, a power management component, an optoelectronic interface element, a voltage converter, a cryptographic component, a transmitter and/or receiver, an electromechanical transducer, an actuator, a microelectromechanical system, a microprocessor, a capacitor, a resistor, an inductance, an accumulator, a switch, a camera, an antenna, a magnetic element, a further component carrier, and a logic chip; wherein at least one of the at least one electrically conductive layer structure, the plating layer and the structure comprises at least one of a group consisting of copper, aluminum, nickel, silver, gold, palladium, and tungsten; wherein at least one of the at least one electrically insulating layer structure comprises at least one of a group consisting of reinforced or non-reinforced resin, epoxy resin, or bismaleimide-triazine resin, FR-4, FR-5, cyanate ester, polyphenylene derivate, glass, prepreg material, polyimide, polyamide, liquid crystal polymer, epoxy-based build-up material, polytetrafluoroethylene, a ceramic, and a metal oxide; wherein the component carrier is shaped as a plate; wherein the component carrier is configured as one of a group consisting of a printed circuit board, and a substrate; wherein the component carrier is configured as a laminate-type component carrier.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1, FIG. 2, FIG. 3 and FIG. 4 illustrate cross-sectional views of structures obtained while performing a method of manufacturing a component carrier with a laser blind hole by a laser shot treatment and by subsequently filling the laser blind hole at least partially with electrically conductive filling medium according to an exemplary embodiment of the invention.

(2) FIG. 5 illustrates a schematic cross-sectional view of a component carrier with laser blind hole according to another exemplary embodiment of the invention.

(3) FIG. 6 illustrates a schematic cross-sectional view of a preform of a component carrier with an exposed electrically insulating layer structure in which a laser blind hole is formed according to another exemplary embodiment of the invention.

(4) FIG. 7 illustrates a schematic cross-sectional view of a component carrier according to an exemplary embodiment of the invention formed based on the preform of FIG. 6 by forming a seed layer and subsequently a plating layer.

DETAILED DESCRIPTION OF ILLUSTRATED EMBODIMENTS

(5) The illustrations in the drawings are schematically presented. In different drawings, similar or identical elements are provided with the same reference signs.

(6) FIG. 1 to FIG. 4 illustrate cross-sectional views of structures obtained during carrying out methods of manufacturing a component carrier 100, shown in FIG. 4, with a laser blind hole 113 by a laser shot treatment from a top side and by subsequently filling the laser blind hole 113 with electrically conductive filling medium formed by multiple filling procedures according to an exemplary embodiment of the invention.

(7) FIG. 1 shows a laminated layer stack 145 comprising electrically conductive layer structures 152, 161 and an electrically insulating layer structure 102.

(8) First electrically conductive layer structure 152 is arranged on an upper main surface 104 of electrically insulating layer structure 102. Second electrically conductive layer structure 161 is embedded in an interior of the electrically insulating layer structure 102, i.e. between the upper main surface 104 and a lower main surface 106 of electrically insulating layer structure 102. The first electrically conductive layer structure 152 may be a laminated copper foil. Thus, the first electrically conductive layer structure 152 is a continuous layer. The first electrically conductive layer structure 152 may have a thickness d1 of less than 12 μm, in particular less than 5 μm, for example in a range between 2 μm and 3 μm. The second electrically conductive layer structure 161 may be a patterned copper layer. Hence, the second electrically conductive layer structure 161 is a buried trace. The second electrically conductive layer structure 161 may have a thickness, s, of less than 10 μm, in particular less than 5 μm, for instance in a range between 2 μm and 3 μm.

(9) In the shown embodiment, the electrically insulating layer structure 102 may comprise resin (in particular epoxy resin), optionally comprising reinforcing particles such as glass fibers or glass spheres. For example, the electrically insulating layer structure 102 may be a thin core. For instance, a vertical thickness, D, of the electrically insulating layer structure 102 may be less than 180 μm, in particular less than 110 μm, for instance in a range between 40 μm and 60 μm. With such thin cores, reliability issues are particularly pronounced.

(10) A horizontal surface of stack 145 is denoted with reference numeral 143.

(11) Referring to FIG. 2, a laser blind hole 113 is formed by carrying out a laser shot 115 irradiated onto horizontal surface 143. Laser processing may be carried out by an appropriate laser source, for instance by an excimer laser and/or a carbon dioxide laser.

(12) The laser shot 115 forms a window 114 or through hole extending through the first electrically conductive layer structure 152 on the upper main surface 104 of the electrically insulating layer structure 102. Thus, the first electrically conductive layer structure 152 is provided with window 114 defining an outer end of the blind hole 113. Furthermore, the laser shot 115 removes material of the electrically insulating layer structure 102 below window 114 and thereby exposes the second electrically conductive layer structure 161. The exposed portion of the second electrically conductive layer structure 161 forms a bottom 151 of blind hole 113. In other words, the bottom 151 of the blind hole 113 is delimited by the second electrically conductive layer structures 161. The tapering blind hole 113 is laterally delimited by sidewalls 112.

(13) As shown in FIG. 2 as well, a lateral overhang 155 may be formed between the first electrically conductive layer structure 152 next to the window 114 and the electrically insulating layer structure 102 in which the major portion of the blind hole 113 is formed. Preferably, a dimension, b, of the overhang 155 is no more than 10 μm. This can be adjusted by changing the parameters of the laser shot 115 in terms of energy, duration, etc.

(14) A diameter, L, of the blind hole 113 at an outer end of the blind hole 113 and thus a diameter of window 114 is less than or equal to 100 μm, for instance 80 μm. A smaller diameter, I, of the tapering blind hole 113 at a bottom 151 of the blind hole 113 may be smaller than L, for instance may be 65 μm.

(15) In order to obtain the component carrier 100 shown in FIG. 3, the laser blind hole 113 according to FIG. 2 is made subject to a first procedure of filling it with an electrically conductive medium such as copper.

(16) In order to accomplish this, it is preferable to firstly carry out an electroless deposition procedure to thereby form a thin seed layer 144 of copper covering (in particular after a pre-treatment, for instance with palladium and/or titanium) the sidewalls 112 of the electrically insulating layer structure 102 and the bottom 151 delimiting the laser blind hole 113, as well as covering exposed surface portions of first electrically conductive layer structure 152. This can be seen, for the example of sidewalls 112, in a detail 121 in FIG. 3. A thickness, e, of the seed layer 144 may be for instance 0.5 μm. However, it is also possible that the seed layer 144 has a thickness above 1 μm and/or that several cumulative seed layers are provided. For example, a thickness of a seed layer 144 or a cumulative thickness of a plurality of seed layers may be in a range between 0.5 μm and 5 μm. When multiple seed layers are provided, they may comprise an organic (for instance polymer) layer, a palladium layer, and/or a copper layer.

(17) Subsequently, further electrically conductive material (such as copper) may be deposited on the seed layer 144 by a plating procedure, in particular by galvanic plating. Thus, the sidewalls 112, the bottom wall 151 of the second electrically conductive layer structure 161 as well as the first electrically conductive layer structure 152 are covered by a thicker plating layer 146 of electrically conductive filling medium such as copper. Hence, the shown structure comprises electrically conductive plating layer 146 extending continuously or uninterruptedly along horizontal surface 143 of the stack 145 outside of the blind hole 113 and along an entire exposed surface of the blind hole 113. As shown, the plating layer 146 is formed to be delimited by an upper demarcation surface 118 oriented upwardly. It should be said that it is well-known by a skilled person that the demarcation surface 118 is clearly visible when imaging a cross-section of the component carrier 100. Forming the electrically conductive plating layer 146 may be carried out by galvanic plating, preferably following the formation of the seed layer 144.

(18) In the region of the narrowest portion of the laser blind hole 113, i.e. at bottom 151, a substantially horizontal bridge structure 110 is formed as a portion of the plating layer 146 connecting the opposing sidewalls 112. A concave upper limiting surface of the plating layer 146 corresponds to the demarcation surface 118.

(19) Good results in terms of reliability can be obtained when thickness, d2, of the plating layer 146 at the exterior horizontal surface 143 of the stack 145 is in a range between 2 μm and 3 μm, for instance is 2.5 μm. In the shown embodiment, the plating layer 146 has a homogeneous or at least substantially homogeneous thickness d2 on the horizontal surface 143 of stack 145. When, in other embodiments, the plating layer 146 does not have a homogeneous thickness d2 on the horizontal surface 143 of stack 145, the minimum thickness d2 of the plating layer 146 on the horizontal surface 143 of stack 145 may be in a range between 2 μm and 3 μm.

(20) Even more importantly, the plating layer 146 should have a minimum thickness, d3, at bottom 151 of the blind hole 113 of at least 8 μm. According to FIG. 3, the minimum thickness d3 is a vertical thickness of plating layer 146. When this design rule is fulfilled, a component carrier 100 with a high electric reliability can be obtained. For instance, d3 is in a range between 8 μm and 12 μm or is even at least 25 μm. In the shown embodiment, the thickness of the plating layer 146 within the blind hole 113 is inhomogeneous. In order to promote proper filling of a volume above the plating layer 146 with structure 148, it may be advantageous to prevent plating layer 146 to become excessively thick. For instance, a maximum value of the minimum thickness, d3, of the plating layer 146 on bottom 151 may be limited to 40 μm, if an extremely reliable component carrier 100 is desired. Otherwise, the thickness may be also above 40 μm.

(21) A particularly high reliability can be obtained when a ratio d2/d3 between the minimum thickness d2 of the plating layer 146 on the exterior upper horizontal surface 143 of the stack 145 and the minimum thickness d3 of the plating layer 146 at the bottom 151 of the blind hole 113 is in a range between 20% and 30%, for instance about 25%. When this design rule is fulfilled, regions with high crack risk being denoted with reference numerals 197, 199 in FIG. 3 can be very safely prevented from causing reliability issues.

(22) In the shown embodiment, the plated electrically conductive plating layer 146 extends along the entire exterior upper horizontal surface 143 of the stack 145 and along an entire surface of the blind hole 113.

(23) As shown in FIG. 3, demarcation surface 118 of the plating layer 146 in the blind hole 113 and facing away from the stack 145 extends laterally outwardly from the bottom 151 of the blind hole 113 towards a circumferential lateral indentation 153 and then extends laterally inwardly from the indentation 153 up to an outer end of the blind hole 113. The circumferential indentation 153 may function as a pocket with a moderate undercut to which electrically conductive material may be properly applied.

(24) Experiments have shown that in particular regions 197 and 199 of component carrier 100 may be specifically prone to undesired crack formation. However, analysis have also shown that if the smallest thickness d3 of the plating structure 146 on the bottom 151 is at least 8 μm, the tendency of correct formation can be strongly suppressed. Synergistically, the tendency of crack formation can be suppressed even stronger if additionally, the ratio d2/d3 is about 25%±5%.

(25) Referring to FIG. 4, an electrically conductive structure 148 filling a major part between the demarcation surface 118 and the upper main surface of the component carrier 100 may be formed. This can be done by carrying out one or more further galvanic plating procedures following the previous plating procedure of forming the plating layer 146. Thereby, multiple further plating structures 187, 188, 189 may be formed, as shown in a detail 190, as constituents of structure 148. Thus, the component carrier 100 according to FIG. 4 can be obtained by carrying out one or more further plating procedures. Thereby, the structure 148, which may for instance consist of copper, can be obtained. In the shown embodiment, a small dip 125 remains at an upper side of the shown component carrier 100. In other embodiments, the structure 148 fills the remaining recess above the demarcation surface 118 almost completely. A skilled person will understand that the demarcation surface 118 is clearly visible when imaging a cross-section of the component carrier 100.

(26) In the shown embodiment, the illustrated component carrier 100 can be a laminate-type plate-shaped component carrier 100 such as a printed circuit board (PCB).

(27) FIG. 4 also illustrates that the exterior electrically conductive layer structure 152, the plating layer 146 and the electrically conductive structure 148 are commonly patterned on a horizontal surface of the electrically insulating layer structure 102 outside of the blind hole 113 so as to form a stacked layer sequence forming an electrically conductive trace 198. Thus, at least one electrically conductive trace 198 used for connection purposes can be formed simultaneously with the filling of the blind hole 113.

(28) FIG. 5 illustrates a schematic cross-sectional view of a component carrier 100 with laser blind hole 113 according to another exemplary embodiment of the invention.

(29) In contrast to the embodiment according to FIG. 1 to FIG. 4, a manufacturing procedure for manufacturing the component carrier 100 according to FIG. 5 is carried out without the first electrically conductive layer structure 152 on the exterior main surface 104 of the electrically insulating layer structure 102. In other words, laser drilling may be carried out directly on the dielectric surface of electrically insulating layer structure 102. During the plating procedure described referring to FIG. 3, in a corresponding manufacturing method for obtaining the component carrier 100 shown in FIG. 5 also the exposed dielectric surface of the electrically insulating layer structure 102 is covered with material of the plating structure 146. Thus, it may be dispensable to connect electrically conductive layer structure 152 to the exterior main surface 104 of the electrically insulating layer structure 102 before plating, which renders the manufacturing method simple.

(30) Furthermore, FIG. 5 shows that below a second electrically conductive layer structure 161, a component 191 is embedded in the stack 145 and is electrically connected via the second electrically conductive layer structure 161, plating structure 146, and structure 148 forming a trace. For instance, embedded component 191 can be a semiconductor chip and the second electrically conductive layer structure 161 can be a pad of the component 191.

(31) FIG. 5 also illustrates that the plating layer 146 and the electrically conductive structure 148 are commonly patterned on a horizontal surface 143 of the electrically insulating layer structure 102 outside of the blind hole 113 so as to form a stacked layer sequence forming a further electrically conductive trace 198. Thus, at least one further electrically conductive trace 198 used for connection purposes can be formed simultaneously with the filling of the blind hole 113.

(32) FIG. 6 illustrates a schematic cross-sectional view of a preform of a component carrier 100 with an exposed electrically insulating layer structure 102 in which a laser blind hole 113 is formed according to another exemplary embodiment of the invention. Thus, the upper main surface of the electrically insulating layer structure 102 is not covered by metallic material when forming laser blind hole 113.

(33) FIG. 7 illustrates a schematic cross-sectional view of a component carrier 100 according to an exemplary embodiment of the invention formed based on the preform of FIG. 6 by forming a seed layer 144 and subsequently a plating layer 146 (as shown in detail 194). The plating layer 146 continuously lines the exterior horizontal planar main surface portion of the electrically insulating layer structure 102 as well as the entire surface defining blind hole 113.

(34) It should be noted that the term “comprising” does not exclude other elements or steps and the article “a” or “an” does not exclude a plurality. Also, elements described in association with different embodiments may be combined.

(35) Implementation of the invention is not limited to the preferred embodiments shown in the figures and described above. Instead, a multiplicity of variants is possible which use the solutions shown and the principle according to the invention even in the case of fundamentally different embodiments.