Circuit for calibration measurements, method, computer program, and electronic device

Abstract

A circuit for calibration measurements comprises a first and a second current source arranged to provide current outputs; a resistor connected between the first current source and a reference voltage; a capacitor connected between the second current source and the reference voltage; a discharge switch connected in parallel with the capacitor and arranged to selectively discharge the capacitor; a comparator circuit arranged to compare voltages across the resistor and the capacitor and output a signal when voltage across the capacitor reaches the voltage across the resistor; and a controller having a clock signal input and connected to the output of the comparator circuit. The controller is arranged to control the discharge switch to discharge the capacitor, change state of the switch to enable charging of the capacitor and count clock signal pulses until the comparator provides the signal when voltage across the capacitor reaches the voltage across the resistor, wherein the controller is arranged to determine a calibration measurement from counted number of clock signal pulses. A method, computer program and electronic device are also disclosed.

Claims

1. A circuit for calibration measurements comprising a first and a second current source arranged to provide current outputs; a resistor connected between the first current source and a reference voltage; a capacitor connected between the second current source and the reference voltage; a discharge switch connected in parallel with the capacitor and arranged to selectively discharge the capacitor; a comparator circuit arranged to compare voltages across the resistor and the capacitor and output a signal when a voltage across the capacitor reaches the voltage across the resistor; a controller having a clock signal input and connected to the output of the comparator circuit, wherein the controller is arranged to control the discharge switch to discharge the capacitor, change state of the switch to enable charging of the capacitor and count clock signal pulses until the comparator provides the signal when voltage across the capacitor reaches the voltage across the resistor, wherein the controller is arranged to determine a calibration measurement from counted number of clock signal pulses; and a switching arrangement enabling an alternative connection comprising that the second current source is selectably connected to the resistor instead, and the first current source is selectably connected to the capacitor instead, wherein the controller further is arranged to control enabling of the alternative connection and to make a second determination of counted clock signals for the alternative connection, and the calibration measurement is determined from the two counts of clock signal pulses.

2. The circuit of claim 1, wherein the switching arrangement comprises: a first switch having an input connected to the first current source and arranged to selectively connect the first current source to either a first node connected to a first terminal of the resistor and a first input of the comparator, or a second node connected to a first terminal of the capacitor and a second input of the comparator; and a second switch having an input connected to the second current source and arranged to selectively connect the second current source to either the second node or the first node.

3. The circuit of claim 1, wherein the switching arrangement is also arranged to enable a swap of the comparator inputs with each other.

4. The circuit of claim 3, wherein the switching arrangement comprises a first switch having an input connected to the first current source and a first input of the comparator and arranged to selectively connect the first current source to either a first node connected to a first terminal of the resistor, or a second node connected to a first terminal of the capacitor; and a second switch having an input connected to the second current source and a second input of the comparator and arranged to selectively connect the second current source to either the second node or the first node.

5. The circuit of claim 1, further comprising a filter capacitor connected in parallel with the resistor and arranged to low-pass filter noise caused by the resistor.

6. The circuit of claim 1, wherein a calibration value is determined from the calibration measurement through a look-up table mapping calibration measurements to calibration values.

7. The circuit of claim 1, wherein a calibration value is determined from the calibration measurement through a computing arrangement arranged to compute a ratio between the counted number of clock pulses and a value indicating a number of clock pulses associated with a desired combination of resistance and capacitance.

8. The circuit of claim 7, wherein a compensation value for systematic latency in the circuit is provided, wherein a denominator of the ratio comprises a difference between the counted number of clock pulses and the compensation value.

9. The circuit of claim 7, wherein the resistor has a programmable resistance controlled by a resistor control value, and/or the capacitor has a programmable capacitance controlled by a capacitance control value, wherein the computation arrangement is arranged to adjust the calibration value for the setting of resistor control value and/or capacitor control value at the calibration measurement.

10. The circuit of claim 7, wherein computations by the computation arrangement are made for a plurality of programmable resistor or capacitance values and are stored for each programmable value, wherein the resistor or capacitance value is comprised in the denominator of the ratio.

11. An electronic device comprising a circuit of claim 1.

12. The electronic device of claim 11, being a communication apparatus.

13. A method for a calibration measurement circuit that has: a first and a second current source arranged to provide current outputs; a resistor connected between the first current source and a reference voltage; a capacitor connected between the second current source and the reference voltage; a discharge switch connected in parallel with the capacitor and arranged to selectively discharge the capacitor; a comparator circuit arranged to compare voltages across the resistor and the capacitor and output a signal when a voltage across the capacitor reaches the voltage across the resistor, wherein the method comprises: controlling the discharge switch to discharge the capacitor; clearing a counter; changing a state of the switch to enable charging of the capacitor; counting clock signal pulses until the comparator provides the signal when voltage across the capacitor reaches the voltage across the resistor; determining a calibration measurement from the counted number of clock signal pulses; forming an alternative connection comprising that the second current source is connected to the resistor instead, and the first current source is connected to the capacitor instead; and making a second determination of counted clock signals for the alternative connection, wherein the calibration measurement is determined from the two counts of clock signal pulses.

14. The method of claim 13, wherein the forming of the alternative connection also comprises swapping the comparator inputs with each other.

15. The method of claim 13, comprising determining a calibration value from the calibration measurement through a look-up table mapping calibration measurements to calibration values.

16. The method of claim 13, comprising determining a calibration value from the calibration measurement by computing a ratio between the counted number of clock pulses and a value indicating a number of clock pulses associated with a desired combination of resistance and capacitance.

17. The method of claim 16, comprising providing a compensation value for systematic latency in the circuit, wherein a denominator of the ratio comprises a difference between the counted number of clock pulses and the compensation value.

18. The method of claim 16, wherein the resistor has a programmable resistance controlled by a resistor control value, and/or the capacitor has a programmable capacitance controlled by a capacitance control value, wherein the method comprises adjusting the calibration value for the setting of resistor control value and/or capacitor control value at the calibration measurement.

19. The method of claim 16, comprising computing calibration values for a plurality of programmable resistor or capacitance values; and storing the computed calibration values for each programmable value, wherein the resistor or capacitance value is comprised in the denominator of the ratio.

20. A nontransitory computer readable medium comprising a computer program that comprises computer executable instructions which when executed by a programmable controller of an electronic circuit for performing calibration measurements causes the controller to perform a method for a calibration measurement circuit that has: a first and a second current source arranged to provide current outputs; a resistor connected between the first current source and a reference voltage; a capacitor connected between the second current source and the reference voltage; a discharge switch connected in parallel with the capacitor and arranged to selectively discharge the capacitor; a comparator circuit arranged to compare voltages across the resistor and the capacitor and output a signal when a voltage across the capacitor reaches the voltage across the resistor, wherein the method comprises: controlling the discharge switch to discharge the capacitor; clearing a counter; changing a state of the switch to enable charging of the capacitor; counting clock signal pulses until the comparator provides the signal when voltage across the capacitor reaches the voltage across the resistor; and determining a calibration measurement from the counted number of clock signal pulses; forming an alternative connection comprising that the second current source is connected to the resistor instead, and the first current source is connected to the capacitor instead; and making a second determination of counted clock signals for the alternative connection, wherein the calibration measurement is determined from the two counts of clock signal pulses.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The above, as well as additional objects, features and advantages of the present invention, will be better understood through the following illustrative and non-limiting detailed description of preferred embodiments of the present invention, with reference to the appended drawings.

(2) FIG. 1 illustrates an example of a conventional calibration circuit

(3) FIG. 2 schematically illustrates a circuit for calibration measurements according to an embodiment.

(4) FIG. 3 schematically illustrates a circuit for calibration measurements according to an embodiment.

(5) FIG. 4 schematically illustrates a circuit for calibration measurements according to an embodiment.

(6) FIG. 5 schematically illustrates a circuit for calibration measurements according to an embodiment.

(7) FIG. 6 schematically illustrates a timing diagram and a block diagram.

(8) FIG. 7 is a timing diagram schematically illustrating a measurement using two measurements.

(9) FIG. 8 is a block diagram schematically illustrating a computing arrangement.

(10) FIG. 9 is a flow chart illustrating a method according to an embodiment.

(11) FIG. 10 is a flow chart illustrating a method according to an embodiment.

(12) FIG. 11 is a block diagram schematically illustrating a communication device 1100 according to an embodiment.

(13) FIG. 12 schematically illustrates a computer-readable medium and a processing device.

DETAILED DESCRIPTION

(14) Embodiments of the present invention are based on the following principles:

(15) When a resistor, grounded at one end and having a resistance R, is supplied with a current I.sub.R, the voltage across the resistor is V.sub.R=I.sub.R.Math.R. When an initially discharged capacitor, grounded at one end and having a capacitance C, is supplied with a constant current I.sub.C, the voltage across the capacitor is V.sub.C=(I.sub.C.Math.t)/C, where t denotes the time since the capacitor began to be charged. When I.sub.R=k.Math.I.sub.C the time t for which V.sub.R=V.sub.C is readily derived to be equal to a scaled time constant k.Math.R.Math.C, where k is a scaling factor. If k=1, this time is equal to the RC time constant. Thus, the RC time constant can be measured by measuring the time it takes for the capacitor to be charge to V.sub.C=V.sub.R. Measuring this time can e.g. be done by a counter circuit counting clock pulses of a reference clock signal having a well-defined frequency, such as a clock signal derived directly or indirectly (e.g. using a phase-locked loop) from a crystal oscillator. The detection of the event that V.sub.R=V.sub.C can be made with a voltage comparator, the output of which can be used to instruct the counter to stop counting. This is a comparably fast way of measuring the RC time constant, since in principle, the RC time constant can be measured in a single charge/discharge cycle of the capacitor (although some embodiments presented below make use of two such cycles to compensate for e.g. offset errors and/or current mismatch). Even though manufacturing inaccuracies etc. can make actual RC constants of integrated RC circuits deviate relatively much from nominal values, there is typically a strong correlation between such deviations for RC circuits (using the same types of resistors and capacitors) integrated on the same integrated circuit chip (as opposed to RC circuits integrated on different integrated circuit chips). Thus, if the RC time constant has been measured (e.g. using the principles outlined above) for a reference RC circuit on one chip, this measured RC time constant can be used to relatively accurately tune the RC time constants of other RC circuits on that same chip.

(16) According to embodiments, the currents I.sub.R and I.sub.C can be made equal. Equal should here be construed with practical technical implementation in mind where some deviation may occur due to for example manufacturing process accuracy, temperature gradients, etc. For the sake of easier understanding of principles, the embodiments demonstrated with reference to the figures assume that the currents I.sub.R and I.sub.C are equal. According to other embodiments I.sub.R and I.sub.C are scaled by a factor of k, and computations are then made taking the scaling into account. In other senses, the features demonstrated below apply for these other embodiments.

(17) FIG. 2 schematically illustrates a circuit 200 for calibration measurements according to an embodiment. A first current source 202 and a second current source 203 are arranged to provide equal current outputs. Here, equal should be considered in its technical context, where the two current sources 202, 203 are made to provide as equal current outputs as possible with practical means at hand. As will be demonstrated below, current mirroring techniques can be used for this. Other ways of keeping the output currents as equal as possible are of course also feasible. The first current source 202 provides its current output to a first terminal of a resistor 204 which is connected by a second terminal to a reference voltage, e.g. ground. Similarly, the second current source 203 provides it current output to a first terminal of a capacitor 205 which by a second terminal is also connected to the reference voltage.

(18) Thus, the first current source 202 will provide a current through the resistor 204 wherein a voltage will be created across the resistor 204. The second current source 203 will charge the capacitor 205 which will build up a voltage across the capacitor 205. After a while, the voltage across the capacitor 205 will reach the level of the voltage across the resistor 204. The time for reaching this state will be used for the calibration measurement.

(19) A comparator circuit 206 is connected to respective nodes where the voltages across the resistor 204 and capacitor 205, respectively, are present. Thereby, the comparator circuit 206 is capable to provide an output signal indicating when the voltage across the capacitor 205 reaches the same value as that across the resistor 204. To ensure that the capacitor is discharged when the charging by the second current source 203 commences, a discharging switch 207 is provided in parallel with the capacitor 205. The switch 207 is controlled by a controller 208. The controller 208 also receives the output from the comparator circuit 206 and a clock signal. The controller 208 thus discharges the capacitor 205 by closing the switch 207, opens the switch 207 to enable charging of the capacitor 205 and starts counting clock pulses of the clock signal until the controller receives a signal from the comparator circuit 206 that the capacitor voltage has reached the resistor voltage. A calibration value can then be computed based on the number of counted clock pulses. As will be demonstrated below, the computation can be performed by fairly simple arithmetic computations, but can also be pre-calculated wherein the calibration value is read from a look-up table based on the number of counted clock pulses. As also demonstrated below, the calibration value may be a vector or matrix for different settings of the RC-circuit to be calibrated.

(20) It can thus be seen that the approach provides a fast result since the calibration value is obtainable after one measurement period, i.e. one discharging and charging of the capacitor to resistor voltage and a following arithmetic computation/look-up table access, which provides significantly shorter time than some of the approaches described in the background section. Below, it is described embodiments where two consecutive such measurement periods are made to compensate for comparator offset and/or current mismatch, but these still provide a relatively fast result since the discharging and charging of the capacitor, even if made twice, take relatively little time.

(21) Current through a resistor inherently generates noise. To avoid or at least alleviate the effect of that noise on the input of the comparator 206, a filter capacitor 209 may optionally be connected in parallel with the resistor 204 which then low-pass filters the noise contribution at the input of the comparator 206.

(22) FIG. 3 schematically illustrates a circuit 300 for calibration measurements according to an embodiment. A first current source 302 and a second current source 303 are arranged to provide equal current outputs. Although the two current sources are arranged to provide equal current outputs, there may be a slight difference between the respective currents. A switching arrangement 310 is therefore provided to enable swapping of the two current sources 302, 303 such that a resistor 304 can be subject to any of the current sources 302, 303 and similar that a capacitor 305 can be subject to any of the current sources 302, 303. The measurement is thus made twice (referred to below as the first and the second measurement), i.e. one time with one combination of resistor 304 and capacitor 305 to respective current sources 302, 303, and one time with another combination of the current sources 302, 303 to the resistor 304 and capacitor 305. For example, for the first measurement, the first current source 302 provides its current output to a first terminal of the resistor 304 which by a second terminal is connected to a reference voltage, e.g. ground. This may be provided with a switch 312 of the switching arrangement 310. The second current source 303 simultaneously provides its current output to a first terminal of the capacitor 305 which by a second terminal is also connected to the reference voltage. This may be provided with a switch 313 of the switching arrangement 310. The first measurement is then provided the same way as demonstrated with reference to FIG. 2, i.e. a controller 308 discharges the capacitor 305 by closing a switch 307, opens the switch 307 to enable charging of the capacitor 305 and starts counting clock pulses of the clock signal until the controller receives a signal from a comparator circuit 306 that the capacitor voltage has reached the resistor voltage. For the second measurement, the switches 312, 313 of the switching arrangement are then toggled, and the measurement procedure is performed once again. Thus, for the second measurement, the first current source 302 provides its current output to the first terminal of the capacitor 305, and the second current source 303 provides its current output to the first terminal of the resistor 304. A calibration value can then be computed based on the number of counted clock pulses. The number of clock pulses can then be an aggregate counted clock pulses, or be an average of the two counts, which is essentially in practice only a bit-shift, i.e. division by two, of the aggregate count in a binary representation.

(23) An optional filter capacitor 309 may, similar to what has been demonstrated with reference to FIG. 2, be connected in parallel with the resistor 304. The filter capacitor 309 is dimensioned to filter out high-frequency noise and/or to reduce kickback effect of the comparator.

(24) A further problem may be that the comparator may have an inherent offset between the inputs. This can be combated by swapping the inputs of the comparator as well and make measurements with the different configurations. This can be made by adding switches for the swapping. However, this increases complexity by additional switches, which also may have other unwanted effects if not arranged properly. As demonstrated below, an approach may be used which does not increase complexity compared to the solution demonstrated with reference to FIG. 3, but where swapping of comparator inputs is provided.

(25) FIG. 4 schematically illustrates a circuit 400 for calibration measurements according to an embodiment. Similar to the embodiment demonstrated with reference to FIG. 3, the embodiment of FIG. 4 comprises a first current source 402, a second current source 403, a resistor 404, a capacitor 405, a comparator 406, a discharging switch 407, a controller 408 and a switching arrangement 410. The switching arrangement 410 comprises a first and a second switch 412, 413. The first switch 412 has an input connected to the first current source 402 and a first input of the comparator 406 and is arranged to selectively connect the first current source 402, and thus the first input of the comparator 406, to either a first node connected to a first terminal of the resistor 404, or a second node connected to a first terminal of the capacitor 405. The second switch 413 has an input connected to the second current source 403 and a second input of the comparator 406 and is arranged to selectively connect the second current source 403, and thus the second input of the comparator 406, to either the second node or the first node. By arranging the inputs of the comparator 406 such that the switching arrangement 410 is between the connection nodes of the respective inputs and the resistor 404 and the capacitor 405, the inputs of the comparator 406 are also swapped. Thereby, any offset in the comparator is taken care of simultaneously with any offset between the current sources 402, 403 without increasing complexity compared to the solution demonstrated with reference to FIG. 3.

(26) An optional filter capacitor 409 may, similarly to what has been demonstrated with reference to FIG. 2, be connected in parallel with the resistor 404.

(27) FIG. 5 illustrates a circuit 500 for calibration measurements according to an embodiment. The exemplary circuit 500 for Toggled Sample RC time constant Measurement comprises a current source arrangement 502 including 6 pFET transistors which form two current branches for measurement. A comparator 506 compares the differential inputs in nodes V1 and V2. Discharge switch 507 is a switch for discharging a sample capacitor 505, so after discharge, the capacitor 505 can be charged from zero voltage level. A sample resistor 504 has resistance Rn and the sample capacitor 505 has capacitance Cm, which will be referred to below, and the values Cm and Rn can be either fixed or programmable.

(28) The voltage on capacitor 505 charged by a current i(t) is

(29) $\mathrm{VCm}=\mathrm{VC}=\frac{1}{\mathrm{Cm}}\stackrel{t}{{}_0}i\left(t\right)\mathrm{dt}$

(30) When the charging current i(t) is a constant i, and the charging is from t=0,

(31) $\mathrm{VC}=\frac{i.Math.t}{\mathrm{Cm}}$

(32) While the voltage VR on the resistor 504 is iRn, when VR=VC, we have t=RnCm. This could be reached when the charging current i(t) is constant. In fact, as long as the current is constant, the RC measurement is independent of the current strength. However in practice of an implementation, like FIG. 5, i(t) is preferably properly chosen so that VR is a small portion of the supply voltage and the current of the current source 502 formed by the 6 transistors is operated in a voltage range that provides a current very close to a constant. The signal indicated Meas is a start signal for a measurement, and the signals indicated Stop1 and Stop2 are used to finish the measurement when V2 equals V1 for a two-period measurement. Normally a two-period measurement is accurate enough for most circuit design requirement with such arrangement, but M-period measurement can be also used for further improvement of accuracy, where M is an even number.

(33) FIG. 6 schematically illustrates a timing diagram and a block diagram for understanding the principle of calibration measurement. The block diagram shows a controller 600 providing control signals to a sample RC time constant measurement circuit 602, which may be according to any of the circuits 300, 400, 500 demonstrated above, and also for circuit 200 when considering particulars discussed below. The controller 600 also receives status signals from the sample RC time constant measurement circuit 602. A gate 604 receives a clock signal and a signal used for gating which opens the gate from start of charging the capacitor of the circuit 602 until the capacitor voltage has reached the resistor voltage of the circuit 602. A gated pulse signal, gp, is thus provided which represents the time it takes for the voltage across the capacitor to reach the voltage across the resistor, i.e. represents the RC time constant. The pulses of the gated pulse signal are counted by a counter 606 and the count is provided to a computing arrangement 608 for making a calibration of a circuit 610 comprising an RC circuit to be calibrated. The circuit 610 may be a filter, e.g. a variable bandwidth low-pass filter as indicated in FIG. 6, but may of course be any other filter, or circuit, comprising an RC circuit which needs to be calibrated to a desired time constant. The calibration may be made from a control word representing a control value for a desired setting, wherein the control word may be computed by the computing arrangement 608 from the measured time, i.e. the counts from the counter 606, and provided information about target time constants for respective settings. The computing arrangement can thus provide a vector or matrix of control words for the various settings.

(34) The timing diagram indicates the performing of two measurement periods where the gating signal is made high first for the first measurement and then made high for the second measurement. The principle of using only one measurement period, i.e. applicable for the circuit 200 demonstrated with reference to FIG. 2, can also be readily understood therefrom, wherein only the first part of the gating signal is utilised.

(35) To reach higher measurement accuracy, a filter capacitor C.sub.f may be used to reduce the thermal noise during comparison. The current in the branch may be weak and the resistance Rn may be large, which may result in large voltage noise. Besides the thermal noise, some comparators often have a kick-back effect when the comparator is toggling the output, which may increase measurement error too. With the aid of the filter capacitor, the thermal noise is low pass filtered and the kick-back effect introduced by the comparator is reduced, thus improving the measurement accuracy.

(36) The input of the comparator may have an offset caused by process mismatch. In addition, the current source branches may also have mismatch. To reach higher measurement accuracy, one way to alleviate this mismatch is to increase the device sizes in the comparator and current sources, but this may make the circuit slow and having large parasitics, which in turn will introduce measurement errors as well. While the solution mentioned above is the two-period measurement where a switching arrangement is used to flip connections between the nodes of connection of the comparator and the R and C branches, so that the input offset due to the comparator and current source mismatch is cancelled effectively. This solution is able to be combined with the use of the filter capacitor demonstrated above.

(37) FIG. 7 is a timing diagram schematically illustrating a measurement using two measurements as e.g. suggested with reference to FIGS. 4 and 5. The corresponding principle for a one-shot measurement as suggested with reference to FIG. 2 can readily be understood from the illustration of FIG. 6 and the corresponding disclosure as well. A Start signal may enable the calibration process which begins with discharge of the capacitor Cm, i.e. the control signal Disch is in a state engaging the discharge switch to short-circuit the capacitor, a polarity signal Polar is set to a first value setting one of the connections by the switching arrangement and a counter clearing signal Clr is set such that the counter is cleared. Once this is done, the discharge and clear signals are set back to respective other states, and the first measurement period is performed, starting with the first rising edge in pulse p2. The comparator will sense the difference between node voltages V1 and V2 and when V1=V2, it will flip its output and this will lead to reset of p2, toggle of polarity signal Polar, and discharge of the capacitor Cm for the second period measurement by setting the control signal Disch in discharge state again. Thereafter, the control signal Disch is set back to its other state and the procedure begins the second measurement period, and the comparator will sense the difference between its input node voltages V1 and V2 again. When V1=V2 it flips the output and this will lead to reset of p2 for the second time. The waveforms for V1/V2 are either a line with a charging slope, or the curve of a 1st order RC circuit having an exponential response. Note that any filter capacitor C.sub.f should be chosen so that it is charged much quicker than the capacitor charging branch when a filter capacitor is used. The counter will count the system clock as long as p2 is high, and when the two-period measurement is finished, it accumulates the total number of clock pulses in the gated pulse signal gp, i.e. the system clock gated by p2. That total number corresponds to two times the time constant of the sample RC components (2.Math.Nmn considering the notation of FIG. 6). As indicated above, a total number corresponding to the time constant can be achieved by just throw away the least significant bit (LSB) for the division of 2. The LSB can also be kept in the computation for further processing, and the division is performed after all control words are obtained, for better accuracy. The two-period measurement removes the mismatch impact on the result, also making the measurement less sensitive to temperature changes. A one-period measurement would correspond to the left half of the diagram, and the polarity signal Polar would not be present.

(38) After the two-period measurement, a set of clock pulses at signal CCK may be created by the controller, and the computing arrangement may use these pulses to compute required control words for a variable bandwidth low-pass filter VBWLPF if the computing arrangement is implemented in on-chip hardware.

(39) FIG. 8 is a block diagram schematically illustrating a computing arrangement 800 of a control word according to an embodiment. The control word, or vector or array of control words, can for example be used for a filter or circuit, similar as demonstrated with reference to FIG. 6.

(40) The resistors of the circuit to be calibrated may be tuned linearly in a range with a programmable control word, for instance, a resistor with a fixed part R.sub.o in series with a programmable part R.sub.p, where a unit resistance r.sub.o can be used for explaining a feasible approach. The fixed part may for example have a resistance R.sub.o which is r.sub.o.Math.a.sub.0, and the programmable part may have a resistance R.sub.p which is r.sub.o.Math.p, where a.sub.0 and p are integers. The aggregate resistance then becomes R.sub.a, i.e.
R.sub.a=R.sub.o+R.sub.p=r.sub.o.Math.a.sub.0+r.sub.o.Math.p=r.sub.o(a.sub.0+p)=r.sub.o.Math.a,

(41) where a is an integer, a.sub.maxaa.sub.0 with a.sub.max representing largest resistance value, and a=a.sub.0+p.

(42) Similarly, a capacitor built with programmable unit cells connected in parallel can be expressed as
C.sub.b=c.sub.0.Math.b

(43) where b.sub.maxbb.sub.0 and b is an integer too, and b.sub.max representing a largest capacitance value.

(44) The target time constant T.sub.t for the calibration can be expressed as
T.sub.tR.sub.a.Math.C.sub.b=r.sub.o.Math.c.sub.o.Math.a.Math.b=t.sub.o.Math.a.Math.b

(45) where t.sub.o is a unit cell time constant.

(46) The sample resistor and capacitor in the sample RC time constant measurement, SRCM, circuit are also designed in a similar way, so
R.sub.n=r.sub.o.Math.n,
and
C.sub.m=c.sub.o.Math.m

(47) where n and m are integers. The R.sub.n and C.sub.m may be programmable or may be built with a fixed number of series or parallel units, i.e., n and m, respectively. We can define the unit cell time constant t.sub.o for a RC unit cell as for the circuit to be calibrated, i.e. t.sub.or.sub.o.Math.c.sub.o. With this in mind, we can express the time constant for the sampling RC components as
T.sub.mnR.sub.n.Math.C.sub.m=t.sub.o.Math.m.Math.n

(48) In practice, the resistor and capacitor components normally may occupy a relative large area, such that the matching accuracy is sufficient. However, the unit cell time constant t.sub.o for the RC unit is process dependent which may lead to as large as +/25% error. The calibration work aims at finding a proper control number, e.g. represented with a control word in binary format, for a targeted time constant in e.g. an RC based low pass filter design, i.e, the values for a and b when both R and C can be programmable, or the number b when only C is programmable, or the number a when only R is programmable.

(49) To calibrate e.g. VBWLPF, the task is further to find multiple time constants T.sub.t1, T.sub.t2, . . . T.sub.tn accordingly. For the i:th targeted time constant T.sub.ti, we can have
T.sub.ti=t.sub.o.Math.a.sub.i.Math.b.sub.i=t.sub.o.Math.M.sub.i

(50) where M.sub.i is the product of the control numbers. As

(51) $t_o=\frac{T_{\mathrm{ti}}}{a_i.Math.b_i}=\frac{T_{\mathrm{mn}}}{m.Math.n}$

(52) we have

(53) $M_i=a_i.Math.b_i=\frac{T_{\mathrm{ti}}}{T_{\mathrm{mn}}}.Math.m.Math.n$

(54) If we use T.sub.mn as the counting time for a counter running at a system clock frequency f.sub.cks, the counted number in the end is N.sub.mn=T.sub.mn.Math.f.sub.cks and the targeted time constant can be converted also in a number counted in cycles of f.sub.cks, i.e. N.sub.ti=T.sub.ti.Math.f.sub.cks. So we can get the control number M.sub.i for i=1, 2, . . . , I.sub.n, assume that there are I.sub.n time constants in the VBWLPF:

(55) $M_i=a_i.Math.b_i=\frac{T_{\mathrm{ti}}.Math.f_{\mathrm{cks}}}{T_{\mathrm{mn}}.Math.f_{\mathrm{cks}}}.Math.m.Math.n=\frac{N_{\mathrm{ti}}.Math.m.Math.n}{N_{\mathrm{mn}}.Math.a_i}$

(56) To implement the time constants, one may prefer to first fix one of the parameter a.sub.i or b.sub.i. For instance, we fix a.sub.i, i.e, use a fixed resistor R.sub.ai=r.sub.o.Math.a.sub.i, then b.sub.i can be computed according to:

(57) $b_i=\frac{T_{\mathrm{ti}}.Math.f_{\mathrm{cks}}}{T_{\mathrm{mn}}.Math.f_{\mathrm{cks}}.Math.a_i}.Math.m.Math.n=\frac{N_{\mathrm{ti}}.Math.m.Math.n}{N_{\mathrm{mn}}.Math.a_i}$

(58) which can be translated into binary control words so that the filter is calibrated and the zeros and poles will be independent of process change, i.e, the change of the unit time constant t.sub.o.

(59) In general, due the circuit latency introduced by the comparator and control logic, the measured time constant for T.sub.mn may be a bit larger than the real one. As it is a constant positive error, a compensation can be added as

(60) $b_i=\frac{N_{\mathrm{ti}}.Math.m.Math.n}{\left(N_{\mathrm{mn}}-n_c\right).Math.a_i}$

(61) where n.sub.c is a compensation item which is usually very small, and b.sub.i is the control value represented by the control word.

(62) For the VBWLPF multiple RC component parameters calibration, the control word can be created either by a micro controller, an on chip parameter computing arrangement implemented in hardware or extracted from a predefined lookup table. A schematic of the an embodiment of the computing arrangement 800 implemented in application-specific hardware is shown in FIG. 8, where a digital divider 802, a first multiplier 804, a second multiplier 806, and an optional adder 808 are included, performing the mathematic computation of b.sub.i elucidated above as a control word CW.sub.i, which may be stored in a register array 810 for providing respective control word CtrlWord.sub.i to the RC circuit to be calibrated for a specific setting of N.sub.ti and a.sub.i. The analogous approach would apply for a specific setting of N.sub.ti and b.sub.i, or a specific setting of N.sub.ti and a.sub.i and b.sub.i, where a matrix of values are computed for each combination of a.sub.i and b.sub.i.

(63) FIG. 9 is a flow chart illustrating a method according to an embodiment. The method comprises controlling 900 the discharge switch to discharge the capacitor and clearing 902 a counter. The circuit is thus ready for commencing measurement, wherein a state of the switch is changed 904 to enable charging of the capacitor and clock signal pulses are counted 906 until the comparator provides 908 the signal when voltage across the capacitor reaches the voltage across the resistor. The parameter N.sub.mn as described above is thereby determined. A computation or lookup table check is then made to determine 910 a calibration measurement from the counted number of clock signal pulses.

(64) FIG. 10 is a flow chart illustrating a method according to an embodiment suitable for example for any of the circuits demonstrated with reference to FIG. 3, 4 or 5 above. In particular, the method is for calibration measurement of an RC circuit. A first connection alternative for the switching arrangement is set 1000, a counter is cleared 1002 and the capacitor is discharged 1004. The circuit is thus ready for commencing measurement, wherein a state of the switch is changed 1006 to enable charging of the capacitor and clock signal pulses are counted 1008 until the comparator provides 1010 the signal when voltage across the capacitor reaches the voltage across the resistor. It is checked 1012 whether both connection alternatives are performed, and since they are not in this example, the procedure continues with setting 1014 the second connection alternative by the switching arrangement, and the procedure repeats steps 1004 to 1012 for the second connection alternative. In the checking 1012 whether both connection alternatives are measured, the procedure continues with computation or lookup table check to determine 1016 a calibration measurement from the counted number of clock signal pulses. Optionally, the counter may be cleared between the two measurements, and thus stored before clearing, but since it is practical to aggregate the counts to achieve an average value, as demonstrated above, it is preferable that after setting 1014 to the second alternative connection, the procedure continues with step 1004.

(65) FIG. 11 is a block diagram schematically illustrating a communication device 1100 according to an embodiment. The communication device 1100 comprises a receiver, transmitter or transceiver arrangement 1102 which comprises one or more RC circuits 1110 as those demonstrated above, e.g. one or more filters. The one or more RC circuits 1110 also comprises the calibration measurement RC circuit as described with reference to any one of FIGS. 2 to 5 above. The receiver, transmitter or transceiver arrangement 1102 may be connected to an antenna 1104 through its antenna port. The communication device 1100 can also comprise other circuits 1106, such as interface towards a user and/or other circuitry or machines, memory, processor, etc. The communication device 1100 can be a smartphone or cellphone, a communication card or device in or for a computer, an embedded communication device in a machine, or the like. The communication device 1100 can be adapted for cellular communication, point-to-point communication, or for communication in a wireless or wired network.

(66) The antenna port described above need not necessarily by connected to an antenna, but can equally be connected to a wired line which conveys radio frequency signals. Thus, the communication device 1100 described with reference to FIG. 11 need not comprise the antenna 1104 wherein the communication device is instead connected to such a wired line conveying radio frequency signals.

(67) The receiver or transceiver arrangement 1102 can comprise a controller 1108 for controlling the operation of the receiver, transmitter or transceiver arrangement 1102. The controller 1108 can be arranged to perform the operations of the calibration measurements as demonstrated above, e.g. control, computation, lookup table access, etc. In particular, the calibration measurement is for calibration measurement of an RC circuit.

(68) The methods according to the present invention are suitable for implementation with aid of processing means, such as computers and/or processors, especially for the case where for example a baseband processor can be used for the control and computations or other controller used in connection with the circuits to be calibrated. Therefore, there is provided computer programs, comprising instructions arranged to cause the processing means, processor, or computer to perform the steps of any of the methods according to any of the embodiments described with reference to FIG. 9 or 10. The computer programs preferably comprises program code which is stored on a computer readable medium 1200, as illustrated in FIG. 12, which can be loaded and executed by a processing means, processor, or computer 1202 to cause it to perform the methods, respectively, according to embodiments of the present invention, preferably as any of the embodiments described with reference to FIG. 9 or 10. The computer 1202 and computer program product 1200 can be arranged to execute the program code sequentially where actions of the any of the methods are performed stepwise. The processing means, processor, or computer 1202 is preferably what normally is referred to as an embedded system. Thus, the depicted computer readable medium 1200 and computer 1202 in FIG. 12 should be construed to be for illustrative purposes only to provide understanding of the principle, and not to be construed as any direct illustration of the elements.

(69) The invention has mainly been described above with reference to a few embodiments. However, as is readily appreciated by a person skilled in the art, other embodiments than the ones disclosed above are equally possible within the scope of the invention, as defined by the appended patent claims.