Semiconductor material including different crystalline orientation zones and related production process

Abstract

The invention relates to a manufacturing process of semiconductor material of element III nitride from a starting substrate, the process comprising: the formation of an intermediate layer based on silicon on a starting substrate, said intermediate layer comprising at least two adjacent zones of different crystalline orientations, especially a monocrystalline zone and an amorphous or poly-crystalline zone, growth via epitaxy of a layer of element III nitride on said intermediate layer,
the intermediate layer being intended to be vaporised spontaneously during the step consisting of growing the layer of element III nitride via epitaxy.

Claims

1. A semiconductor substrate, comprising a material including a Group III element nitride, the material comprising: a plurality of regions of stress relaxation, and a monocrystalline region, extending in at least a portion of the substrate and including a plurality of interconnected bidimensional forms, wherein each bidimensional form has a Dmax/Drain ratio of a largest dimension (Dmax) to a smallest dimension (Dmin) of the bidimensional form between 5 and 20.

2. The substrate as claimed in claim 1, wherein the substrate comprises at least one of the following: a physical curvature defining a radius of curvature of at least around 5 m; a variation in offcut angle less than or equal to around 0.6 degrees between a bidimensional form in a central part of the substrate having an offcut angle and a bidimensional form in a peripheral part between the centre and a peripheral edge of the substrate having an offcut angle; and a relaxation ratio (Asr/Asc) less than or equal to around 30%, where Asc is an area of the plurality of interconnected bidimensional forms and Asr is an area of the plurality of regions of stress relaxation.

3. The substrate as claimed in claim 1, wherein a geometric variation between the plurality of bidimensional forms is less than or equal to 10% through the substrate, and wherein the geometric variation comprises at least one of the following: variation of a size of the plurality of bidimensional forms, variation of the position of the form on the substrate, variation of an orientation of the plurality of bidimensional forms on the substrate, variation of at least one dimension of the plurality of bidimensional forms, or variation in total pitch between the regions of stress relaxation defining the plurality of forms.

4. The substrate as claimed in claim 1, wherein each form of the plurality of bidimensional forms has a region having resistivity of around 1.0 ohm-cm or more on a surface of the substrate, and wherein each form of the plurality of bidimensional forms is configured to contain at least one device structure formed on the substrate, said device structure having a device centre spaced apart from the region of each form.

5. The substrate as claimed in claim 1, wherein the monocrystalline region forms a plurality of interconnected device regions having bidimensional forms, and wherein the substrate comprises a central zone located towards a centre of at least one device region and including a dopant.

6. The semiconductor substrate as claimed in claim 5, wherein the central zone has resistivity that is substantially identical to resistivity of a non-doped material towards the periphery of the region.

7. The semiconductor substrate as claimed in claim 5, wherein the dopant comprises germanium.

8. The semiconductor substrate as claimed in claim 5, wherein the resistivity of the central zone and resistivity of a material towards a periphery of the region are between around 0.01 ohm-cm and 1.0 ohm-cm.

9. The semiconductor substrate as claimed in claim 1, wherein directions defined by the largest dimensions of the bidimensional forms are distributed uniformly between two perpendicular orientations defined on a surface of the substrate.

10. The semiconductor substrate as claimed in claim 1, wherein directions defined by the largest dimensions of the bidimensional forms are distributed uniformly between three separate orientations of 120 defined on a surface of the substrate.

11. The semiconductor substrate as claimed in claim 1, wherein the directions defined by the largest dimensions of the bidimensional forms are distributed uniformly between orientations defined on a surface of the substrate by directions of the crystalline axes of a family of direction [10-10] or of a family of direction [11-20].

12. The semiconductor substrate as claimed in claim 1, wherein the regions of stress relaxation comprise at least one of a poly-crystalline material and amorphous material.

13. The semiconductor substrate as claimed in claim 1, wherein the plurality of interconnected bidimensional forms is defined by a repetitive pattern of isolated regions of stress relaxation.

14. The semiconductor substrate as claimed in claim 13, wherein each region of stress relaxation has a pattern including at least two connected lines extending in at least two non-parallel directions when viewed from a surface of the semiconductor substrate.

15. The semiconductor substrate as claimed in claim 13, wherein the repetitive pattern of the isolated regions of stress relaxation forms the plurality of interconnected forms having an area of at least 14 cm.sup.2.

16. The semiconductor substrate as claimed in claim 13, wherein the regions of stress relaxation have a width of at least 10 m.

17. The semiconductor substrate as claimed in claim 1, wherein the semiconductor substrate comprises gallium nitride.

18. The semiconductor substrate as claimed in claim 1, wherein the semiconductor substrate has a thickness greater than 1 m and at most 10 cm.

19. The semiconductor substrate as claimed in claim 3, wherein the plurality of interconnected bidimensional forms comprises a first form at a central region of the semiconductor substrate and a second form at a peripheral region of the semiconductor substrate, wherein the geometric variation between the first form and the second form is between 0.1% and 5%.

20. The semiconductor substrate as claimed in claim 1, wherein the plurality of interconnected bidimensional forms are connected by at least one zone of monocrystalline material having a width of at least 10 m.

21. The semiconductor substrate as claimed in claim 1, wherein the semiconductor substrate comprises a variation in offcut angle less than or equal to around 0.4 degree0.2 degrees between: a bidimensional form in a central part of the substrate having an offcut angle and a bidimensional form in a peripheral part of the substrate arranged between the centre part and a peripheral edge of the semiconductor substrate having an offcut angle.

22. The semiconductor substrate as claimed in claim 1, wherein the regions of stress relaxation extend vertically from an upper surface of the semiconductor substrate towards a lower surface of the semiconductor substrate.

23. The semiconductor substrate as claimed in claim 1, wherein the monocrystalline region comprises a density of dislocations less than or equal to around 110.sup.7 dislocations/cm.sup.2, and wherein the regions of stress relaxation comprise a density of dislocations greater than around 110.sup.8 dislocations/cm.sup.2 or 110.sup.9 dislocations/cm.sup.2.

24. The semiconductor substrate as claimed in claim 1, wherein the semiconductor substrate comprises a physical curvature with a relative distance from a median reference plane representing the surface plane of a semiconductor wafer without curvature, less than or equal to 50 m.

25. The semiconductor substrate as claimed in claim 1, wherein the semiconductor substrate comprises a semiconductor wafer having a diameter equal to around 10 centimetres, and wherein the semiconductor wafer comprises a crystalline curvature defining a radius of curvature of at least around 15 m.

26. The semiconductor substrate as claimed in claim 1, wherein the semiconductor substrate comprises a variation in pitch, between the regions of stress relaxation defining the plurality of forms, less than or equal to 45 m.

27. A method of manufacturing an optoelectronic component comprising: producing the optoelectronic component on the semiconductor substrate as claimed in claim 1.

Description

BRIEF DESCRIPTION OF THE FIGURES

(1) Other advantages and characteristics of the semiconductor material and its related manufacturing process will emerge from the following description of several variant embodiments, given by way of non-limiting examples from the attached diagrams, in which:

(2) FIGS. 1a, 1b, and 2 illustrate two variant embodiments of a manufacturing process of semiconductor material of element III nitride from a starting substrate,

(3) FIG. 3 illustrates in a plan view an example of a substrate of treated sapphire obtained by using a protective mask having a first pattern,

(4) FIG. 4 illustrates in a plan view an example of a layer of gallium nitride obtained by using a protective mask having a second pattern,

(5) FIGS. 5 and 6 illustrate deformations and variations of the orientation of the crystalline planes observed in substrates of GaN made according to the invention and flowing from implementing the invention; these substrates are characterised by discontinuity of the orientation of the crystalline planes systematically present in the passage of the amorphous or poly-crystalline zones.

(6) FIGS. 7 and 8 shows the orientation measurements of the crystalline planes in substrates according to the invention, taken by a standard X-ray diffraction method, which determine deformations and variations in orientation such as illustrated in FIGS. 5 and 6. FIGS. 7 and 8 further show concordance between the periodicity of the discontinuity of the orientation of the crystalline planes and the periodicity of the repetition of amorphous or polycrystalline zones in the intermediate layer based on silicon. The period is 10 mm for the substrate of element III nitride in FIG. 7, the period is 1.5 mm for that of FIG. 8. The geometry of the amorphous zones made in the intermediate layer based on silicon for making the measured substrates is illustrated in FIG. 9;

(7) FIGS. 10 to 13 illustrate examples of semiconductor substrates according to the invention.

DETAILED DESCRIPTION

(8) Different examples of manufacturing processes of semiconductor material, as well as products obtained in reference to the figures will now be described in more detail. In these different figures, equivalent elements bear the same reference numerals.

(9) In reference to FIG. 1, this illustrates an embodiment of a manufacturing process of semiconductor material of element III nitride, and more precisely gallium nitride GaN on a starting sapphire substrate type. This process overall comprises three phases: a first phase (steps 100 to 600) in which the starting substrate is treated to enable layer growth including adjacent zones of different crystallinity; a second phase (step 700) in which a layer of gallium nitride GaN is epitaxied, a third phase (step 800a or step 800b) in which the layer of epitaxied gallium nitride is cut through its thickness to obtain a wafer of gallium nitride which can: either be used for making semiconductor structures such as light-emitting diodes (LED), or as starting substrate for the growth of a new layer of element III nitride.

(10) The process comprises a first step 100 consisting of depositing a layer of photosensitive resin 20 on the growth face (so-called epitaxy-ready face or epi-ready according to English terminology) of the sapphire substrate 10. As a variant, the layer of photosensitive resin could be replaced by a layer of material dielectric.

(11) In another step 200 of the process, openings 21 are formed in the layer of photosensitive resin 20. The layer of photosensitive resin is illuminated by using a light emitting in the ultraviolet (UV) range. The layer of photosensitive resin 20 is exposed through an exposure mask (not shown) to light up only some regions of the photosensitive layer 20. Openings 21 form in the layer of photosensitive resin 20 at the level of the regions lit up by the UV light, such that some zones of the sapphire substrate 10 are no longer covered by the layer of photosensitive resin 20. This produces a protective mask comprising openings 21. Amorphous zones are then created in the sapphire substrate 10 at the level of the openings 21 of the protective mask.

(12) In another step 300 of the process, the substrate is exposed to oxygen plasma O.sub.2 or to argon plasma Ar. The sapphire substrate undergoes intense bombardment of ionised particles at the level of the openings 21 of the protective mask. This plasma bombardment destroys the crystalline character of the sapphire substrate 10 at the level of the zones of its growth face not covered by the protective mask. The crystalline zones of the substrate 10 located at the right of the openings 21 are converted into amorphous zones. The zones of the substrate covered by the protective mask are not damaged by the bombardment such that they retain their crystalline character. Exposure to plasma bombardment during a period of the order of 2 to 5 minutes is enough to destroy the crystalline character of the sapphire substrate 10 at its surface.

(13) When the plasma bombardment step is complete, the protective mask is removed (step 400) from the substrate. This results in a sapphire substrate comprising adjacent zones of different crystallinity at the level of its growth face. The different crystallinity zones are mixed at the surface of the sapphire substrate.

(14) In reference to FIG. 3, this illustrates in a plan view an example of a treated sapphire substrate conducting steps 100 to 400 described previously. This sapphire substrate 10 comprises a plurality of monocrystalline zones 12 and adjacent amorphous zones 11 in its growth plane.

(15) Of course, the forms of the monocrystalline zones and amorphous zones depend on the pattern of the protective mask. This pattern can have different shapes (pointed, square, triangular, strip, etc.) as a function of the specific application. In fact, a monocrystalline zone corresponds to a useful zone where the electronic component is or components are made. The surface of the crystalline zones 12 can be adjusted to that of a single electronic component or be larger to collect a multiplicity of these same components according to the application.

(16) In particular, the protective mask can be selected such that the dimensions of a monocrystalline zone satisfy the conditions on a Dmax/Dmin ratio in which: Dmax corresponds to the largest dimension of the monocrystalline zone in the growth plane, Dmax can be defined as being the length of the largest straight segment which is registered on the surface of the monocrystalline zone and whereof the ends are in contact with one (or more) amorphous or poly-crystalline zones adjacent to the relevant monocrystalline zone; this longest straight segment also defines a direction, without orientation constraint, which by definition will be the direction of the crystalline zone, and Dmin corresponds to the smallest dimension of the monocrystalline zone in the growth plane, Dmin can be defined as being the diameter of the largest circle totally registered in the monocrystalline zone, this circle being limited by contact with the adjacent amorphous or poly-crystalline zone or zones.

(17) In the event of ambiguity reference will be made to the patterns of the protective mask for evaluations of Dmax and Dmin.

(18) In particular, the geometric pattern of the protective mask can be selected such that this Dmax/Dmin ratio is: strictly over 5, and under or equal to 20.

(19) The fact that the Dmax/Dmin ratio is strictly over 5 produces a layer of element III nitride including monocrystalline zones whereof the dimensions satisfy the needs of many applications. The fact that the Dmax/Dmin ratio is less than or equal to 20 maintains the stresses above a cracking threshold in the crystalline zone.

(20) In fact, as explained previously, the amorphous or poly-crystalline zones are formed to limit the cracking phenomenon due to stresses in the layer of element III nitride.

(21) To limit this cracking phenomenon, it is therefore preferable to limit the largest dimension Dmax of each monocrystalline zone to a value under a critical dimension or distance DC which is a function of a specific cracking threshold of the element III nitride material. This threshold can be determined experimentally by progressively increasing the largest dimension of the monocrystalline zones. Stresses can cause deformation of the crystalline zone when the dimension of the monocrystalline zone is less than the critical dimension then the appearance of cracks in the layer of element III nitride beyond this critical distance.

(22) Preferably, the protective mask selected to form the monocrystalline zones and the amorphous or poly-crystalline zones has a single geometric pattern repeated many times on its surface. However, the mask can also comprise a single pattern intended to cover the entire surface of the substrate, such as for example a spiral pattern. Such a protective mask produces semiconductor material comprising two adjacent zones of different crystalline orientations, specifically: a single monocrystalline zone and a single poly-crystalline or amorphous zone.

(23) These two zones have spiral forms such that the crystalline orientation of the crystalline planes of the monocrystalline zone is discontinuous along the surface of the semiconductor material.

(24) A particular situation for stress is that where all the monocrystalline zones have a narrow elongated form, characterised by a large Dmax/Dmin ratio, however with Dmax<DC, and all have their largest dimension parallel to match the planned application, such as making components of laser or transistor type. Anisotropic deformation of the layer of element III nitride is noticed, and this is unfavourable for later transformation of the layer of element III into a substrate. Advantageously, orientation of the patterns can be varied on the surface of the protective mask. In particular, when the geometry of the pattern is elongated with a Dmax/Dmin ratio typically between 5 and 20, the protective mask can comprise a plurality of all the patterns, the orientation of the largest dimension varying (for example from 60 or 120) between two adjacent sets of patterns.

(25) This retains isotropy of deformation at the surface of the layer of element III nitride. More precisely, this prevents all stresses from propagating in a preferred direction, which would be the case if the patterns of elongated form were all aligned with the mask. So, isotropic distribution of the patterns on the mask retains deformation isotropy in the layer of element III nitride.

(26) Another solution for maintaining stress isotropy can comprise using a protective mask in which the geometry of each pattern is itself isotropic. This is for example the case of a protective mask having a pattern as a square, rhombus, circle, or any pattern defining in the crystalline zone a larger Dmax dimension near the smaller dimension Dmin, typically Dmax/Dmin<3. More advantageously still, an isotropic pattern such as an equilateral triangle, a rhombus at 60/120 or a hexagon will also have elements of crystalline symmetry of the element III nitride.

(27) In reference again to FIG. 1, the process comprises a step 500 consisting of depositing a layer of silicon 30 onto the substrate 10.

(28) The layer of silicon 30 acts intermediate layer intended to be vaporised spontaneously during the later step of growth via epitaxy of the layer of gallium nitride GaN.

(29) Growth of the layer of silicon 30 on the substrate 10 including adjacent amorphous 11 and monocrystalline zones 12 causes formation of a layer of silicon 30 including adjacent amorphous zones 31 and crystalline zones 32.

(30) In fact, the inventors have discovered that the crystallinity or the absence of crystallinity of the substrate propagates in the layer of silicon 30 deposited on the latter.

(31) In this way, zones of amorphous silicon 31 or close to the amorphous state (i.e. poly-crystalline) form vertically to the amorphous zones 11 of the substrate 10, and the monocrystalline silicon zones 32 form vertically to the monocrystalline zones 12 of the substrate 10.

(32) This results in a layer of silicon 30 including amorphous or poly-crystalline zones 31 and adjacent monocrystalline zones 32.

(33) In another step 600 of the process, a layer of aluminium nitride AlN is deposited onto the layer of silicon 30. The layer of aluminium nitride AlN acts as buffer layer to improve the quality and crystalline morphology of the layer of gallium nitride GaN epitaxied later.

(34) The epitaxy of the layer of aluminium nitride 40 on the layer of silicon 30 including adjacent amorphous zones 31 and monocrystalline zones 32 causes formation of a layer of aluminium nitride 40 including adjacent amorphous or poly-crystalline zones 41 and monocrystalline zones 42.

(35) In fact, the inventors have discovered that the crystallinity or absence of crystallinity propagates in the layer of aluminium nitride 40.

(36) Zones of amorphous aluminium nitride 41or close to the amorphous state (i.e. poly-crystalline)form above of the amorphous zones 31 of silicon, and the zones of monocrystalline aluminium nitride 42 form above of the monocrystalline zones 32 of silicon.

(37) On completion of the deposit step of the layer of aluminium nitride, a stack is obtained comprising: a sapphire substrate 10 including amorphous zones 11 and monocrystalline zones 12 at the level of its growth face, a layer of silicon 30 on the substrate sapphire 10, the layer of silicon 30 including amorphous zones (or poly-crystalline) 31 and monocrystalline zones 32, a layer of aluminium nitride 40 on the layer of silicon 30, the layer of aluminium nitride 40 including amorphous zones (or poly-crystalline) 41 and monocrystalline zones 42.

(38) The second phase of the process is then executed.

(39) In a step 700 of the process, a layer of gallium nitride 50 is deposited onto the layer of aluminium nitride 40.

(40) The layer of gallium nitride is deposited via epitaxy in vapour phase from chlorides and hydrides (or HVPE, acronym of the English expression Hydride Vapour Phase Epitaxy). However, the expert will appreciate that depositing of the layer of gallium nitride can also be done via epitaxy in vapour phase with metal organics (or MOVPE, acronym of the English expression Metal Organic Vapour Phase Epitaxy).

(41) During growth of the layer of gallium nitride, the layer of silicon vaporises spontaneously such that the AlN/GaN stack comprising the layer of aluminium nitride AlN and the layer of gallium nitride GaN dissociates from the sapphire substrate.

(42) This decoupling between the sapphire substrate and the AlN/GaN stack favourably limits the cracking phenomenon in the layer of gallium nitride by eliminating stresses tied to the differences in thermal coefficients between sapphire and gallium nitride during cooling subsequent to the deposit of the layer of gallium nitride 50. In the absence of amorphous or poly-crystalline zones 51, this decoupling unfavourably allows stresses, which continue growing with improvement in the crystalline quality of GaN, to be released by generating cracks during growth. The introduction of amorphous or poly-crystalline zones 51 provides places where stress can favourably relax without creating cracks. The introduction of zones 51 enables the manufacture of a layer of gallium nitride 50 without cracks comprising zones 52 of very high quality.

(43) The growth of the layer of gallium nitride 50 on the layer of aluminium nitride 40 including mixed amorphous 41 and monocrystalline zones 42 causes formation of a layer of gallium nitride 50 including adjacent amorphous or poly-crystalline zones 51 and monocrystalline zones 52: amorphous or poly-crystalline zones of gallium nitride 51 form above of the amorphous zones 41 of aluminium nitride, and monocrystalline zones of gallium nitride 52 form above of the monocrystalline zones 42 of aluminium nitride.

(44) The layer of gallium nitride 50 does not grow equally to the surface of the layer of aluminium nitride because of the presence of amorphous or poly-crystalline zones 41 of aluminium nitride.

(45) In fact, the growth rate of gallium nitride on a monocrystalline zone is greater by up to twice the growth rate of gallium nitride on an amorphous or poly-crystalline zone.

(46) During growth of the layer of gallium nitride, this natural phenomenon causes formation of facets 55 which ensure continuity of the surface of the layer 50 between: the amorphous or poly-crystalline zones 51 of gallium nitride above the zones 41 of aluminium nitride, and the upper growth region 53 above the monocrystalline zones of aluminium nitride 42.

(47) Preferably, the growth temperature of the layer of gallium nitride is selected relatively low to induce a three-dimensional (3D) growth mode of the layer of gallium nitride 50. For example, the growth temperature of the layer of gallium nitride is kept substantially equal to 980 C.

(48) This mode of 3D growth causes formation of islets and of facetted holes 54 at the level of the upper growth region 53. This allows strong doping in oxygen of gallium nitride because of the presence of facets, facets of islets and holes 54 and facets 55, over its entire growth surface. This strong doping in oxygen has the advantage of diminishing the resistivity of the layer of gallium nitride over its entire surface, which enables the manufacture of semiconductor structures over a larger surface of the layer of gallium nitride.

(49) The growth of the layer of gallium nitride can be maintained until the upper region of growth 53 has completely disappeared. For example, the growth of the layer of gallium nitride can be maintained until a layer of gallium nitride of thickness greater than twice the width of a monocrystalline zone is obtained.

(50) Of course, the growth of the layer of gallium nitride can also be interrupted before the upper region of growth 53 disappears completely.

(51) On completion of the growth step of the layer of gallium nitride, the result is a stack comprising a layer of aluminium nitride and a layer of gallium nitride, the thickness of the layer of gallium nitride able to vary between 1 m and 10 mm as a function of the specified application, the stack being autosupported and released from the starting substrate 10.

(52) Another step 800a, 800b of the process consists of cutting the layer of gallium nitride through its thickness to obtain a wafer of gallium nitride. The wafer of gallium nitride can be cut in a region of the layer of gallium nitride where the upper growth region 53 has disappeared (step 800a), or in a region of the layer of gallium nitride where the upper growth region 53 is still present (step 800b). Steps 800a and 800b make, by polishing, substrates of plane GaN whereof the roughness Ra is of the order of an angstrom, without cracks with crystalline zones 52 of excellent quality specific to the growth of devices such as very high-power light-emitting diodes for lighting.

(53) The resulting wafer of gallium nitride can be used to make optoelectronic components. In this case, the optoelectronic components are made on the monocrystalline zones of the wafer of gallium nitride.

(54) As a variant, the wafer of gallium nitride can be used as a substrate for growing a new layer of element III nitride, especially gallium nitride.

(55) Different growth techniques of the new layer of gallium nitride can be used, such as an epitaxial overgrowth technique (or ELO, acronym of the English expression Epitaxial Lateral Overgrowth).

(56) In the case of epitaxial lateral overgrowth, a growth mask is for example arranged on the wafer of gallium nitride and whereof the openings extend above the monocrystalline zones 52 of the wafer of gallium nitride, the mask covering the amorphous or poly-crystalline zones 51 of the wafer of gallium nitride.

(57) Advantageously, the pattern of the mask can be provided to partially cover the monocrystalline zones of the wafer of gallium nitride. This limits the thickness of growth necessary to obtain a flat new layer of gallium nitride.

(58) In reference to FIG. 2, this illustrates another embodiment of the manufacturing process of a layer of gallium nitride. This second embodiment differs from the process illustrated in FIG. 1 in that the crystalline quality of the sapphire substrate is not degraded to obtain amorphous zones.

(59) A step 110 of this process comprises depositing a layer of amorphous gallium nitride 60 over the entire surface of the sapphire substrate 10. The layer of gallium nitride amorphous can be deposited by MOVPE at a very low temperature, typically less than or equal to 600 C. so as to favour amorphous growth of the gallium nitride.

(60) As a variant, the deposit step of the layer of amorphous gallium nitride 60 can be replaced by a deposit step of a layer of amorphous aluminium nitride. The inventors have in fact noted that amorphous aluminium nitride, also obtained by deposit at very low temperature, can play the same role as the amorphous GaN in this embodiment.

(61) In another step 210 of the process, a protective mask 20 including openings 21 is deposited on the layer of amorphous gallium nitride 60.

(62) The layer of amorphous gallium nitride is then etched (step 310) through the openings 21 of the protective mask 20 until the sapphire substrate becomes visible.

(63) In another step 410 of the process, the protective mask is removed, resulting in a sapphire substrate including zones of amorphous gallium nitride on its overgrowth face.

(64) The growth of the layer based on silicon then occurs, as does the growth of the layer of aluminium nitride and the growth of the layer of gallium nitride (step 510), as described previously in reference to FIG. 1.

(65) The crystalline orientation or the absence of crystalline orientation propagates through these different layers, resulting (prior to vaporisation of the layer based on silicon) in a stack comprising: a sapphire substrate 10, amorphous zones of gallium nitride 60 on the sapphire substrate 10, a layer based on silicon 30 on the sapphire substrate 10, said layer based on silicon 30 including: amorphous or poly-crystalline zones 31 above amorphous zones of gallium nitride 60, monocrystalline zones 32 above zones of the substrate not covered by the layer of amorphous gallium nitride 60, a layer of aluminium nitride 40 on the layer based on silicon 30, said layer of aluminium nitride 40 including: amorphous or poly-crystalline zones 41 above amorphous or poly-crystalline zones based on silicon 31, monocrystalline zones 42 above monocrystalline zones based on silicon 32, a layer of gallium nitride 50 on the layer of aluminium nitride 40, said layer of gallium nitride 50 including: amorphous or poly-crystalline zones 51 above amorphous or poly-crystalline zones of aluminium nitride 41, monocrystalline zones 52 above monocrystalline zones of aluminium nitride 42.

(66) On completion of the growth step of the layer of gallium nitride including adjacent zones of different crystalline orientations, the steps of the second and third phases described in reference to FIG. 1 are conducted.

(67) As described previously, different arrangements of the monocrystalline and amorphous (or poly-crystalline) zones can be obtained as a function of the protective mask selected.

(68) In reference to FIG. 4, this illustrates an example of arrangements for monocrystalline and amorphous (or poly-crystalline) zones of a layer of gallium nitride 50 for a type of protective mask.

(69) The monocrystalline zones 52 have an overall triangular form, and are enclosed by overall rectilinear amorphous or poly-crystalline zones 51 having different orientations.

(70) In reference to FIGS. 5 and 6, these schematically illustrate the radii of curvature of two layers of gallium nitride 50 including alternating rectilinear monocrystalline zones and rectilinear amorphous (or poly-crystalline) zones. These two layers of gallium nitrides 50 were obtained by using the manufacturing process illustrated in FIG. 1.

(71) These two layers of gallium nitride 50 differ in that the protective masks used in the manufacturing process have different pitches.

(72) In the case of the layer of gallium nitride whereof the radius of curvature is illustrated in FIG. 5, the pitch of the protective mask used is 10 millimetres.

(73) In the case of the layer of gallium nitride whereof the radius of curvature is illustrated in FIG. 6, the pitch of the protective mask used is 5 millimetres.

(74) As is evident from these figures, the combination: of the formation of amorphous or poly-crystalline zones adjacent to monocrystalline zones, with use of a sacrificial layer based on silicon vaporising spontaneously during growth of the layer of gallium 50,
produces discontinuity of the orientation of the crystalline planes in the layer of gallium nitride 50. This locally decreases stresses in the layer of gallium nitride 50 to below a critical threshold causing cracking of the latter.

(75) In this way, the substrates of gallium nitride obtained by executing the process described hereinabove are characterised by discontinuity of the orientation of the crystalline planes systematically present for passage of amorphous or poly-crystalline zones, as shown in FIGS. 5 and 6.

(76) It is evident in fact in FIGS. 5 and 6 that the substrates exhibit discontinuity of the orientation of the crystalline planes in the crystallised zones for passage of amorphous zones. This discontinuity is associated with the amorphous zones since it presents periodicity of said zones.

(77) In reference to FIGS. 7 and 8, the orientation of the crystalline planes as a function of positions on the substrate along a measuring line 56 is illustrated. These crystalline orientation planes in substrates according to the invention, created by a standard X-ray diffraction method, determine the orientation deformations and variations such as illustrated in FIGS. 5 and 6.

(78) FIGS. 7 and 8 further reveal the concordance between the periodicity of the discontinuity of the orientation of the crystalline planes and the periodicity of the repetition of the amorphous or poly-crystalline zones in the intermediate layer based on silicon. The period is 10 mm for the substrate of element III nitride of FIG. 7, and the period is 1.5 mm for that of FIG. 8.

(79) The geometry of the amorphous zones formed in the intermediate layer based on silicon for manufacturing the measured substrates is illustrated in FIG. 9.

(80) FIG. 10 illustrates a semiconductor substrate formed by using the process according to the invention described here. The semiconductor substrate 100 comprises a semiconductor wafer made of gallium nitride whereof an arrangement of the regions of stress relaxation 151 divides the monocrystalline region 152 into an interconnected plurality of triangular forms by using the pattern illustrated in FIG. 4. As described previously, different arrangements of the amorphous and/or poly-crystalline regions, which result in the monocrystalline region being divided into different interconnected formed regions, can be obtained as a function of the selected protective mask.

(81) Generally, the semiconductor substrate 100 can be in the form of a semiconductor wafer having a form similar to a disc defining a particular diameter. For example, the diameter of the semiconductor wafer can be at least around 5.1 cm (around 2 inches), at least around 7.6 cm (around 3 inches), at least around 10 cm (around 4 inches), at least around 15 cm (around 6 inches), at least around 20 cm (around 8 inches) or even at least around 30 cm (around 12 inches).

(82) In the embodiment of FIG. 10, a semiconductor substrate formed from a material based on nitride of group III comprises a region of monocrystal 152 (in other words, a monocrystalline region) and a plurality of regions of stress relaxation 151 extending in at least one part of the substrate and defining a plurality of interconnected bidimensional forms in the region of monocrystal. Preferably, the region of monocrystal is a continuous monocrystalline region divided into a plurality of interconnected regions. These interconnected regions are preferably identical as to size and form, but in practice there will be some inevitable degree of variation. As described in greater detail hereinbelow, the preferred embodiments reduce to a minimum any geometric variation through the substrate, improving predictability and productivity for devices formed on the substrate.

(83) The regions of stress relaxation comprise amorphous and/or poly-crystalline regions as described hereinabove, which act to absorb stress/deformation of tension in the substrate. As illustrated in FIG. 11, the autosupported substrates or the semiconductor wafers 100 formed from material based on nitride of group III, such as GaN, generally have a curved concave form due to stress which appears during crystalline development. In FIG. 11, arrow 122 represents the quantity of physical curvature present relative to a median reference plane 120 (which would represent the surface plane of a semiconductor wafer without curvature). Also, the substrate can have a physical curvature such as illustrated, as well as a curvature of the internal crystalline structure.

(84) As illustrated in FIG. 12, however, in the embodiments of the present invention, the amorphous or poly-crystalline regions of stress relaxation 151 act to dissipate some of the stresses in the substrate 102. In fact, the presence of these regions enables division of the monocrystal substrate into zones 152 which behave like smaller independent crystals. The curvatures both physical and crystalline are accordingly considerably reduced.

(85) In some embodiments, the stress in the substrate is reduced to the point where no cracking occurs, or only very minimal cracking in the substrate. Preferably, substantially all resulting cracking occurs in the regions of stress relaxation such that the region of monocrystal is substantially devoid of cracks. As described hereinabove, the prior art shows the use of amorphous or poly-crystalline zones in a layer of nitride of an element of group III to decrease the number of crystalline defects in the regions of monocrystal by trapping the dislocations in the amorphous or poly-crystalline zones of the layer of nitride of an element of group III. By contrast, the embodiments of the present invention utilise amorphous or poly-crystalline zones as regions of stress relaxation to reduce the physical and crystalline curvatures of the substrate or of the semiconductor wafer.

(86) The expression bidimensional forms is used here to make reference to the forms on the surface of the substrate formed by the regions of stress relaxation. It must be understood that these bidimensional forms are simply the forms of the surface of a region of monocrystal which extends downwards through the substrate. Similarly, the regions of stress relaxation form forms or lines on the surface of the substrate as described here, but these regions extend also downwards through the substrate, extending preferably vertically from the upper surface of the substrate towards the lower surface of the substrate. FIG. 13 illustrates a pattern of regions of stress relaxation forming a plurality of interconnected bidimensional triangular forms on the surface of the substrate. As illustrated in FIG. 13, each of these regions or forms extends downwards through the substrate.

(87) The semiconductor substrate comprises also at least one of the following: a physical curvature defining a radius of curvature of at least around 5 m; a variation in offcut angle (2) less than or equal to around 0.6 degree between a bidimensional form in a central part of the substrate having an offcut angle (c) and a bidimensional form in a peripheral part of the substrate arranged between the centre and a peripheral edge of the substrate having an offcut angle (p); and a relaxation ratio (Asr/Asc) less than or equal to around 30%, where Asc is the area of the plurality of interconnected bidimensional forms and Asr is the area of the plurality of regions of stress relaxation.

(88) In an embodiment, the substrate comprises a semiconductor wafer having a diameter of at least around 10 cm (around 4 inches) having a physical curvature defining a radius of curvature of at least around 12 m. Preferably, the embodiments of the present invention will have a physical curvature with a relative distance from a median reference plane less than or equal to 50 less than or equal to 40 m, or less than or equal to 25 m, as illustrated in FIG. 12.

(89) In some embodiments, the variation in offcut angle through the semiconductor wafer is controlled to be less than 0.2 degree (0.1 degree) through the substrate independently of the size of the free-standing substrate. In some embodiments, the substrate comprises a semiconductor wafer having a diameter of around 5.1 cm (around 2 inches) and the semiconductor wafer comprises a crystalline curvature defining a radius of curvature of at least around 7 m. In some embodiments, the substrate comprises a semiconductor wafer having a diameter of around 10 cm (around 4 inches) and the semiconductor wafer comprises a crystalline curvature defining a radius of curvature of at least around 15 m.

(90) In some embodiments, the substrate comprises a relaxation ratio (Asr/Asc) less than or equal to around 20%, 15%, 12%, or 10%, 5%, or 1%, where Asc is the area of the plurality of interconnected bidimensional forms and Asr is the area of the plurality of regions of stress relaxation.

(91) According to one aspect, the geometric variation between the plurality of interconnected bidimensional forms is less than or equal to 20%, 15%, 10%, 9%, 8%, 7%, 6%, 5%, 4%, 3%, 2%, 1%, 0.75%, 0.5%, 0.25%, or 0.1% through the substrate. As used here, the expression geometric variation makes reference to any variation in the geometry of two of the bidimensional forms, including the size of the forms, the position of the forms on the substrate, the orientation of the forms on the substrate, at least one dimension of the forms, or a variation in total pitch between the regions of stress relaxation defining the plurality of forms. In some embodiments, the substrate comprises a variation in total pitch between the plurality of interconnected bidimensional forms through the substrate less than or equal to 20%, 15%, 10%, 9%, 8%, 7%, 6%, 5%, 4%, 3%, 2%, 1%, 0.75%, 0.5%, 0.25%, or 0.1% through the substrate. Preferably, the substrate comprises a variation in pitch less than or equal to 45 m.

(92) In some embodiments, a semiconductor substrate formed from material based on nitride of group III comprises a plurality of regions of stress relaxation; a region of monocrystal extending between the plurality of regions of stress relaxation, the region of monocrystal forming a plurality of interconnected bidimensional forms; where the geometric variation between the plurality of bidimensional forms is less than or equal to 10%, 9%, 8%, 7%, 6%, 5%, 4%, 3%, 2%, 1%, 0.75%, 0.5%, 0.25%, or 0.1% through the substrate.

(93) According to another embodiment, a production batch of autosupported substrates can be formed by using the processes described here. In particular, a production batch can comprise at least 20 substrates formed consecutively relative to each other, which are not necessarily selected randomly in a larger reserve of substrates, which have been formed by using the same process and intended to have the same geometric and crystalline characteristics. For particular embodiments, a production batch of at least 20 substrates can be formed, in which each of the substrates has the characteristics described here.

(94) Also, the production batch in its entirety can have particular characteristics. In some embodiments, a production batch of substrates comprises at least 20 substrates, each of the substrates in the batch comprising a semiconductor substrate formed from a material based on nitride of group III, the substrate comprising: a region of monocrystal; a plurality of regions of stress relaxation extending in at least one part of the substrate and defining a plurality of interconnected bidimensional forms in the region of monocrystal; and where the substrate comprises at least one of the following: a physical curvature defining a radius of curvature of at least around 5 m; a variation in offcut angle (2) less than or equal to around 0.6 degree between a bidimensional form in a central part of the substrate having an offcut angle (c) and a bidimensional form in a peripheral part of the substrate arranged between the centre and a peripheral edge of the substrate having an offcut angle (p); and a relaxation ratio (Asr/Asc) less than or equal to around 30%, where Asc is the area of the plurality of interconnected bidimensional forms and Asr is the area of the plurality of regions of stress relaxation.

(95) In such a production batch of substrates each of the substrates in the batch can also comprise a plurality of regions of stress relaxation; and a region of monocrystal extending between the plurality of regions of stress relaxation, the region of monocrystal forming a plurality of interconnected bidimensional forms, where the geometric variation between the plurality of bidimensional forms is less than or equal to 10%, 9%, 8%, 7%, 6%, 5%, 4%, 3%, 2%, 1%, 0.75%, 0.5%, 0.25%, or 0.1% through the substrate.

(96) In some embodiments, a semiconductor substrate formed from a material based on nitride of group III comprises a region of monocrystal extending between a plurality of regions of stress relaxation, the region of monocrystal forming a plurality of interconnected bidimensional forms, where each form of the plurality has a region of high resistivity having resistivity of around 1.0 ohm-cm or more on the substrate surface in the form, and where each form of the plurality of forms is configured to contain at least one device structure formed on the substrate, said device structure having a device centre spaced apart from the region of high resistivity.

(97) In some embodiments, a semiconductor substrate formed from a material based on nitride of group III comprises a region of monocrystal extending between a plurality of regions of stress relaxation, the region of monocrystal forming a plurality of interconnected bidimensional forms, where each form of the plurality of forms is configured to contain at least one device structure having a complementary form. A complementary form will be that in which the device structure is adjusted in the form of monocrystalline zone defined by the bidimensional form.

(98) In some embodiments, a semiconductor substrate formed from a material based on nitride of group III comprises a plurality of regions of stress relaxation; a region of monocrystal extending between the plurality of regions of stress relaxation, the region of monocrystal forming a plurality of interconnected device regions having bidimensional forms; and a zone located towards the centre of at least one device region in which a dopant has been added to lower the resistivity of the monocrystalline material in the zone.

(99) Preferably, the doped central zone has resistivity which is substantially identical to the resistivity of the non-doped material towards the periphery of each zone. The dopant can comprise germanium, for example. The resistivity of the doped central zone and the resistivity of the non-doped material towards the periphery of each zone are between around 0.01 ohm-cm and 1.0 ohm-cm, and preferably less than or equal to around 0.1 ohm-cm.

(100) According to an aspect, the interconnected bidimensional forms are formed by a repetitive pattern of isolated regions of stress relaxation. The regions of stress relaxation are each preferably in the form of at least two connected lines extending in at least two non-parallel directions. The term lines makes reference to the bidimensional form of surface of the regions of stress relaxation, even though the regions extend through the substrate. In reference to FIG. 4, for example, the bidimensional form of surface of the regions of stress relaxation (amorphous or poly-crystalline zones 51) is generally in the form of two lines crossing each other (not parallel). In an embodiment, one of the lines could have for example a width of around 10 m and a length of 400 m, whereas the second line, which crosses the central part of the first line according to an angle, could have for example a width of around 10 m and a length of around 200 m.

(101) The pattern of the regions of stress relaxation can form a plurality of interconnected polygonal, circular, ellipsoidal, irregular, hexagonal, equilaterally triangular or triangular forms. In an embodiment, the pattern of the regions of stress relaxation forms a plurality of interconnected forms in which the largest dimension of the bidimensional form is at least 100 m, at least 200 m, or at least 300 m. In another embodiment, the pattern of the regions of stress relaxation forms a plurality of interconnected forms in which the smallest dimension of the bidimensional form is at least 200 m or more. In some embodiments, the pattern of the regions of stress relaxation forms a plurality of interconnected forms in which the dimension of the bidimensional form in a first direction is greater than the dimension of the bidimensional form in a second direction.

(102) Any one of the preceding claims, in which the pattern of the regions of stress relaxation forms a plurality of interconnected forms having an area of at least 14 cm.sup.2.

(103) The regions of stress relaxation forming the repetitive pattern can have a width of at least 10 m, for example a width of around 10 m to 100 m. The regions of stress relaxation can each be for example in the form of at least two connected lines extending in at least two non-parallel directions. The regions of stress relaxation can be each in the form of at least two connected lines, one of the lines forming an angle with the other line. The regions of stress relaxation can each be in a form in which a part of the form extends in a direction on the substrate surface, whereas another part of the form extends in a different direction on the substrate surface.

(104) As described hereinabove, the plurality of regions of stress relaxation acts to dissipate stress through the substrate. In some embodiments, the semiconductor substrate comprises gallium nitride. In some embodiments, the semiconductor substrate has a thickness greater than 1 m, preferably from 100 m to 10 cm, more preferably from 500 m to 3 mm.

(105) In some embodiments, the plurality of interconnected bidimensional forms comprises at least one first form at a central region of the substrate and a second form at a peripheral region of the substrate, and the geometric variation between the first form and the second form is less than or equal to 10%, 9%, 8%, 7%, 6%, 5%, 4%, 3%, 2%, 1%, 0.5%, 0.25%, or 0.1%. The plurality of interconnected bidimensional forms comprises at least one first form at a central region of the substrate and a second form at a peripheral region of the substrate, and the geometric variation between the first form and the second form is between 0.1% and 5%, or between 0.01% and 10%. The geometric variation can comprise at least one of the following: the size of the form, the position of the form on the substrate, the orientation of the form on the substrate, at least one dimension of the form, or a variation in total pitch between the regions of stress relaxation defining the plurality of forms.

(106) In some embodiments, the interconnected bidimensional forms are connected by at least one zone of monocrystalline material having a width of at least 10 m, for example a width of around 10 m to 100 m.

(107) In some embodiments, the semiconductor substrate comprises a variation in offcut angle (2) less than or equal to around 0.4 degree (+0.2 degree), 0.38 degree, 0.36 degree, 0.34 degree, 0.32 degree, 0.3 degree, 0.28 degree, 0.26 degree, 0.24 degree, 0.22 degree, or 0.20 degree between a bidimensional form in a central part of the substrate having an offcut angle (c) and a bidimensional form in a peripheral part of the substrate arranged between the centre and a peripheral edge of the substrate having an offcut angle (p).

(108) In some embodiments, the region of monocrystal comprises a density of dislocations less than or equal to around 1107 dislocations/cm2, 9106 dislocations/cm2, 8106 dislocations/cm2, 7106 dislocations/cm2, 6106 dislocations/cm2, 5106 dislocations/cm2, 4106 dislocations/cm2, 3106 dislocations/cm2, 2106 dislocations/cm2, 1106 dislocations/cm2, 1105 dislocations/cm2, or 1104 dislocations/cm2.

(109) The embodiments here represent an innovation relative to the prior art. The present application presents a particular process for forming semiconductor substrates using a particular combination of characteristics, comprising the processes described hereinabove which form amorphous and/or poly-crystalline zones or regions in a layer of nitride of element of group III. As described hereinabove, the prior art shows the use of these amorphous or poly-crystalline zones in a layer of nitride of an element of group III to lower the number of crystalline defects in regions of monocrystal by trapping the dislocations in the amorphous or poly-crystalline zones of the layer of nitride of an element of group III. But in these documents, it is neither described nor suggested that the presence of amorphous or poly-crystalline zones in a layer of nitride of an element of group III absorbs the stresses of the layer of nitride of an element of group III.

(110) On the contrary, the embodiments of the present invention use amorphous or poly-crystalline zones as regions of stress relaxation to reduce the physical and crystalline curvatures of the substrate or the semiconductor wafer. Introducing amorphous and/or poly-crystalline regions provides zones in which stress can be relaxed without creating cracks. This enables manufacture of a layer of very high quality of monocrystalline gallium nitride without cracks in the substrate.

(111) The expert will have understood that numerous modifications can be made to the processes and materials described hereinabove without departing materially from the new ideas presented here.

(112) It is therefore evident that the examples which have just been given are only particular non-limiting illustrations.