Optical receivers with dc cancellation bias circuit and embedded offset cancellation

Abstract

In optical receivers, cancelling the DC component of the incoming current is a key to increasing the receiver's effectiveness, and therefore increase the channel capacity. Ideally, the receiver includes a DC cancellation circuit for removing the DC component; however, in differential receivers an offset may be created between the output voltage components caused by the various amplifiers. Accordingly, an offset cancellation circuit is required to determine the offset and to modify the DC cancellation circuit accordingly.

Claims

1. An optical receiver comprising: at least one photodetector capable of generating a differential input current including first and second input current components in response to an optical signal; a trans-impedance amplifier (TIA) capable of converting the first and second input current components into first and second input voltage components; a DC cancellation circuit (DCCC) for cancelling a DC portion of the first and second input current components or the first and second input voltage components by comparing the first and second input current components or the first and second input voltage components to respective first and second reference voltages or currents, and sinking the DC portion of the first and second input current components based on the comparisons; and an offset cancellation circuit (OCC) capable of obtaining first and second voltage samples after the TIA and of cancelling offset between the first and second input voltage components by modifying at least one of the first or second reference voltages.

2. The optical receiver according to claim 1, wherein the offset cancellation circuit comprises: a voltage comparator for determining the offset by comparing the first and second voltage samples; and a voltage summer for adding or subtracting the offset to or from one of the first or second reference voltages.

3. The optical receiver according to claim 1, wherein the offset cancellation circuit comprises: a voltage comparator for determining the offset by comparing the first and second voltage samples; and a voltage summer for adding a portion of the offset to one of the first or second reference voltages and subtracting another portion of the offset from the other of the first or second reference voltages.

4. The optical receiver according to claim 1, further comprising a variable gain amplifier (VGA) capable of amplifying the first and second input voltage components to a desired output voltage forming first and second output voltage components.

5. The optical receiver according to claim 4, further comprising first and second OCC sensing points positioned between the TIA and VGA enabling the offset cancellation circuit to sample the first and second input voltage components, respectively, for the first and second sample voltages.

6. The optical receiver according to claim 1, further comprising first and second OCC sensing points positioned after the VGA enabling the offset cancellation circuit to sample the first and second output voltage components, respectively, for the first and second sample voltages.

7. The optical receiver according to claim 4, further comprising: a driver stage after the VGA for driving subsequent stages of the optical receiver; and first and second OCC sensing points positioned after the driver stage enabling the offset cancellation circuit to sample the first and second output voltage components, respectively, for the first and second sample voltages.

8. The optical receiver according to claim 1, wherein the DC cancellation circuit comprises: a voltage comparator for comparing a sample of each of the first and second input current components or the first and second input voltage components to the first and second reference voltages, respectively, generating first and second comparisons; and a current sink for sinking the DC portions of the first and second input current components based on the first and second comparisons.

9. The optical receiver according to claim 8, further comprising first and second DCCC sensing points positioned before the TIA enabling the DC cancellation circuit to sample the first and second input current components, respectively.

10. The optical receiver according to claim 8, further comprising first and second DCCC sensing points positioned after the TIA enabling the DC cancellation circuit to sample the first and second input voltage components, respectively.

11. The optical receiver according to claim 10, wherein the offset cancellation circuit comprises: a voltage comparator for determining an offset by comparing the samples of the first and second input voltage components; and a voltage summer for adding or subtracting the offset to or from one of the first or second reference voltages.

12. The optical receiver according to claim 8, wherein the offset cancellation circuit comprises a weighted summer capable of adding or subtracting a difference between the first and second voltage samples, and modifying the first and second reference voltages used by the current sink based on the difference.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The invention will be described in greater detail with reference to the accompanying drawings which represent preferred embodiments thereof, wherein:

(2) FIG. 1 is a schematic diagram of an optical receiver in accordance with an embodiment of the present invention;

(3) FIG. 2a is a schematic diagram of a trans-impedance amplifier (TIA) of the optical receiver of FIG. 1 with a DC cancellation circuit defining the output bias condition;

(4) FIG. 2b is a schematic diagram of a trans-impedance amplifier (TIA) of the optical receiver of FIG. 1 with a DC cancellation circuit defining the input bias condition;

(5) FIG. 3 is a schematic diagram of a differential input and differential output trans-impedance amplifier (TIA) of the optical receiver of FIG. 1 with a DC cancellation circuit and a offset cancellation circuit;

(6) FIG. 4 is a schematic diagram of an embodiment of a receiver with a DC cancellation circuit and a offset cancellation circuit with a different sampling location;

(7) FIG. 5 is a schematic diagram of an embodiment of a receiver with a DC cancellation circuit and a offset cancellation circuit with yet another sampling location;

(8) FIG. 6 is a schematic diagram a receiver utilizing the TIA of FIG. 3;

(9) FIG. 7 is a schematic diagram of the receiver of FIG. 4 with a predetermined offset;

(10) FIG. 8a is a plot of the VGA input voltage vs time with an introduced offset, as shown in the receiver of FIG. 7;

(11) FIG. 8b is a plot of the receiver output voltage (V) vs time (s) for the receiver of FIG. 7;

(12) FIG. 9 is a plot of Output Voltage offset (mV) from a Monte Carlo simulation with the offset cancellation circuit (OCC) ON and OFF;

(13) FIG. 10 is a plot of current (A) vs. time (s) for two differential current components;

(14) FIG. 11 is a plot of output voltage (V) vs. time (s) for two differential output voltage components; and

(15) FIGS. 12a to 12d are Monte Carlo plots of input and output voltages with and without offset cancellation.

DETAILED DESCRIPTION

(16) While the present teachings are described in conjunction with various embodiments and examples, it is not intended that the present teachings be limited to such embodiments. On the contrary, the present teachings encompass various alternatives and equivalents, as will be appreciated by those of skill in the art.

(17) With reference to FIG. 1, a receiver 1 includes a variable gain trans-impedance amplifier (TIA) 2 for converting a photodiode current signal into a voltage signal, a variable gain amplifier (VGA) 3 for amplifying the voltage signal, and a driver stage 4 for driving subsequent stages, e.g. an ADC. The front end of the receiver 1 may be connected to a general transducer, which may be contained in a photonic integrated circuit (PIC) 6 including one or more transducers, such as one or more photodetectors, and preferably a pair of photodiodes. The back end of the receiver 1 may be connected to an output load, e.g. a digital signal processor 7 for converting the output of the receiver 1 into digital signals.

(18) The receiver 1 includes a Gain Control Circuit (GCC) 8 to set the gain of the TIA 2 and the VGA 3, via TIA and VGA gain control signals 12 and 14, respectively, for a given range of input signal power and desired range of output signal power. The gain control circuit 8 is typically implemented as an open loop control or a close loop control. An open loop implementation sets the gain of the TIA 2 and the VGA 3 according to an overall gain control signal 9 from a device controller (not shown). A closed loop control senses the output signal power from the TIA 2, the VGA 3 or the driver stage 4, via feedback signals 15a and 15b to a power, e.g. voltage, detector in the gain control circuit 8, and varies the gain of the TIA 2 and the VGA 3 to set the desired output voltage magnitude. The closed loop mode is also known as automatic gain control (AGC).

(19) A DC cancellation circuit 21 is provided to maintain the receiver input bias while suppressing any DC component at the input generated by a optical-to-electrical transducer, e.g. a photodiode. The DC cancellation circuit 21 uses a closed loop 25 in which a sample voltage or current is compared to a reference voltage (or current) VREF. VREF may be the optimum input bias for the TIA 2, and therefore depends on the TIA circuit topology. Ideally, the VREF provides the best noise, bandwidth, linearity etc. according to the design specifications. Typically, VREF may be 0.3V to 1.5V, and ideally about 1V, but other TIA designs may utilize a VREF above or below these values. VREF is an on-chip (or off-chip) reference voltage that may be designed to be invariant, e.g. bandgap voltage, or have a temperature or process dependency. The closed loop 25 is used to define the output (FIG. 2a) or the input (FIG. 2b) bias condition. The reference voltage (or current) VREF is selected to guarantee proper operation of the receiver 1.

(20) With reference to FIG. 3, an embedded offset cancellation circuit 31 is used to modify, e.g. increase or decrease the magnitude, the reference voltage or current used by the DC cancellation circuit 21. Offset introduced by the transducer, in PIC 6, and offset generated in the receiver 1 are minimized overall with a small increase in area and power consumption. In general, an amplifier, e.g. TIA 2 or VGA 3, uses the DC cancellation circuit 21 to suppress DC components, either voltage or current. The closed loop 25 ensures that the sample point (either input or output) matches the reference voltage or current VREF used to define the closed loop condition.

(21) Careful design and manufacture may be done to ensure the information is not suppressed within the closed loop 25, which is typically achieved by selecting the closed loop maximum operating frequency well below the low cut-off frequency of the incoming signal.

(22) The example illustrated in FIG. 3 provides differential input currents IINP and IINN with amplification and conversion to differential output voltages VOUTP and VOUTN via the TIA 2, the VGA 3 and the driver 4. The DC cancellation circuit 21 defines the TIA input bias according to the reference voltage VREF. The embedded offset cancellation circuit 31 may use the same sensing points or separate sensing points (OCINP OCINN) just after the TIA 2 or just after the VGA 3 to sample the TIA output voltages VOUTP and VOUTN. The offset cancellation circuit 31 modifies the reference voltages (or currents) VREF1 and VREF2 used in the DC cancellation circuit 21. Extensive verification, e.g. verification of loop maximum frequency below signal minimum frequency, loop stability, nested loop stability, is required to ensure the variation in the reference voltages or currents VREF1 and VREF2 of the DC cancellation circuit 21 needed to compensate offset at the TIA output does not degrade the performance of the TIA 2.

(23) Flexibility in the location of the offset cancellation sensing points OCINP OCINN enables the correction of offset within the receiver path. For example, the sensing points OCINP OCINN may be located after the TIA 2, between the TIA 2 and the VGA 3, as in FIG. 3, after the driver 4, as in FIG. 4 or after the VGA 3, between the VGA 3 and the driver 4, as in FIG. 5.

(24) The DC cancellation sensing point is shown at the input prior to the TIA 2; however, other sensing points may also be used, e.g. in between the TIA 2 and the VGA 3.

(25) The interaction between the DC cancellation 21 and the offset cancellation 31 must be verified to avoid any penalty in the receiver performance

(26) Depending on the sensing point, the offset cancellation circuit 31 and the reference voltage or current VREF may be combined with different signs and weights.

(27) With reference to FIG. 6, the receiver 1 includes an implementation of the DC cancellation circuit 21 with the embedded offset cancellation circuit 31. The DC cancellation circuit 21 suppress DC components in the receiver input. Offset at the output of the TIA 2 is suppressed by sensing the voltage after the TIA 2, and modifying the DC cancellation reference voltage VREF accordingly.

(28) The offset cancellation circuit 31 includes a voltage comparator 32 with a first input resistor Ri1 for sensing the first voltage component, and a second input resistor Ri2 for sensing the second voltage component. The voltage output of the voltage comparator 32, i.e. the difference or offset between the two voltage components, is fed to a weighted summer 33 for combining with the reference voltage (or current) VREF. The weighted summer 33 adds or subtracts the output from the comparator, i.e. the offset cancellation circuit 31, to one of two reference voltage VREF1 and VREF2 signals provided to the DC cancellation circuit 21. Alternatively, a first portion, e.g. , of the offset is added to one reference voltage VREF1 and a second portion, e.g. , of the offset is subtracted from the other reference voltage VREF2.

(29) In the DC cancellation circuit 21, each reference voltage signal VREF1 and VREF2 is compared in voltage comparators OA1 and OA2 with one of the sensing input points taken at the input of the TIA 2. The difference between the sensed point and the modified reference voltage signals VREF1 and VREF2 is used to control a first terminal, e.g. gate, of first and second feedback transistors, e.g. NFET1 and NFET2, to sink the input DC current of the input current signals IIN_P and IIN_N via the second and third terminals, e.g. drain and source, of the first and second feedback transistors NFET1 and NFET2, and set the DC input voltage VIN_P and VIN_N.

(30) As an example, illustrated in FIG. 7, a predetermined offset Voffset is added in the high frequency path of the receiver 1. The added offset Voffset is corrected by the offset cancellation loop, which senses the receiver output voltage and modifies the TIA input voltage (FIG. 8a) such the output voltage does not have offset (FIG. 8b)

(31) Large gain (typically more than 70 dB) is required from the receiver 1, therefore, any asymmetry within the receiver 1 will generate an offset signal that can potentially degrade the output signal. Offset generated within a receiver path can take values comparable to the output voltage. Under that condition the information can be lost. FIG. 9 illustrates a Monte Carlo (MC) simulation with superimposed results when the offset cancellation circuit (OCC) 31 is OFF and ON. When the offset cancellation circuit is turned OFF, the offset measured at the receiver output is about +/240 mV. This value will affect the output voltage in the receiver 1, and therefore the incoming signal can be partially or completely lost. The offset compensation loop turned ON reduces the offset content to less than +/20 mV, i.e., more than one order of magnitude, as shown in the MC run with the offset cancellation circuit (OCC) ON (FIG. 9)

(32) With reference to FIG. 10, the DC cancellation circuit 21 sets the voltage at the inputs of the TIA 2 for proper operation. The input currents IIN_P and IIN_N contain a variable and a constant component, i.e. IIN_P=+Iin+Idc and IIN_N=Iin+Idc The variation of the single ended output terminals is shown in FIG. 10. In the example, IIN_P and IIN_N have a high frequency component and a DC component that is changing over time. The DC cancellation circuit 21 removes the DC component using a current sinker and a control loop that maintains stable the TIA input common-mode voltage. Therefore, the variation in DC component does not affect the output voltage, as shown in FIG. 11.

(33) Input voltage is set by the DC cancellation circuit 21. Process variation changes the input voltage VIN_P VIN_N. The offset cancellation does not affect the input voltage, as shown in FIG. 12a, 12b, where the input voltage distribution remains relatively constant irrespective of having the OCC ON or OFF.

(34) The output voltage does depend on the OCC 31, when turned on the output voltage variation reduces, FIG. 12c, 12d, and the difference between VOUT_P and VOUT_N (i.e., output offset) is even lower, as shown in FIG. 9.

(35) The foregoing description of one or more embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. It is intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.