Lead-Free Solder Alloy Comprising Sn, Bi and at Least One of Mn, Sb, Cu and its Use for Soldering an Electronic Component to a Substrate

Abstract

A solder alloy comprises 38.0-42.0 wt % bismuth (Bi), 0.01-2 wt % of at least one further element chosen from the group of manganese (Mn), antimony (Sb) and copper (Cu), the balance being tin (Sn), and is at least substantially free of nickel (Ni), and further preferably substantially free of silver (Ag). The solder alloy may be combined with a halide-free solder flux to constitute a solder paste, solder bath or solder wire. The solder paste is for instance used for soldering electronic component packages such as quad flat non-leaded (QFN) packages or for soldering surface mount devices (SMD), resulting in low void formation. The solder alloy may also be applied by means of wave-soldering or selective soldering.

Claims

1-24. (canceled)

25. A method of soldering an electronic component package and/or a surface mount device (SMD) to a substrate, the method comprising applying by wave-soldering or selective soldering a lead-free solder alloy having an alloy composition consisting substantially of 58.0-62.0 wt % tin (Sn), 38.0-41.0 wt % bismuth (Bi), 0.01-2.0 wt % of antimony (Sb), 0-1.0% of manganese (Mn), wherein the alloy composition is free of nickel (Ni).

26. The method as claimed in claim 25, wherein tin (Sn) is present in the alloy composition in an amount of 58.0-59.9 wt %.

27. The method as claimed in claim 25, wherein the lead-free solder alloy is substantially free of silver (Ag).

28. The method as claimed in claim 25, wherein the solder is applied by selective soldering at a speed of 10 mm/s or greater.

29. The method as claimed in claim 28, wherein the solder is applied by selective soldering at a speed of 20 mm/s or greater.

30. The method as claimed in claim 28, wherein the solder is applied by selective soldering at a speed of 30 mm/s or greater.

31. The method as claimed in claim 25, wherein the solder alloy is applied in a temperature range of 190 to 320 C.

32. The method as claimed in claim 25, wherein the solder alloy is further applied as a solder paste composition comprising a halide-free flux for soldering an electronic component package.

33. the method as claimed in claim 32, wherein the substrate is soldered entirely with a single solder alloy.

34. The method as claimed in claim 32, wherein the solder alloy has a particle size in the range of 10-40 m as defined by sieve analysis.

35. the method as claimed in claim 34, wherein the solder alloy has a particle size in the range of 20-30 m as defined by sieve analysis.

36. The method as claimed in claim 32, wherein the electronic component comprises a plurality of contacts and an exposed die pad, which contacts and which die pads are soldered to associated contacts on the substrate.

37. The method as claimed in claim 35, wherein the contacts are contact pads, which are at least partially present on a bottom side of the electric component package.

38. The method as claimed in claim 37, wherein the exposed die pad and the contact pads are arranged in a substantially co-planar way.

39. The method as claimed in claim 32, wherein the electronic component package is a quad-flat no lead (QFN) type package.

40. The method as claimed in claim 32, wherein the electronic component package is provided with solder balls.

41. The method as claimed in claim 40, wherein the solder balls are made of a SAC (tin-silver-copper) solder alloy.

42. The method as claimed in claim 32, wherein the soldering occurs at a reflow temperature of 200 C. or less.

43. The method as claimed in claim 42, wherein the reflow temperature is in the range of 180-190 C.

44. The method as claimed in claim 25, wherein the substrate is provided with a finish of the organic preservative type (OSP).

Description

EXAMPLES

[0034] In order to test reliability, void formation in so-called QFN packages was tested using X-ray analysis. The QFN-package is a package with an exposed die pad surrounded by a plurality of contact pads. The QFN package is a popular choice because of its thin and small profile, low weight and good thermal properties because of the exposed die pad and reduced lead inductance. It is similar to for instance QFP (quad flat package). In 2013, around 32.6 billion QFN packages have been assembled. Further variations on the QFN package are most likely to be developed. QFN packages typically comprise one or more integrated circuits. The plurality of contact pads is present at the four side edges of the package, typically extending both on a side face and the bottom face of the package. The number of contact pads is for instance in the range of 20-100. The pitch (heart-to-heart distance between neighbouring contact pads) is for instance in the range of 0.3-0.7 mm, and the width of the contact pad being about half of the pitch.

[0035] When performing X-ray analysis on soldered QFN packages (after reflow), excessive void formation can be observed under the exposed die pad of the QFN package, particularly with the SAC solders as commonly applied. A test carried out by applicant in investigations leading to the invention unexpectedly discovered that the void area can be more than 35% of the total area of the exposed die pad. Furthermore, it was found that the void formation can be different across a single substrate, typically a printed circuit board. This large void formation clearly has a negative impact on thermal conductivity, electric conductivity and mechanical strength of the assembled package.

[0036] Several lead-free solder alloys were tested. These are specified in Table 1.

TABLE-US-00001 TABLE 1 solder alloys Sn Bi Ag Cu Sb Mn Nr (wt %) (wt %) (wt %) (wt %) (wt %) (wt %) S1* 96.5 3.0 0.5 S2* 99 0.3 0.7 S3* 96 3 0.3 0.7 S4* 80 20 S5* 42 57 1 S6 76.5 23 0.5 S7 70.5 28.5 0.65 0.35 S8 68.2 31.5 0.05 0.25 S9 59.9 40 0.1 S10 59.5 40 0.5 S11 59.9 40 0.1 S12 59.8 40 0.1 0.1 (*= comparative example)

[0037] Solder pastes were prepared using Interflux DP5600 solder flux in a mixture of l0 wt % or 10.5 wt % flux and 89.5 wt % or 90 wt % solder alloy powder. This solder flux is specified for use in combination with low-melting Sn42Bi57Ag1 and Sn42Bi58 solder alloys. The solder paste is screen printed on testboard PCBs, using a MicroDEK 249 stencil printer, and a 120 m stencil with no reduction. Printing solder paste without any reduction will give the worst voiding results, and was therefore chosen for comparison of different solder alloys. In each experiment, 3 QFN type components are placed on the test PCB. The test PCB has OSP-Cu finish. Use was made of packages supplied by Amkor as MLF48 packages, with a size of 77 mm and an exposed die pad of 55 mm and 48 contact pads. After placing the packages on the test PCB, the PCBs are reflowed with an ERSA HotFlow 2/14 reflow oven.

[0038] Use was made of a standard linear reflow profile for lead-free soldering, with a peak temperature of 243 C. The standard linear reflow profile was adopted after initial experiments demonstrating that there was no major difference between a standard linear profile (with a peak at 235 C.) and a soak profile (having a soak platform at 200 C. and a peak at 250 C.).

[0039] After reflow, the QFN components are inspected using an Y. Cougar FeinFocus X-Ray system for void analysis. Void analysis is performed via contrast detection and describes, when inspecting the soldered component for the topside, the surface area that has voided and the surface area without voiding.

[0040] Table 2 shows test results for the voiding

TABLE-US-00002 TABLE 2 voiding results for compositions S1-S9 Lowest Nr voiding Median voiding Highest voiding Average St Dev S1* 27.18% 35.37% 42.11% 35.68% 3.74% S2* 21.03% 30.75% 44.54% 32.91% 8.79% S3* 4.10% 16.00% 41.01% 17.12% 12.51% S4* 4.92% 5.90% 17.96% 8.83% 5.45% S5* 3.96% 8.56% 20.21% 10.51% 5.78% S6 0.82% 3.73% 12.12% 5.05% 3.77% S7 2.27% 3.36% 6.37% 3.46% 1.73% S8 0.5% 3.20% 19.55% 4.99% 5.35% S9 0.0% 0.55% 3.88% 1.18% 1.23%

[0041] Further experiments were carried out with some further compositions. The test protocol was identical, except that the reflow temperature was chosen to have a peak temperature of 200 C. Table 3 shows the results.

TABLE-US-00003 TABLE 3 void test results obtained with solder alloys S10-11-12. Lowest Median Highest Nr voiding voiding voiding Average St Dev S10 1.0% 3.27% 6.47% 3.79% 2.10% S11 7.02% 7.81% 9.18% 8.05% 0.89% S12 1.83% 3.57% 7.75% 4.13% 2.13%

[0042] Further tests were carried out with the compositions S9. The compounds were subjected to two different standard reflow profiles, one for lead-free (243 C. peak temperature) and one for leaded components (200 C.). Furthermore the finish of the test board was varied, i.e. as OSP Copper (OSP Cu), Immersion Sn (Imm Sn) and NiAu, as known per se to the skilled person. Voiding results are shown in Table 4

TABLE-US-00004 TABLE 4 voiding results for alloy S9 with different finishings and at different peak temperatures. Peak Lowest Highest Sample Finish temperature value Median value Average S9 OSP Cu 243 C. 1.5% 1.8% 3.9% 2.5% S9 OSP Cu 200 C. 0.3% 1.1% 6.5% 1.4% S9 NiAu 243 C. 0.0% 0.15% 1.0% 0.3% S9 NiAu 200 C. 1.0% 2.6% 4.2% 2.5% S9 Imm Sn 200 C. 0.2% 1.1% 5.2% 1.7%