INTEGRATION CIRCUIT AND METHOD FOR PROVIDING AN OUTPUT SIGNAL

Abstract

In an embodiment an integration circuit has a first input terminal configured to receive a first input signal, a second input terminal configured to receive a second input signal, an output terminal to provide an output signal as a function of the first and the second input signal, a first and a second amplifier, each being switchably connected between the first or the second input terminal and the output terminal, and a capacitor which is switchably coupled in a feedback loop either of the first or of the second amplifier such that the capacitor and one of the first and the second amplifier form an inverting integrator providing the output signal. Therein the integration circuit is prepared to be operated in a first and a second subphase, wherein in each of first and second subphases one of the first and the second input signals is supplied to the inverting integrator and the respective other one of first and the second input signals is supplied to the respective other one of the first and the second amplifier.

Claims

1. An integration circuit having a first input terminal configured to receive a first input signal, a second input terminal configured to receive a second input signal, an output terminal to provide an output signal as a function of the first and the second input signal, a first and a second amplifier, each being switchably connected between either the first or the second input terminal and the output terminal, and a capacitor which is switchably coupled in a feedback loop either of the first or of the second amplifier such that the capacitor and one of the first and the second amplifier form an inverting integrator providing the output signal, wherein the integration circuit is prepared to be operated in a first and a second subphase, wherein in each of first and second subphases one of the first and the second input signals is supplied to the inverting integrator and a respective other one of first and the second input signals is supplied to a respective other one of the first and the second amplifiers, and wherein the output signal is provided as a function of a time continuous integration of a difference between or a ratio of the first and the second input signal.

2. The integration circuit according to claim 1, wherein the second input signal is complementary to the first input signal and wherein each of the first input signal and the second input signal comprises a current signal.

3. The integration circuit according to claim 1, wherein each of the first input signal, the second input signal and the output signal is a single-ended signal.

4. The integration circuit according to claim 1, wherein the integration circuit is prepared to be operated in a third and a fourth subphase, wherein in each of third and fourth subphases with respect to the first and second subphases the respective other one of the first and the second amplifier forms the inverting integrator, and wherein in each of third and fourth subphases one of the first and the second input signals is supplied to the inverting integrator and the respective other one of first and the second input signals is supplied to the respective other one of the first and the second amplifier with respect to the preceding third or fourth subphase.

5. The integration circuit according to claim 4, wherein a transition between the first and the second subphase and vice versa and a transition between the third and the fourth subphase and vice versa is defined by interchanging a connection of the first and the second input terminal to the inverting integrator or the respective other one of the first and the second amplifier with respect to a connection of the first and the second input terminal to the inverting integrator or the respective other one of the first and the second amplifier during a preceding subphase.

6. The integration circuit according to claim 4, wherein the integration circuit is prepared to be operated during a predefined measurement period which is divided in a first and a second phase, wherein during the first phase of the measurement period a sequence having the first and the second subphases is repeated, and wherein during the second phase of the predefined measurement period a sequence having the third and the fourth subphases is repeated.

7. The integration circuit according to claim 6, wherein a transition from the first to the second phase is defined by changing over a connection of the capacitor in the feedback loop of the first or of the second amplifier from the first to the second amplifier or vice versa such that with respect to the preceding first or second phase the other amplifier and the capacitor form the inverting integrator.

8. The integration circuit according to claim 7, wherein the changing over the connection of the capacitor is effected such that in the first phase the first amplifier and the capacitor form the inverting integrator which is prepared to provide the output signal and in the second phase the second amplifier and the capacitor form the inverting integrator or vice versa.

9. The integration circuit according to claim 4, wherein the first amplifier has an inverting input terminal which is switchably connected either to the first or to the second input terminal as a function of the first, second, third and fourth subphases, and a non-inverting input terminal which receives a reference signal, and the second amplifier has an inverting input terminal which is switchably connected either to the first or to the second input terminal as a function of the first, second, third and fourth subphases, and a non-inverting input terminal which receives the reference signal.

10. The integration circuit according to claim 8, wherein the feedback loop of the first amplifier extends between an output of the first amplifier and its inverting input terminal, and wherein the feedback loop of the second amplifier extends between an output of the second amplifier and its inverting input terminal.

11. The integration circuit according to claim 1, wherein the amplifier which does not form the inverting integrator in the respective subphase is configured in unity feedback forming a dummy amplifier.

12. Delta sigma converter, having an integration circuit according to claim 1, a comparator circuit which is coupled to the output terminal of the integration circuit, the comparator circuit being prepared to provide a comparator signal as a function of a comparison of the output signal of the integration circuit with a threshold signal.

13. A temperature sensor having a delta sigma converter according to claim 12.

14. Method for providing an output signal having the following steps in a first subphase feeding a first input signal to a first amplifier forming an inverting integrator, feeding a second input signal to a second amplifier forming a dummy amplifier and providing an output signal by integrating the first input signal, and in a second subphase feeding the first input signal to the second amplifier forming the dummy amplifier, feeding the second input signal to the first amplifier forming the inverting integrator and providing the output signal by integrating the second input signal, wherein the dummy amplifier is configured in unity feedback, and wherein the output signal is provided as a function of a time continuous integration of a difference between or a ratio of the first and the second input signal.

15. Method for providing an output signal according to claim 14, further comprising in a third subphase feeding the first input signal to the first amplifier forming the dummy amplifier, feeding the second input signal to the second amplifier forming the inverting integrator and providing the output signal by integrating the second input signal, and in a fourth subphase feeding the first input signal to the second amplifier forming the inverting integrator, feeding the second input signal to the first amplifier forming the dummy amplifier and providing the output signal by integrating the first input signal, wherein first and second subphases are repeated during a first phase of a predefined measurement period, and third and fourth subphases are repeated during a second phase of the predefined measurement period.

16. The integration circuit according to claim 1, wherein each of the first input signal, the second input signal and the output signal is a single-ended signal, and wherein the integration circuit is prepared to be operated in a third and a fourth subphase, wherein in each of third and fourth subphases with respect to the first and second subphases the respective other one of the first and the second amplifier forms the inverting integrator, and wherein in each of third and fourth subphases one of the first and the second input signals is supplied to the inverting integrator and the respective other one of first and the second input signals is supplied to the respective other one of the first and the second amplifier with respect to the preceding third or fourth subphase.

17. The integration circuit according to claim 16, wherein a transition between the first and the second subphase and vice versa and a transition between the third and the fourth subphase and vice versa is defined by interchanging a connection of the first and the second input terminal to the inverting integrator or the respective other one of the first and the second amplifier with respect to a connection of the first and the second input terminal to the inverting integrator or the respective other one of the first and the second amplifier during a preceding subphase.

18. The integration circuit according to claim 17, wherein the integration circuit is prepared to be operated during a predefined measurement period which is divided in a first and a second phase, wherein during the first phase of the measurement period a sequence having the first and the second subphases is repeated, and wherein during the second phase of the predefined measurement period a sequence having the third and the fourth subphases is repeated.

19. The integration circuit according to claim 18, wherein a transition from the first to the second phase is defined by changing over a connection of the capacitor in the feedback loop of the first or of the second amplifier from the first to the second amplifier or vice versa such that with respect to the preceding first or second phase the other amplifier and the capacitor form the inverting integrator.

20. The integration circuit according to claim 19, wherein the changing over the connection of the capacitor is effected such that in the first phase the first amplifier and the capacitor form the inverting integrator which is prepared to provide the output signal and in the second phase the second amplifier and the capacitor form the inverting integrator or vice versa.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0049] The text below explains the proposed integration circuit and corresponding method in detail using exemplary embodiments with reference to the drawings. Components and circuit elements that are functionally identical or have the identical effect bear identical reference numbers. In so far as circuit parts or components correspond to one another in function, a description of them will not be repeated in each of the following figures.

[0050] FIG. 1 shows an embodiment example of the proposed integration circuit;

[0051] FIG. 2 shows an exemplary timing diagram for the proposed integration circuit;

[0052] FIG. 3A shows an embodiment example of the proposed integration circuit during the first subphase;

[0053] FIG. 3B shows an embodiment example of the proposed integration circuit during the second subphase;

[0054] FIG. 3C shows an embodiment example of the proposed integration circuit during the third subphase;

[0055] FIG. 3D shows an embodiment example of the proposed integration circuit during the fourth subphase;

[0056] FIG. 4 shows a temperature sensor having a delta sigma converter as proposed.

DETAILED DESCRIPTION

[0057] FIG. 1 shows an embodiment example of the proposed integration circuit. The integration circuit has a first and a second input terminal In1, In2, a first amplifier A1, a second amplifier A2, a capacitor C and an output terminal Out. The first input terminal In1 is configured to receive a first input signal I1 which comprises, for example, a first input current. The second input terminal In2 is configured to receive a second input signal I2 which comprises, for instance, a second input current. The first amplifier A1 is switchably connected between the first and the second input terminal In1, In2 and the output terminal Out. The second amplifier A2 is switchably connected between the first and the second input terminal In1, In2 and the output terminal Out. In detail, the first input terminal In1 is switchably connected to an inverting input terminal of the first amplifier A1 by a first switch S1. The first input terminal In1 is further switchably connected to an inverting input terminal of the second amplifier A2 by means of a second switch S2. The second input terminal In2 is switchably connected to the inverting input of the first amplifier A1 by a third switch S3. The second input terminal In2 is further coupled to the inverting input of the second amplifier A2 by means of a fourth switch S4.

[0058] The capacitor C is switchably coupled in a feedback loop either of the first amplifier A1 or of the second amplifier A2 by means of a first chopping switch CS1 and a second chopping switch CS2. The amplifier out of first and second amplifiers A1, A2 which has the capacitor C switched into its feedback loop by means of chopping switches CS1 and CS2 forms an inverting integrator. The respective other amplifier out of first and second amplifiers A1, A2 is configured in unity feedback with its output being connected to its inverting input by means of chopping switches CS1, CS2 thereby forming a dummy or replica amplifier. An output of the amplifier out of first and second amplifiers A1, A2 which forms the inverting integrator is switched to the output terminal Out of the integration circuit by means of the second chopping switch CS2 for providing the output signal Out. The first and the second chopping switch CS1, CS2 are concurrently controlled by a second clock signal clk2.

[0059] A chopping switch is also called a swapping switch, implementation of which is known to those skilled in the art.

[0060] First, second, third and fourth switches S1, S2, S3, S4 are controlled by a first clock signal clk1 and the inverted first clock signal clk1. In detail, the second and the third switch S2, S3 are controlled by the first clock signal clk1, whereas the first and the fourth switch S1, S4 are controlled by the inverted first clock signal clk1.

[0061] The non-inverting inputs of the first and the second amplifiers A1, A2 each receive a reference signal Vref.

[0062] FIG. 1 also shows parasitic capacitances which build up at the input terminals In1, In2. Namely, a first parasitic capacitance Cp1 builds up at the first input terminal In1 with respect to a reference potential terminal 10. Similarly, at the second input terminal In2 a second parasitic capacitance Cp2 builds up with reference to the reference potential terminal 10. Operation of the integration circuit will be described below with reference to FIG. 2 and FIGS. 3A to 3D.

[0063] FIG. 2 shows an exemplary timing diagram for the proposed integration circuit. The first and the second clock signals clk1, clk2 are depicted with respect to time t. A measurement period of the integration circuit is made up of two phases, namely a first phase P1 and a second P2. First and second phases P1, P2 are determined by the second clock signal clk2. The first phase P1 further has a number of first and second subphases SP1, SP2 determined by the first clock signal clk1. The second phase P2 has a number of third and fourth subphases SP3, SP4 which also are determined by the first clock signal clk1.

[0064] FIG. 3A shows an embodiment example of the proposed integration circuit during the first subphase. During the first subphase SP1 as of FIG. 2 the first amplifier A1 is configured as inverting integrator Int, whereas the second amplifier A2 forms a dummy amplifier. Under control of the first clock signal clk1, the second and the third switches S2, S3 are closed, whereas the first and the fourth switches S1, S4 are opened. Consequently, the second input signal I2 is provided to the inverting integrator Int and the first input signal I1 is provided to the dummy amplifier A2. The output signal Vout is provided as an integration of the second input signal In1. A first voltage V1 drops at the first input terminal In1. A second voltage V2 drops at the second input terminal In2.

[0065] FIG. 3B shows an embodiment example of the proposed integration circuit during the second subphase. The first amplifier A1 continues to form the inverting integrator Int together with the capacitor C. Under control of the first clock signal clk1 first and fourth switches S1, S4 are closed and second and third switches S2, S3 are opened. Consequently, the first input signal I1 is supplied to the inverting integrator Int. The second input signal I2 is supplied to the dummy amplifier A2. The output signal Vout is provided as a function of an integration of the first input signal I1.

[0066] It can be seen that instead of switching one of the input terminals In1, In2 which is currently not used for integration, i.e. it is idle, to a reference potential terminal as in state of the art implementations described in the opening part of this application, according to the proposed integration circuit the input terminal whose input signal is not currently integrated is switched to the dummy amplifier. Because of a matching between the first and the second amplifiers A1, A2 and consequently matched virtual ground voltages, a voltage swing at the input terminals In1, In2 is greatly reduced. There is no need to increase a supply voltage nor to decrease a frequency of the first clock signal clk1. The proposed integration circuit can be operated with a clock frequency of approximately 1 MHz, for example.

[0067] A voltage swing at an input node therein denotes the difference in voltage at this node which occurs when switching over from the first subphase SP1 to the second subphase SP2 and vice versa.

[0068] FIG. 3C shows an embodiment example of the proposed integration circuit during the third subphase SP3. Under control of the second clock signal clk2 the integration circuit is operated in the second phase P2 according to FIG. 2 and the roles of inverting integrator and dummy amplifier are swapped between first and second amplifier A1, A2 using the chopping switches CS1, CS2 of FIG. 1. Consequently, during the third subphase SP3 the second amplifier A2 forms the inverting integrator Int together with the capacitor C and provides the output signal Vout. The first amplifier A1 forms the dummy amplifier configured in unity feedback. Under control of the first clock signal clk1 the switches are operated such that the first input signal I1 is supplied to the dummy amplifier A1 and the second input signal I2 is provided to the inverting integrator Int. The output signal Vout is provided in function of an integration of the second input signal I2. Therein, clk2 represents the inverted second clock signal clk2.

[0069] FIG. 3D shows an embodiment example of the proposed integration circuit during the fourth subphase. In the fourth subphase SP4 as of FIG. 2 the second amplifier A2 continues to form the inverting integrator Int. Under control of the first clock signal clk1, the first input signal In1 is supplied to the inverting integrator Int and the second input signal I2 is supplied to the dummy amplifier A1. The output signal Vout is provided as a function of an integration of the first input signal I1.

[0070] It can be seen that during switchover from the third to the fourth subphase SP3, SP4 the input signals of first and second amplifiers A1, A2 are swapped. Thereby a voltage swing across the parasitic capacitances Cp1, Cp2 of FIG. 1 is greatly reduced. Furthermore, by swapping the roles of inverting integrator Int and dummy amplifier between first and second amplifiers A1, A2 when switching over from the first phase P1 to the second phase P2 in the operation of the integration circuit, a residual swing which is caused by mismatch of the operational amplifiers and potential differences in offsets is further reduced. This residual error is cancelled on average.

[0071] FIG. 4 shows a temperature sensor having a delta sigma converter as proposed. The delta sigma converter Conv has an integration circuit IC as proposed and described above and a comparator circuit Cmp which is coupled to the output of the integration circuit IC. The comparator circuit Cmp compares the output signal Vout of the integration circuit IC to a threshold signal Vth and therefrom provides a comparison signal Sc.

[0072] The comparison signal Sc is provided to a counter component Ctr which provides a number of zero crossings of the comparison signal Sc. After some further filtering a temperature signal Stmp is provided.

[0073] When the delta sigma converter Conv is used in a temperature sensor a bipolar frontend FE is applied to provide the first and the second input signals I1, I2 as is known to those skilled in the art.

[0074] The bipolar frontend FE has a proportional to absolute temperature, PTAT, sensor which provides the first input signal I1 in the form of the first input current. The bipolar frontend further has a complementary to absolute temperature, CTAT, sensor which provides the second input signal I2 in the form of the second input current. The integration circuit IC within the delta sigma converter Conv provides a digital pulse modulated signal that represents the ratio of first to second input signal I1, I2 in the form of the comparison signal Sc. After applying digital post-processing in the form of the counter Ctr, the measured temperature is digitally represented in the temperature signal Stmp.

[0075] It is to be understood that any feature described in relation to any one embodiment may be used alone, or in combination with other features described, and may also be used in combination with one or more features of any other of the embodiments, or any combination of any other of the embodiments unless described as alternative. Furthermore, equivalents and modifications not described above may also be employed without departing from the scope of the integration circuit and method which are defined in the accompanying claims.