Room-temperature-bonded semiconductor device and manufacturing method of room-temperature-bonded semiconductor device

Abstract

Provided is a semiconductor device formed by performing bonding at room temperature with respect to a wafer in which bonded electrodes and insulating layers and are respectively exposed to front surfaces, including a bonding interlayer which independently exhibits non-conductivity and exhibits conductivity by being bonded to the bonded electrodes, between the front surfaces.

Claims

1. A room-temperature-bonding semiconductor device, comprising: one substrate with semiconductor base materials including conductive materials and insulating materials in a surface thereof as a bonded surface; another substrate with semiconductor base materials including conductive materials and insulating materials in a surface thereof as a bonded surface; and a bonding interlayer which is disposed between the one substrate and the another substrate in contact with the entire bonded surface of the one substrate and the entire bonded surface of the another substrate and which has portions with conductivity by contact with the conductive materials of the one substrate and the another substrate which ensure the conductivity between the conductive materials of the one substrate and the conductive materials of the another substrate and portions with non-conductivity in contact with the insulating materials of the one substrate and the another substrate.

2. The room-temperature-bonded semiconductor device according to claim 1, wherein the insulating materials of the one substrate and the insulating materials of the another substrate are bonded together via the bonding interlayer.

3. The room-temperature-bonded semiconductor device according to claim 1, wherein the bonding interlayer is formed of an amorphous semiconductor material.

4. The room-temperature bonded semiconductor device according to claim 1, wherein at least one of the one substrate and the another substrate is formed such that the conductive materials are formed to be protruded in a direction perpendicular to the bonding interlayer to the bonding interlayer compared to the insulating materials a height position of the insulating material of the bonded surface is lower than that of the conductive material.

5. A manufacturing method of a room-temperature-bonded semiconductor device including, comprising: one substrate with semiconductor base materials including conductive materials and insulating materials being formed in a surface thereof as a bonded surface; another substrate with semiconductor base materials including conductive materials and insulating materials being formed in a surface thereof as a bonded surface; and a bonding interlayer which is disposed between the one substrate and the another substrate in contact with the entire bonded surface of the one substrate and the entire bonded surface of the another substrate, one surface thereof being bonded to the bonded surface of the one substrate and another surface thereof being bonded to the bonded surface of the another substrate, and which has portions with conductivity obtained by the contact with the conductive materials of the one substrate and the another substrate bonded thereto and portions with non-conductivity bonded to the insulating materials of the one substrate and the another substrate, the method comprising the steps of: respectively activating the bonded surfaces of the substrates; after the activating step, forming a bonding interlayer which independently exhibits non-conductivity and exhibits conductivity by being bonded to the conductive material, on at least one of the activated bonded surfaces; and after the forming step, performing pressure-welding with respect the one substrate and the another substrate via the bonding interlayer, wherein, in the forming step, a semiconductor material is sputtered by being irradiated with a fast atom beam, and thus, the bonding interlayer is formed on the bonded surface of the one substrate, and then, the bonding interlayer formed on the bonded surface is irradiated with a fast atom beam, and a part of the semiconductor material forming the bonding interlayer is sputtered, and thus, the bonding interlayer is formed on the bonded surface of the another substrate.

6. A manufacturing method of a room-temperature-bonded semiconductor device including one substrate with semiconductor base materials including conductive materials and insulating materials being formed in a surface thereof as a bonded surface; another substrate with semiconductor base materials including conductive materials and insulating materials being formed in a surface thereof as a bonded surface; and a bonding interlayer which is disposed between the one substrate and the another substrate in contact with the entire bonded surface of the one substrate and the entire bonded surface of the another substrate, one surface thereof being bonded to the bonded surface of the one substrate and another surface thereof being bonded to the bonded surface of the another substrate, and which has portions with conductivity obtained by the contact with the conductive materials of the one substrate and the another substrate bonded thereto and portions with non-conductivity bonded to the insulating materials of the one substrate and the another substrate, the method comprising the steps of: respectively activating the bonded surfaces of the substrates; after the activating step, forming a bonding interlayer which independently exhibits non-conductivity and exhibits conductivity by being bonded to the conductive material, on at least one of the activated bonded surfaces; and after the forming step, performing pressure-welding with respect to the one substrate and the another substrate via the bonding interlayer, wherein at least one of the one substrate and the another substrate is formed such that a height position of the insulating material of the bonded surface is lower than that of the conductive material, a pressure-welding load is imparted to the conductive material at the time of performing pressure welding with respect to the substrates, the conductive materials are directly bonded together and thus, the bonding interlayer is broken by the conductive material.

7. The manufacturing method of a room-temperature-bonded semiconductor device according to claim 5, further comprising a step of: after the pressure-welding step, heating the one substrate and the another substrate at a predetermined temperature.

8. The manufacturing method of a room-temperature-bonded semiconductor device according to claim 5, wherein the bonding interlayer is formed by vapor deposition, sputtering, or chemical vapor deposition of the semiconductor material.

9. The manufacturing method of a room-temperature-bonded semiconductor device according to claim 5, wherein at least one substrate and the another substrate is formed such that a height position of the insulating material of the bonded surface is lower than that of the conductive material, and a pressure-welding load is imparted to the conductive material at the time of performing pressure-welding with respect to the substrates, the conductive material are directly bonded together and thus, the bonding interlayer is broken by the conductive material.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) FIG. 1 is a sectional view schematically illustrating a configuration of a bonding at room temperature device to which a semiconductor device according to this embodiment is bonded.

(2) FIG. 2 is a sectional view schematically illustrating configurations of a first wafer and a second wafer before bonding.

(3) FIG. 3 is a sectional view schematically illustrating a configuration of a semiconductor device formed by bonding the first wafer and the second wafer together.

(4) FIG. 4 is a sectional view schematically illustrating a state where the first wafer and the second wafer are bonded together.

(5) FIG. 5 is a transmission electron microscope photograph illustrating a bonding interface of SiO.sub.2/SiO.sub.2 as an insulating layer.

(6) FIG. 6 is a transmission electron microscope photograph illustrating a bonding interface of Cu/Cu as a junction electrode.

(7) FIG. 7 is a graph illustrating an EELS spectrum of an Si-L absorption edge at a measurement point.

(8) FIG. 8 is a graph illustrating an EELS spectrum of an OK absorption edge at the measurement point.

(9) FIG. 9 is a graph illustrating a relationship between a current and a voltage in SiO.sub.2/SiO.sub.2 bonding.

(10) FIG. 10 is a graph illustrating the EELS spectrum of the Si-L absorption edge at the measurement point.

(11) FIG. 11 is a graph illustrating an EELS spectrum of a Cu-L absorption edge at the measurement point.

(12) FIG. 12 is a graph illustrating a relationship between a current and a voltage in Cu/Cu bonding.

(13) FIG. 13A is a step explanatory diagram illustrating a step of bonding the first wafer and the second wafer together.

(14) FIG. 13B is a step explanatory diagram illustrating a step of bonding the first wafer and the second wafer together.

(15) FIG. 13C is a step explanatory diagram illustrating a step of bonding the first wafer and the second wafer together.

(16) FIG. 13D is a step explanatory diagram illustrating a step of bonding the first wafer and the second wafer together.

(17) FIG. 13E is a step explanatory diagram illustrating a step of bonding the first wafer and the second wafer together.

(18) FIG. 13F is a step explanatory diagram illustrating a step of bonding the first wafer and the second wafer together.

(19) FIG. 14A is a step explanatory diagram illustrating another step of bonding the first wafer and the second wafer together.

(20) FIG. 14B is a step explanatory diagram illustrating another step of bonding the first wafer and the second wafer together.

(21) FIG. 14C is a step explanatory diagram illustrating another step of bonding the first wafer and the second wafer together.

(22) FIG. 14D is a step explanatory diagram illustrating another step of bonding the first wafer and the second wafer together.

(23) FIG. 15A is a sectional view schematically illustrating a configuration before a first wafer and a second wafer according to another embodiment are bonded together.

(24) FIG. 15B is a sectional view schematically illustrating a configuration of a state where the first wafer and the second wafer according to another embodiment are bonded together.

DESCRIPTION OF EMBODIMENTS

(25) Hereinafter, embodiments according to the present invention will be described with reference to the drawings. Furthermore, the present invention is not limited by the following embodiments. In addition, constituents of the following embodiments include a constituent which can be easily substituted by a person skilled in the art, or substantially the same constituent.

(26) FIG. 1 is a sectional view schematically illustrating a configuration of a bonding at room temperature device to which a semiconductor device is bonded according to this embodiment. As illustrated in FIG. 1, a bonding at room temperature device 10 includes a vacuum chamber 11, an upper side stage 12 and a lower side stage 13 which are disposed in the vacuum chamber 11, fast atom beam sources (FAB) 14 and 15, and a vacuum evacuation device 16.

(27) The vacuum chamber 11 is a container sealing the inside from the environment, and the vacuum evacuation device 16 evacuates gas from the inside of the vacuum chamber 11. Accordingly, the inside of the vacuum chamber 11 is in a vacuum atmosphere. Further, the vacuum chamber 11 includes a gate (not illustrated) which allows an internal space of the vacuum chamber 11 to be communicated with or to be separated from the outside.

(28) The upper side stage 12 includes an electrostatic chuck 12A formed in the shape of a disk, and a pressure-welding mechanism 12B moving the electrostatic chuck 12A up and down in a vertical direction. The electrostatic chuck 12A includes a dielectric layer on a lower end of the disk, applies a voltage to the dielectric layer, and adsorbs and supports a first wafer (a substrate) 17 on the dielectric layer by an electrostatic force. The pressure-welding mechanism 12B translates the electrostatic chuck 12A with respect to the vacuum chamber 11 in the vertical direction according to the manipulation of a user.

(29) The lower side stage 13 is a stage supporting a second wafer (a substrate) 18 on an upper surface thereof, and includes a transport mechanism (not illustrated). The transport mechanism translates the lower side stage 13 in a horizontal direction according to the manipulation of the user, and rotatively moves the lower side stage 13 around a rotation axis which is parallel to the vertical direction. In addition, the lower side stage 13 may have a mechanism which includes a dielectric layer on an upper end thereof, applies a voltage to the dielectric layer, and adsorbs and supports the second wafer 18 on the dielectric layer by an electrostatic force.

(30) The fast atom beam sources 14 and 15 emits a neutral atomic beam (for example, an argon Ar atom) used for activating a front surface of the wafer. One fast atom beam source 14 is disposed towards the first wafer 17 which is supported on the upper side stage 12, and the other fast atom beam source 15 is disposed towards the second wafer 18 which is supported on the lower side stage 13. The neutral atomic beam is emitted, and thus, each of the front surfaces of the first wafer 17 and the second wafer 18 is activated. In addition, other activation units (for example, an ion gun or plasma) may be used for activating each of the wafers, instead of the fast atom beam sources 14 and 15.

(31) Next, a semiconductor device 20 which is subjected to bonding at room temperature by using the bonding at room temperature device 10 will be described. FIG. 2 is a sectional view schematically illustrating the configurations of the first wafer and the second wafer before bonding, and FIG. 3 is a sectional view schematically illustrating the configuration of the semiconductor device which is formed by bonding the first wafer and the second wafer together. As illustrated in FIG. 2, the first wafer 17 includes a first insulating layer (an insulating material) 22 formed by being laminated on a first semiconductor base material 21, and a first bonded electrode (a conductive material) 23 formed on a first insulating layer 22. Each of the first insulating layer 22 and the first bonded electrode 23 is formed by being exposed to a front surface 17A of the first wafer 17, and the front surface 17A bonding as a bonded surface. In addition, the second wafer 18 includes a second insulating layer (an insulating material) 25 formed by being laminated on a second semiconductor base material 24, and a second bonded electrode (a conductive material) 26 formed on a second insulating layer 25. Each of the second insulating layer 25 and the second bonded electrode 26 is formed by being exposed to a front surface 18A of the second wafer 18, and the front surface 18A functions as a bonded surface. The front surfaces 17A and 18A are formed as a flat surface, and the front surfaces 17A and 18A are closely bonded together.

(32) In the first semiconductor base material 21 and the second semiconductor base material 24, for example, single crystal silicon (Si) is used, and materials such as single crystal germanium (Ge), gallium arsenide (GaAs) or silicon carbide (SiC) can be used. In addition, in the first semiconductor base material 21 and the second semiconductor base material 24, not only the same type of material but also different types of materials may be used.

(33) The first insulating layer 22 and the second insulating layer 25 are formed of an oxide or a nitride of the semiconductor base material on the front surfaces 17A and 18A sides. Specifically, in a case where single crystal silicon (Si) is used as the semiconductor base material, a silicon oxide film (SiO.sub.2) or a silicon nitride film (Si.sub.3N.sub.4) is formed by film formation in an oxidizing furnace, a nitriding furnace, a chemical vapor deposition (CVD) device, or the like, as the first insulating layer 22 and the second insulating layer 25. In this embodiment, the silicon oxide film (SiO.sub.2) is formed. In addition, the first junction electrode 23 and the second bonded electrode 26 are formed of a material having excellent conductivity, for example, copper (Cu). A wiring material is connected to the first bonded electrode 23 and the second bonded electrode 26, and thus, an electronic circuit or various elements are formed.

(34) In a case where the first wafer 17 and the second wafer 18 are bonded together, and as illustrated in FIG. 2 and FIG. 3, the front surfaces 17A and 18A as the bonded surface face each other, and the bonding at room temperature is performed by using the bonding at room temperature device 10 described above. In this case, the first bonded electrode 23 of the first wafer 17 and the second bonded electrode 26 of the second wafer 18 are bonded together, the first insulating layer 22 of the first wafer 17 and the second insulating layer 25 of the second wafer 18 are bonded together. In the bonding at room temperature, the materials of the first bonded electrode 23 and the second bonded electrode 26 are bonded together, but the first insulating layer 22 and the second insulating layer 25 are the silicon oxide film (SiO.sub.2) or the silicon nitride film (Si.sub.3N.sub.4), and thus, are not able to be directly bonded together. For this reason, in this configuration, as illustrated in FIG. 4, a bonding interlayer 30 for simultaneously joining the bonded electrode and the insulating layer together is disposed between the front surface 17A of the first wafer 17 and the front surface 18A of the second wafer 18.

(35) The bonding interlayer 30 is a thin film for bonding the front surface 17A of the first wafer 17 and the front surface 18A of the second wafer 18 together, and is formed of an amorphous semiconductor material (for example, amorphous silicon). According to the studies of the present inventors, it is determined that the amorphous semiconductor material (for example, amorphous silicon) independently (in a single body) exhibits non-conductivity, but exhibits conductivity by being bonded to metals or the like. For this reason, the amorphous semiconductor material is used as the bonding interlayer 30, and thus, it is possible to rigidly join the first insulating layer 22 and the second insulating layer 25 together while retaining non-conductivity (insulating properties) between the first insulating layer 22 and the second insulating layer 25. Further, it is possible to ensure conductivity between the first bonded electrode 23 and the second bonded electrode 26 without degrading electric properties between the first bonded electrode 23 and the second bonded electrode 26. That is, the bonding interlayer 30 is formed by including a region (an insulating bonded portion 30a) which bonds the first insulating layer 22 and the second insulating layer 25 together while retaining the non-conductivity (the insulating properties), and a region (a conductive junction portion 30b) which has conductivity and bonds the first bonded electrode 23 and the second bonded electrode 26 together.

(36) Next, the bonding interlayer 30 will be described in detail. FIG. 5 is a transmission electron microscope photograph illustrating a bonding interface of SiO.sub.2/SiO.sub.2 as the insulating layer, and FIG. 6 is a transmission electron microscope photograph illustrating a bonding interface of Cu/Cu as the junction electrode. A transmission electron microscope (TEM) is an electron microscope in which an electron beam is applied to an observation target, and an interference image produced by electrons transmitted through the observation target is enlarged and observed.

(37) As illustrated in FIG. 5, an amorphous silicon (a-Si) layer as the bonding interlayer 30 (an insulating bonded portion 30a) is formed on the bonding interface of SiO.sub.2/SiO.sub.2 as the first insulating layer 22 and the second insulating layer 25. In addition, as illustrated in FIG. 6, similarly, an amorphous silicon (a-Si) layer as the bonding interlayer 30 (a conductive bonded portion 30b) is formed on the bonding interface of Cu/Cu as the first bonded electrode 23 and the second bonded electrode 26. Both of the bonding interlayers 30 are formed to have a thickness of approximately 7 nm to 9 nm, and a void (an air gap) does not exist between the bonding interlayer 30 and SiO.sub.2 or Cu, and thus, a sufficient adhesion state can be obtained.

(38) The bonding interlayer 30 is formed on the bonded surface of the insulating layer (SiO.sub.2) and the bonded electrode (Cu) by sputtering single crystal silicon, and is formed by changing the state from the single crystal silicon to amorphous silicon. The present inventors analyzed a state in the vicinity of the interface by an electron energy-loss spectroscopy (EELS), with respect to two measurement points of a measurement point 1 in the bonding interlayer 30 and a measurement point 2 in the insulating layer (SiO.sub.2). The electron energy-loss spectroscopy is a method of analyzing a constituent element or an electronic structure of a substance by measuring the energy lost by a mutual interaction with respect to an atom when electrons are transmitted through a thin sample.

(39) FIG. 7 is a graph illustrating an EELS spectrum of an Si-L absorption edge at the measurement point, and FIG. 8 is a graph illustrating an EELS spectrum of an OK absorption edge at the measurement point. For comparison, FIG. 7 illustrates spectrums in the same energy range of single crystal silicon (c-Si), amorphous silicon (a-Si), and a silicon oxide film (SiO.sub.2). As illustrated in FIG. 7, the EELS spectrum of the Si-L absorption edge at the measurement point 1 in the bonding interlayer 30 is close to the single crystal silicon or the amorphous silicon, and a characteristic peak of SiO.sub.2 was not observed. In addition, in the EELS spectrum of the OK absorption edge, the existence of an oxygen atom O was rarely confirmed in the bonding interlayer 30. For this reason, the bonding interlayer 30 does not contain an Si oxide, and the bonding interlayer 30 (the insulating junction portion 30a) formed between the first insulating layer 22 and the second insulating layer 25 is considered as amorphous silicon from a high-resolution image illustrated in FIG. 5.

(40) Subsequently, the electric properties of the bonding interlayer 30 (the insulating bonded portion 30a) formed in SiO.sub.2/SiO.sub.2 were measured. FIG. 9 is a graph illustrating a relationship between a current and a voltage in SiO.sub.2/SiO.sub.2. As illustrated in FIG. 9, the electric properties of amorphous silicon are greatly different from those of single crystal silicon, and thus, it is possible to confirm that the amorphous silicon exhibits non-conductivity in which electricity is blocked in the single body. Here, the non-conductivity indicates a state where resistivity is greater than or equal to 10.sup.5 .Math.cm.

(41) In addition, a bonding strength of SiO.sub.2/SiO.sub.2 bonded via the bonding interlayer 30 was measured. The bonding strength is measured by cutting a sample of the bonded SiO.sub.2/SiO.sub.2 to be a chip having a size of 12 mm12 mm, and by performing a tensile test with respect to the chip. In the test, the chip is fixed to a jig, and a load when the chip is broken was measured while changing a tensile load with respect to the jig. In the tensile test, a breakage occurred, but the breakage occurred due to the peeling-off of the chip from the jig on an adhesion interface, and the bonding of SiO.sub.2/SiO.sub.2 was retained. The tensile strength at the time of being broken was greater than or equal to 25 MPa, and thus, the strength of the bonding interface due to the bonding interlayer 30 is considered to be greater than or equal to 25 MPa.

(42) Thus, in a configuration using the amorphous silicon (the amorphous semiconductor material) as the junction interlayer 30, a result was obtained in which it is possible to rigidly join the first insulating layer 22 and the second insulating layer 25 together while retaining the non-conductivity (the insulating properties) between the first insulating layer 22 and the second insulating layer 25.

(43) Next, in the bonding interlayer 30 (the conductive bonded portion 30b) formed in Cu/Cu, a state in the vicinity of the interface was analyzed by an electron energy-loss spectroscopy. There are three measurement points of a measurement point A which is positioned in the vicinity of a boundary between the bonding interlayer 30 and Cu, a measurement point B which is positioned in the center of the bonding interlayer 30 in a thickness direction, and a measurement point C which is positioned between the measurement point A and the measurement point B in the thickness direction. FIG. 10 is a graph illustrating the EELS spectrum of the Si-L absorption edge at the measurement point, and FIG. 11 is a graph illustrating an EELS spectrum of a Cu-L absorption edge at the measurement point. For comparison, FIG. 11 illustrates spectrums in the same energy range of copper (Cu).

(44) As illustrated in FIG. 10, all of the EELS spectrums on the Si-L absorption edge at the measurement points A to C in the bonding interlayer 30 have the same shape, and illustrate that silicon independently exists. In addition, as illustrated in FIG. 11, in the EELS spectrums on the Cu-L absorption edge, the existence of copper is confirmed even at all of the measurement points A to C in the bonding interlayer 30.

(45) Further, the electric properties of the bonding interlayer 30 formed in Cu/Cu were measured. FIG. 12 is a graph illustrating a relationship between a current and a voltage in Cu/Cu. As illustrated in FIG. 12, even in a case where the bonding is performed via the bonding interlayer 30, a linear relationship is obtained between the voltage and the current, and thus, ohmic (according to Ohm's Law) connection is considered to be obtained in Cu/Cu. In addition, a resistance value at the time of performing direct bonding in Cu/Cu was less than or equal to 20 (m), and the resistance value at the time of performing the junction via the bonding interlayer 30 was less than or equal to 25 (m), and thus, approximately the same result was obtained. This point is greatly different from the fact that the non-conductivity is exhibited on the bonding interlayer in SiO.sub.2/SiO.sub.2. As described above, it is considered that this is because copper exists in the entire region of the bonding interlayer 30 (the conductive bonded portion 30b) even though the amount of copper is partially minute, and it is considered that this is because amorphous silicon of the bonding interlayer 30 and copper of each of the electrodes were bonded to each other at the time of performing pressure-welding between the first bonded electrode 23 and the second bonded electrode 26.

(46) Thus, in a configuration using the amorphous silicon (the amorphous semiconductor material) as the bonding interlayer 30, a result was obtained in which it is possible to ensure the conductivity between the first bonded electrode 23 and the second bonded electrode 26. Accordingly, the semiconductor device 20 of this embodiment includes the bonding interlayer 30 between the front surfaces 17A and 18A to which the bonded electrodes 23 and 26 and the insulating layers 22 and 25 are respectively exposed, and thus, it is possible to realize the hybrid bonding in which the bonded electrodes 23 and 26 and the insulating layers 22 and 25 are respectively and simultaneously bonded together. Further, the bonding interlayer 30 independently exhibits non-conductivity and exhibits conductivity by being bonded to the bonded electrodes 23 and 26, and thus, it is possible to ensure the non-conductivity between the first insulating layer 22 and the second insulating layer 25 while ensuring the conductivity between the first bonded electrode 23 and the second bonded electrode 26. For this reason, it is possible to prevent a current flowing between the first bonded electrode 23 and the second bonded electrode 26 from flowing between the first insulating layer 22 and the second insulating layer 25, and thus, it is possible to prevent a leak current from being generated, and to realize a stable operation of the semiconductor device 20.

(47) Next, a manufacturing procedure of the semiconductor device 20 will be described. FIG. 13A to FIG. 13F are step explanatory diagrams illustrating a step of bonding the first wafer and the second wafer together. As a premise, the first wafer 17 and the second wafer 18 are respectively manufactured in advance according to separate working steps in a state where the bonded electrodes 23 and 26 and the insulating layers 22 and 25 are respectively exposed to the front surfaces 17A and 18A.

(48) As illustrated in FIG. 13A, the first wafer 17 is transported into the vacuum chamber 11 of the bonding at room temperature device 10, and the first wafer 17 is supported on the electrostatic chuck 12A of the upper side stage 12 such that the front surface 17A is directed towards a vertically lower side. A vacuum atmosphere is maintained in the vacuum chamber 11. In this state, an argon beam 14a exits from the fast atom beam source 14 towards the front surface 17A of the first wafer 17. The front surface 17A of the first wafer 17 is irradiated with the argon beam 14a, and the front surface 17A is activated.

(49) Subsequently, as illustrated in FIG. 13B, a bare wafer 31 is transported into the vacuum chamber 11, and the bare wafer 31 is mounted on an upper surface of the lower side stage 13. The bare wafer 31 is formed of single crystal silicon, and is used as a sputtering source at the time of forming the junction interlayer 30. In this state, an argon beam 15a exits from the fast atom beam source 15 towards the bare wafer 31. Accordingly, the bare wafer 31 is sputtered, and a silicon atom flicked out from the bare wafer 31 increases, and thus, the junction interlayer 30 is formed on the front surface 17A of the first wafer 17. In this embodiment, the irradiation of the argon beam 15a is performed for a predetermined time (for example, 10 minutes), and the junction interlayer 30 having a thickness of approximately 1 nm to 50 nm is formed on the front surface 17A of the first wafer 17. As described above, the bonding interlayer 30 is amorphous silicon.

(50) Subsequently, as illustrated in FIG. 13C, the bare wafer 31 is discharged from the vacuum chamber 11, and instead, the second wafer 18 is transported into the vacuum chamber 11. The second wafer 18 is mounted on the upper surface of the lower side stage 13 such that the front surface 18A is directed towards a vertically upper side. Subsequently, as illustrated in FIG. 13D, the argon beam 15a exits from the fast atom beam source 15 towards the front surface 18A of the second wafer 18. The front surface 18A of the second wafer 18 is irradiated with the argon beam 15a, and the front surface 18A is activated.

(51) Subsequently, as illustrated in FIG. 13E, the argon beam 14a exits from the fast atom beam source 14 towards the bonding interlayer 30 formed on a front surface of the first wafer 17. In this case, a part of the amorphous silicon forming the bonding interlayer 30 functions as a sputtering source. According to the irradiation of the argon beam 14a, the bonding interlayer 30 is sputtered, a silicon atom flicked out from the bonding interlayer 30 increases, and thus, the bonding interlayer 30 is also formed on the front surface 18A of the second wafer 18. In this embodiment, the irradiation of the argon beam 14a is performed for a predetermined time (for example, 10 minutes), and the bonding interlayer 30 having a thickness of approximately 1 nm to 50 nm is formed on the front surface 18A of the second wafer 18. As described above, the bonding interlayer 30 is also amorphous silicon. In this embodiment, the bonding interlayer 30 formed on the front surface of the first wafer 17 is used as the sputtering source, and thus, a separate sputtering source is not required to be prepared for the front surface 18A of the second wafer 18, and the output and input of the sputtering source with respect to the vacuum chamber 11 is reduced, and thus, it is possible to simplify an operating procedure, and to simply form the bonding interlayer 30 on each of the front surfaces 17A and 18A of the first wafer 17 and the second wafer 18.

(52) Subsequently, the first wafer 17 and the second wafer 18 are aligned, and then, as illustrated in FIG. 13F, the pressure-welding mechanism 12B of the upper side stage 12 is operated, and thus, the electrostatic chuck 12A supporting the first wafer 17 is lowered to a vertically lower side, and the first wafer 17 and the second wafer 18 are subjected to the pressure-welding. Accordingly, the front surface 17A of the first wafer 17 and the front surface 18A of the second wafer 18 are joined together via the junction interlayer 30, and thus, the semiconductor device 20 is formed. Subsequently, the semiconductor device 20 (the first wafer 17 and the second wafer 18) is heated at a predetermined temperature (for example, approximately 50 C. to 400 C.) in the vacuum chamber 11. Accordingly, the alloying of copper (Cu) of the first bonded electrode 23 and the second bonded electrode 26 and amorphous silicon of the bonding interlayer 30 is accelerated, and the bonding between the first bonded electrode 23 and the second bonded electrode 26 becomes more rigid, and thus, the electric properties are improved.

(53) As described above, the manufacturing method of the semiconductor device 20 of this embodiment includes a step of respectively activating the front surface 17A of the first wafer 17 and the front surface 18A of the second wafer 18, a step of forming the bonding interlayer 30 on the activated front surfaces 17A and 18A, and a step of performing the pressure-welding with respect to the first wafer 17 and the second wafer 18 via the bonding interlayer 30, and thus, it is possible to easily realize the hybrid bonding in which the bonded electrodes 23 and 26 and the insulating layers 22 and 25 are respectively and simultaneously bonded together.

(54) Further, in this embodiment, the bare wafer 31 is irradiated with the argon beam 15a, and the bare wafer 31 is sputtered, and thus, the bonding interlayer 30 is formed on the front surface 17A of the first wafer 17, and then, the bonding interlayer 30 formed on the front surface 17A is irradiated with the argon beam 14a, a part of the amorphous silicon forming the bonding interlayer 30 is sputtered, and thus, the bonding interlayer 30 is formed on the front surface 18A of the second wafer 18, and therefore, it is possible to simplify the operating procedure, and to simply form the bonding interlayer 30 on each of the front surfaces 17A and 18A of the first wafer 17 and the second wafer 18.

(55) Next, another manufacturing procedure of the semiconductor device 20 will be described. FIG. 14A to FIG. 14D are step explanatory diagrams illustrating another step of bonding the first wafer and the second wafer together. Even in this case, as a premise, the first wafer 17 and the second wafer 18 are respectively manufactured in advance according to separate working steps in a state where the bonded electrodes 23 and 26 and the insulating layers 22 and 25 are respectively exposed to the front surfaces 17A and 18A.

(56) As illustrated in FIG. 14A, the first wafer 17 is transported into the vacuum chamber 11 of the bonding at room temperature device 10, and the first wafer 17 is supported on the electrostatic chuck 12A of the upper side stage 12 such that the front surface 17A is directed towards the vertically lower side. Similarly, the second wafer 18 is transported into the vacuum chamber 11, and the second wafer 18 is mounted on the upper surface of the lower side stage 13 such that the front surface 18A is directed towards the vertically upper side. A vacuum atmosphere is maintained in the vacuum chamber 11. In this state, the argon beams 14a and 15a respectively exit from the fast atom beam sources 14 and 15 towards the front surface 17A of the first wafer 17 and the front surface 18A of the second wafer 18. The front surface 17A of the first wafer 17 and the front surface 18A of the second wafer 18 are respectively irradiated with the argon beams 14a and 15a, and the front surfaces 17A and 18A are activated.

(57) Subsequently, as illustrated in FIG. 14B, the first wafer 17 and the second wafer 18 of which the front surfaces 17A and 18A are activated, are transported to a film formation chamber 40 from the vacuum chamber 11. In this case, it is preferable that the first wafer 17 and the second wafer 18 are transported according to a transport path of the vacuum not to be in contact with the outside air (oxygen). The film formation chamber 40 is a chamber for forming the junction interlayer 30 described above on the front surface 17A of the first wafer 17 and the front surface 18A of the second wafer 18, and a chemical vapor deposition device (not illustrated) is disposed in the film formation chamber 40. In a chemical vapor deposition method, raw material gas containing silicon is supplied onto the front surface 17A of the first wafer 17 and the front surface 18A of the second wafer 18 in a state where the first wafer 17 and the second wafer 18 are heated in predetermined conditions, and the bonding interlayer 30 is formed by a chemical reaction on the front surfaces 17A and 18A. Even in the chemical vapor deposition method, the bonding interlayer 30 is formed of amorphous silicon. In such a configuration, it is possible to separately form the bonding interlayer 30, and thus, it is possible to shorten a treatment time of a bonding step.

(58) Subsequently, as illustrated in FIG. 14C, the first wafer 17 and the second wafer 18 on which the bonding interlayer 30 is formed, are transported into the vacuum chamber 11. Then, the first wafer 17 is supported on the electrostatic chuck 12A of the upper side stage 12 such that the bonding interlayer 30 is directed towards the vertically lower side, and the second wafer 18 is mounted on the upper surface of the lower side stage 13 such that the bonding interlayer 30 is directed towards the vertically upper side. A vacuum atmosphere is maintained in the vacuum chamber 11. In this state, the argon beams 14a and 15a respectively exit from the fast atom beam sources 14 and 15 towards the bonding interlayers 30 and 30 formed on the first wafer 17 and the second wafer 18. Front surfaces of the junction interlayers 30 and 30 of the first wafer 17 and the second wafer 18 are irradiated with the argon beams 14a and 15a, and the front surfaces of the bonding interlayers 30 and 30 are activated.

(59) Subsequently, the first wafer 17 and the second wafer 18 are aligned, and then, as illustrated in FIG. 14D, pressure-welding mechanism 12B of the upper side stage 12 is operated, and thus, the electrostatic chuck 12A supporting the first wafer 17 is lowered to the vertically lower side, and the first wafer 17 and the second wafer 18 are subjected to the pressure-welding. Accordingly, the front surface 17A of the first wafer 17 and the front surface 18A of the second wafer 18 are bonded together via the bonding interlayer 30, and thus, the semiconductor device 20 is formed. Subsequently, the semiconductor device 20 (the first wafer 17 and the second wafer 18) is heated at a predetermined temperature (for example, 50 C. to 400 C.) in the vacuum chamber 11. Accordingly, the alloying of copper Cu of the first bonded electrode 23 and the second bonded electrode 26 and amorphous silicon of the bonding interlayer 30 is accelerated, and the bonding between the first bonded electrode 23 and the second bonded electrode 26 becomes more rigid, and thus, the electric properties are improved.

(60) Next, another embodiment will be described. FIG. 15A is a sectional view schematically illustrating a configuration before a first wafer and a second wafer according to another embodiment are bonded together, and FIG. 15B is a sectional view schematically illustrating a configuration of a state where the first wafer and the second wafer according to another embodiment are bonded together. In the configuration described above, the front surface 17A of the first wafer 17 and the front surface 18A of the second wafer 18 are respectively formed as a flat surface, and the front surfaces 17A and 18A are formed to be closely bonded together. In contrast, in another embodiment, as illustrated in FIG. 15A, a first insulating layer 122 and a first bonded electrode 123 laminated on a first semiconductor base material 121 are exposed to the front surface 17A, a height position of a front surface 122A of the first insulating layer 122 is lower than a height position of a front surface 123A of the first bonded electrode 123. A difference t between the height positions is set to be approximately 1 nm to 100 nm, which is approximately the same level as the bonding interlayer 30. Similarly, a second insulating layer 125 and a second bonded electrode 126 laminated on a second semiconductor base material 124 are exposed to the front surface 18A, and a height position of a front surface 125A of the second insulating layer 125 is lower than a height position of a front surface 126A of the second bonded electrode 126. A difference t between the height positions is set to be approximately 1 nm to 100 nm, which is approximately the same level as the bonding interlayer 30. The other configurations are identical to the configurations of the embodiment described above, and thus, the description thereof will be omitted.

(61) According to such a configuration, when the first wafer 17 and the second wafer 18 are subjected to the pressure-welding, a pressure-welding load is imparted to the first bonded electrode 123 and the second bonded electrode 126, and as illustrated in FIG. 15B, the bonding interlayer 30 is broken by the first bonded electrode 123 and the second bonded electrode 126, and the first bonded electrode 123 and the second bonded electrode 126 are directly bonded together. Accordingly, excellent electric properties and excellent junction strength can be obtained in the bonding between the first bonded electrode 123 and the second bonded electrode 126.

(62) As described above, the embodiments of the present invention have been described, but the present invention is not limited to the embodiments described above. For example, in the embodiments described above, although the bonding interlayer 30 is formed on both of the front surfaces 17A and 18A of the first wafer 17 and the second wafer 18, it may be formed on one of the front surfaces 17A and 18A. In addition, in the embodiments described above, although the first bonded electrode 123 and the second bonded electrode 126 are respectively formed to protrude from the first insulating layer 122 and the second insulating layer 125, one of the first bonded electrode 123 and the second bonded electrode 126 may be formed to protrude from the first insulating layer 122 and the second insulating layer 125. In addition, in the embodiments described above, a configuration has been described in which the bonding interlayer 30 is formed by the sputtering or the chemical vapor deposition method, and the bonding interlayer 30 may be formed by vapor deposition. In the vapor deposition, a vapor deposition material (for example, silicon) is heated in a vacuum container, is gasified or sublimated, and is attached onto a front surface of a substrate mounted in a separated position, and thus, a thin film is formed. According to such a method, the bonding interlayer 30 is formed of amorphous silicon. In such a configuration, it is possible to separately form the bonding interlayer 30, and thus, to shorten the treatment times of the bonding step.

REFERENCE SIGNS LIST

(63) 10 BONDING AT ROOM TEMPERATURE DEVICE 11 VACUUM CHAMBER 12 UPPER SIDE STAGE 12A ELECTROSTATIC CHUCK 12B PRESSURE-WELDING MECHANISM 13 LOWER SIDE STAGE 14, 15 FAST ATOM BEAM SOURCE 14a, 15a ARGON BEAM 17 FIRST WAFER (SUBSTRATE) 17A FRONT SURFACE (BONDED SURFACE) 18 SECOND WAFER (SUBSTRATE) 18A FRONT SURFACE (BONDED SURFACE) 20 SEMICONDUCTOR DEVICE 21, 121 FIRST SEMICONDUCTOR BASE MATERIAL 22, 122 FIRST INSULATING LAYER (INSULATING MATERIAL) 23, 123 FIRST BONDED ELECTRODE (CONDUCTIVE MATERIAL) 24, 124 SECOND SEMICONDUCTOR BASE MATERIAL 25, 125 SECOND INSULATING LAYER (INSULATING MATERIAL) 26, 126 SECOND BONDED ELECTRODE (CONDUCTIVE MATERIAL) 30 BONDING INTERLAYER 31 BARE WAFER 40 FILM FORMATION CHAMBER 122A FRONT SURFACE 123A FRONT SURFACE 125A FRONT SURFACE 126A FRONT SURFACE