Component carrier having an ESD protective function and method for producing same

Abstract

A green film composed of varistor material laminated on a ceramic main body, which is provided with metallizations on both sides, and is sintered to form a varistor layer. A terminating electrode pair completes the arrangement and allows the varistor layer to be operated as a varistor. The upper second electrode pair can serve directly as a terminal contact for mounting an electrical component.

Claims

1. A component carrier comprisinga ceramic main body having electrical terminal pads on a first surface and a first electrode pair on a second surface, wherein electrical terminal pads and first electrode pair are connected to one another via plated-through holes, comprisinga varistor layer laminated above the first electrode pair, and comprisinga second electrode pair, which is applied above the varistor layer and is electrically connected in parallel with the first electrode pair, wherein the varistor layer is laterally dimensioned such that it is circumferentially spaced apart from the edges of the component carrier, wherein a passivation layer is arranged above the varistor layer and the second electrode pair such that the varistor layer is enclosed on all sides and completely between the ceramic main body, the second electrode pair and the passivation layer and only terminal contacts remain free of and not covered by the second electrode pair, and wherein the passivation layer includes glass or a polymer.

2. The component carrier according to claim 1, wherein the second electrode pair comprises a solderable material or is provided with a solderable surface layer.

3. The component carrier according to claim 1, wherein the main body comprises aluminum nitride.

4. The component carrier according to claim 1, wherein at least the second electrode pair comprises a copper-containing material.

5. The component carrier according to claim 1, wherein at least one internal electrode is arranged between first and second electrode pairs, said at least one internal electrode being embedded into the varistor layer and being electrically floating or electrically connected to a respective electrode of the first electrode pair.

6. A method for producing a component carrier comprising the following steps: providing a monolithic ceramic main body, providing plated-through holes through the main body, printing electrical terminal pads on a first surface of the main body, printing a first electrode pair on the second surface, laminating a green film or a preformed stack of green films over the whole area above the first electrode pair on the ceramic main body, said green film being able to be converted into a varistor layer by sintering, structuring the green film such that a circumferential marginal region of the second surface of the main body is also exposed besides an access to the first electrode pair, sintering the green film and converting into the varistor layer, printing a second electrode pair onto the varistor layer and the exposed region of the first electrode pair such that first and second electrode pairs are electrically interconnected and an overlap of an electrode of the first electrode pair with the opposite electrode of the second electrode pair jointly defines an active varistor region situated therebetween.

7. The method according to claim 6, wherein one or a plurality of metallizations, selected from terminal pads, first electrode pair and second electrode pair, is produced by printing a paste containing Cu and glass portions, which has a solderable surface after firing.

8. The method according to claim 6, wherein the laminated green film is structured with the aid of a laser.

9. The method according to claim 6, wherein laminating the green film comprises laminating a prelaminated stack of a plurality of green films, wherein at least one internal electrode printed onto a green film is integrated in the stack.

10. The method according to claim 6, wherein the internal electrode is printed in a structured fashion and does not extend over the entire varistor layer, wherein the green film, after laminating, is structured by material removal such that at least one internal electrode intersects one of the exposed edges of the green film, wherein, after printing the second electrode pair, one of the electrodes thereof electrically contacts the internal electrode.

11. The method according to claim 6, wherein, after laminating the green film, before or after printing the second electrode pair, a passivation layer is applied and structured such that in the first case only the surface region provided for the second electrode pair remains free of the passivation layer, or wherein in the second case the printed second electrode pair remains free only in a region in which solderable terminal contacts are subsequently produced by reinforcement of the second electrode pair.

12. The method according to claim 6, wherein after laminating the green film, after printing the second electrode pair, a passivation layer is applied and structured, wherein the printed second electrode pair remains free only in a region in which solderable terminal contacts are subsequently produced by reinforcement of the second electrode pair, wherein the reinforcement is effected by electrodeposition of a solderable metal layer onto the exposed region of the second electrode pair.

13. The method according to claim 6, wherein a large-area main body is provided which is able to be singulated into a multiplicity of component carriers, wherein the large-area main body, after the completion of the second electrode pair or the solderable terminal contacts, is singulated into the multiplicity of component carriers by separation of the main body, wherein the separation of the main body is effected exclusively in the marginal region and at a distance from the respective edge of the varistor layer.

14. A method for producing a component carrier comprising the following steps: providing a monolithic ceramic main body, providing plated-through holes through the main body, printing electrical terminal pads on a first surface of the main body, printing a first electrode pair on the second surface, laminating a green film or a preformed stack of green films over the whole area above the first electrode pair on the ceramic main body, said green film being able to be converted into a varistor layer by sintering, structuring the green film such that a circumferential marginal region of the second surface of the main body is also exposed besides an access to the first electrode pair, sintering the green film and converting into the varistor layer, printing a second electrode pair onto the varistor layer and the exposed region of the first electrode pair such that first and second electrode pairs are electrically interconnected and an overlap of an electrode of the first electrode pair with the opposite electrode of the second electrode pair jointly defines an active varistor region situated therebetween, wherein a passivation layer is applied such that the varistor layer is enclosed on all sides and completely between the ceramic main body, the second electrode pair and the passivation layer.

Description

(1) The component carrier according to the invention and various method variants for producing it are explained in greater detail below on the basis of exemplary embodiments and with reference to the associated figures. The figures show schematic cross sections and are not drawn as true to scale. Individual parts may be illustrated in an enlarged manner in order to afford better understanding.

(2) FIG. 1 shows one simple embodiment of a component carrier.

(3) FIGS. 2A to 2H show one simple method for producing a component carrier on the basis of various method stages.

(4) FIGS. 3A to 3F show a second production method for a flat variant on the basis of schematic cross sections during various method stages.

(5) FIGS. 4A to 4G show various method stages on the basis of schematic cross sections during the production of a component carrier comprising a multilayered varistor.

(6) FIGS. 5A and 5B show the production of a film stack such as can be used during the production of a multilayered varistor.

(7) FIGS. 6A to 6E show various embodiments of a component carrier according to the invention after being equipped with a component.

(8) FIG. 1 shows, in schematic cross section, one simple embodiment of a component carrier BT according to the invention. A ceramic main body GK is provided with terminal pads AF on a first surface O1. A first electrode pair EP1 is applied on the second surface O2 situated opposite. Each terminal pad AF is assigned to an electrode of the first electrode pair EP1 and is connected to said electrode via a plated-through hole DK through the main body GK.

(9) A varistor layer VS bears above both electrodes of the first electrode pair EP1. A second electrode pair EP2 is fitted above the varistor layer VS and structured such that a first electrode of the second electrode pair is in contact with a first electrode of the first electrode pair. Correspondingly, the second electrode of the second electrode pair EP2 is in contact with the second electrode of the first electrode pair EP1.

(10) In this case, an electrode of the first electrode pair overlaps an electrode of the second electrode pair EP2 such that with the intervening varistor layer VS in the overlap region a varistor arises.

(11) A part of the active varistor is illustrated as an excerpt in an enlarged view above the component carrier BT. Close-packed zinc oxide grains ZK are arranged in the varistor layer VS. As soon as the voltage present at first and second electrode pairs EP1, EP2 exceeds the breakdown voltage, a conductive path forms between individual zinc oxide grains ZK, with the result that the varistor layer VS becomes conducting and the current is dissipated harmlessly by way of a short circuit through the varistor layer via both electrodes.

(12) The term varistor voltage denotes the voltage drop across the varistor given an impressed current of 1 mA. It does not have special electro-physical importance, but is used as a practical, standardized reference point for specifying varistors.

(13) The main body GK is preferably formed from aluminum oxide or, for better heat conduction, from aluminum nitride. Other ceramic materials, too, are theoretically suitable, but costly. Terminal pads and first electrode pair comprise a fired conductive paste, for example based on silver. The same correspondingly applies to the plated-through hole DK. The second electrode pair EP2, too, is preferably formed from a conductive fired paste and either is already solderable per se or is provided with a solderable surface. A copper-containing paste which either already has a solderable surface per se by virtue of additives or has a solderable surface finish can be used in a cost-effective manner.

(14) FIGS. 2A to 2H show one simple production method for a component carrier according to FIG. 1. FIG. 2A shows in the first stage a main body GK having, for the purpose of producing plated-through holes DK, at least two holes filled with a conductive compound, in particular a paste that can be fired.

(15) FIG. 2B shows the main body after the production of terminal pads AF on the first surface and a first electrode pair EP1 on the second surface. The metallizations on the two surfaces can be present in the form of a conductive paste, but can also already be fired.

(16) In the next step, a green film of a varistor layer VS is laminated onto the second surface above the first electrode pair EP1. This is carried out over the whole area over the entire surface of the main body GK.

(17) In the next step, the whole-area varistor layer VS is structured with the aid of a structuring tool ST. In this case, the varistor layer VS is removed in a circumferential marginal region along the edges of the main body and the surface of the main body is exposed there. Moreover, the varistor film VS is removed in the marginal region of the first electrode pair EP1 in order to contact the electrode pair there later. Preferably, the electrodes of the first electrode pair are embodied in each case in a strip-shaped fashion, as is the exposed region.

(18) FIG. 2E shows the arrangement after the structuring of the varistor layer VS.

(19) A second electrode pair EP2 is then applied to the laminated green film of the varistor layer VS such that a respective electrode thereof contacts an electrode of the first electrode pair EP1 in the exposed region. The second electrode pair EP2 is preferably printed, wherein a conductive paste based on silver or copper can be used. After printing, the second electrode pair EP2 can be fired, wherein at the same time the first electrode pair, provided that it is not sintered beforehand, and likewise the terminal pads AF are also concomitantly fired. FIG. 2F shows the arrangement after the completion of the second electrode pair.

(20) In order to produce solderable terminal contacts AK, a passivation layer PS is then applied over the entire surface and structured such that it forms a mask for the production of the terminal contacts AK. A glass-containing layer or some other resist mask, for example a polymer, can be used as passivation layer PS. A glass-containing passivation layer can be printed, for example. A polymer layer, like a photoresist, can be laminated as a film or applied by spin-coating in liquid form and patterned photolitho-graphically. FIG. 2G shows the arrangement at this method stage.

(21) The external contacts AK can then be applied in an galvanic method. To that end, the second electrode pair EP2, where it is freed of and not covered by the passivation layer PS, is reinforced with a metal of good conductivity, for example with copper. In order to produce a solderable surface, a finishing layer composed of gold, palladium or nickel and/or NiPdAu, NiAu or else CuNiSn can subsequently be applied. Together with this finishing step, if appropriate, the terminal pads AF on the first surface O1 can also be provided with a solderable coating. FIG. 2H shows the arrangement at this method stage.

(22) FIGS. 3A to 3F show, on the basis of schematic cross sections during various method stages, the production of a component carrier according to the invention in which an internal electrode IE is provided in the varistor layer VS. The method starts with a main body GK provided with electrodes, for example as illustrated in FIG. 2B. A green film for the varistor layer VS is then laminated onto said main body. In this case, two variants are possible, in principle. In the case of the first variant, a first partial layer of the varistor layer can be laminated and the internal electrode IE can then be printed. Afterward, a second green film of the varistor layer VS is laminated thereabove over the whole area such that the internal electrode is completely embedded between the two varistor layers.

(23) In accordance with a second variant, the internal electrode IE is printed onto a first partial film of the varistor layer VS and then a second partial film of the varistor layer is laminated thereabove. This takes place wholly separately from the main body GK, thus giving rise to a prelaminate, which only then is laminated onto the ceramic main body GK.

(24) FIG. 3A shows the arrangement with the varistor layer, in which the internal electrode IE is embedded in a manner both overlapping the electrodes of first and second electrode pairs.

(25) With the aid of a structuring tool ST, as illustrated in FIG. 3B, said varistor layer VS is also structured and in this case the marginal region and likewise the regions of the first electrode pair that are provided for terminals are freed of the varistor layer VS. The internal electrode remains floating and is not exposed or cut during the structuring. By way of example, a laser can be used for the structuring.

(26) The varistor layer VS is subsequently sintered, wherein a volume shrinkage commences such as occurs when any ceramic is fired. Since the varistor layer is clamped by the main body, however, this leads at most to little lateral shrinkage, usually none at all, but in return to a reduction of the layer thickness of the varistor layer. FIG. 3C shows the arrangement after the sintering of the varistor layer VS, wherein the reduced layer thickness in comparison with FIG. 3B is clearly discernible.

(27) Over the whole area a passivation layer PS is then applied and structured, or is applied in a manner having already been structured or prestructured, for example by printing. The passivation layer PS does not cover the terminal regions provided for connecting the first electrode pair and also parts of the varistor layer VS on which the second electrode pair is produced in a structured fashion later. FIG. 3D shows the arrangement with the structured passivation layer PS.

(28) In the regions free of the passivation layer PS, the second electrode pair EP2 is then applied, for example by printing. The second electrode pair is subsequently fired. FIG. 3E shows the arrangement at this method stage.

(29) In order to produce a solderable surface, a finishing layer can be applied to the second electrode pair EP2, for example by electrodeposition of a surface layer OS, for example of a gold, palladium or platinum layer, or of one of the further coatings mentioned above. FIG. 3F shows the arrangement at this method stage.

(30) The finished component carrier BT can then be equipped with an electrical component, which can be soldered onto the first electrode pair or onto the surface layer OS thereof. Alternatively, the component can also be mounted onto the terminal pads AF on the opposite first top side O1.

(31) FIGS. 4A to 4G show the production of a component carrier having a multilayered varistor construction on the basis of schematic cross sections during various method stages. To that end, FIG. 4A shows a main body GK coated with electrodes on both sides, namely with terminal pads AF on the underside or first surface and a first electrode pair EP1 on the second surface O2.

(32) A film stack FS is then laminated onto the second surface above the first electrode pair EP1. The method for that can be carried out as already described in the previous exemplary embodiment in accordance with FIG. 3.

(33) The film stack FS can be produced remotely from the main body by a procedure in which green films printed with electrode material are laminated one above another such that the internal electrodes IE mutually overlap and electrodes of different polarities can be contacted at marginal regions situated opposite one another. There the individual layers of the internal electrodes also do not overlap another internal electrode of opposite polarity. The laminated film stack FS is subsequently laminated as a whole onto the surface of the main body above the first electrode pair EP1. FIG. 4B shows the arrangement at this method stage.

(34) FIG. 2D shows how the film stack FS is structured with the aid of a structuring tool ST such that a circumferential marginal region of the green body and also the terminal regions of the first electrode pair that are provided for connecting the second electrode pair are exposed. At the same time, here in the two opposite marginal regions in each case a corresponding side edge of an internal electrode is exposed in order thus to contact it with an electrode to be applied later of the second electrode pair.

(35) FIG. 4D shows the arrangement after the structuring and firing of the film stack, a varistor layer VS with here two internal electrodes IE being obtained. In the figure, the left edge of the lower internal electrode IE1 is exposed for connection to the left electrode of the first electrode pair. At the right edge of the varistor layer VS, the upper internal electrode 1E2 is exposed for connection to the right electrode of the first electrode pair.

(36) In the next step, the second electrode pair EP2 is printed, wherein each of the two electrodes contacts the corresponding underlying electrode of the first electrode pair 1 and also one or more assigned internal electrodes IE. Besides printing, which is preferred, other metallization methods are also conceivable, in principle, e.g. ink jet methods, vapor deposition, sputtering. In the active varistor region, electrodes of different polarities overlap, selected from electrode layers from the second electrode pair EP2, internal electrodes IE and the first electrode pair EP1. FIG. 4E shows the arrangement at this method stage.

(37) FIG. 4F shows the arrangement after the application of a passivation layer PS, which serves for masking the varistor layer before the production of the terminal contacts. The passivation layer can be printed or else applied by spray coating. As mentioned with reference to the previous exemplary embodiments, the passivation layer can comprise an arbitrary dielectric material, in particular a glass-containing layer or a polymer. The regions of the second electrode pair that are provided for producing the external contacts are left uncovered.

(38) Into these exposed regions, by means of electrodeposition, the second electrode pair EP can then be reinforced or provided with a solderable surface layer OS.

(39) FIGS. 5A and 5B show the production of a film stack FS such as can be used as a prelaminate for a later varistor layer. For this purpose, a corresponding number of green films are printed with an internal electrode and stacked one above another such that internal electrodes IE of different polarities are offset relative to one another, but overlap in the center. An unprinted green film is also arranged above the topmost internal electrode and laminated with the other printed green films to form a film stack FS, as is illustrated in FIG. 5B. The film stack FS, too, can still be handled like a green film and can be laminated in this form onto a green body.

(40) FIGS. 6A to 6E show various embodiments of component carriers according to the invention after the mounting of a component onto the terminal contacts AK of the second electrode pair EP2 or, in the variant in accordance with FIG. 6E, onto the terminal pads AF. FIG. 6A shows the simplest embodiment of the component carrier with monolayer varistor layer and non-passivated second electrode pair.

(41) In the embodiment according to FIG. 6B, a monolayer varistor layer VS is likewise used, but exposed regions of the varistor layer and large parts of the second electrode pair EP2 are covered with a passivation layer PS. The only locations that remain free are those in which the terminal contacts are produced, onto which the component BE is subsequently mounted with the aid of connection means VM. A bump or a conventional solder joint can be used as connection means VM.

(42) In the embodiment according to FIG. 6C, the varistor layer VS has a floating internal electrode, which is not in electrical contact with first or second electrode pair. Here, too, a passivation layer PS is again provided, which leaves free only the terminal contacts. In contrast to FIG. 6B, a surface layer OS is additionally also applied above the terminal contacts or the second electrode pair EP in the region of the terminal contacts.

(43) FIG. 6D shows a multilayered varistor layer, in which at least two internal electrodes are provided, which are electrically conductively connected alternately to a respective electrode of the second electrode pair EP. A passivation layer PS above the second electrode pair and the exposed region of the varistor layer leaves free only the region for the terminal contacts AK, which can be produced electrolytically. A component BE is applied to the terminal contacts and electrically conductively connected with the aid of connection means VM.

(44) FIG. 6E shows the already explained embodiment of a component carrier in which the component is applied to the terminal pads on the opposite surface of the main body GK by means of connection means VM. In this method variant, the varistor layer is preferably covered with a passivation layer apart from the external contacts AK in order to facilitate the handling of the component carrier with the component BE mounted thereon, or in order to protect the varistor layer VS during the handling of the arrangement.

(45) The component BE can be an arbitrary electrical component which is sensitive to overvoltages such as can be triggered e.g. by an ESD pulse, and which is protected against these current or voltage surges with the aid of the varistor function within the varistor layer. One exemplary application is an LED that can be applied as component BE to the component carrier.

(46) The invention has been able to be explained only on the basis of a few exemplary embodiments and is therefore not restricted to the embodiments illustrated. The production methods, in particular, have been illustrated only for an isolated main body intended to be equipped with a component. It is also possible, however, to use a large-area main body GK or a corresponding wafer which can be singulated into a multiplicity of individual component carriers in the latter method step.

(47) Although the electrodes have been illustrated only in pairs, a component carrier is not restricted to those having two electrodes or having two terminal contacts per electrode. For each electrode it is possible to provide a plurality of terminal pads or electrode pairs, which, however, can again be interconnected in parallel among one another.

(48) The varistor layer can be without an internal electrode or be provided with a floating internal electrode or with electrically connected overlapping internal electrodes. The number of internal electrodes enlarges the overlap area of electrodes of opposite polarities and thus determines the capacitance of the varistor.

(49) More overlap area of the electrodes leads to more current-carrying capacity. Doubled ceramic height with internal electrode situated therebetween yields doubled protection level since double the number of microvaristors are then in series. Doubled area yields doubled dissipation capability since double the number of current paths are then in parallel.

(50) Doubled volume of the varistor yields approximately doubled energy absorption capability since double the number of energy absorbers in the form of zinc oxide grains are then available.

(51) The embodiment according to FIG. 6E has the further advantage that the first surface that can be equipped with the component BE largely consists of the main body GK, which has a good reflectivity. If an LED is applied as component BE, then the light emission thereof is improved by virtue of the higher reflection of the main body, which is largely exposed at the top side. A planar installation location for the component BE, e.g. for an LED, is also obtained as a result. Moreover, a good thermal contact between component and main body is thus ensured.

LIST OF REFERENCE SIGNS

(52) BT Component carrier GK Ceramic main body O1,O2 First and second surfaces AF Electrical terminal pads EP1 First electrode pair EP2 Second electrode pair VS Varistor layer DK Plated-through hole OS Solderable surface layer (solderable metal layer) IE Internal electrode PS Passivation layer GF Green film AK Terminal contacts FS Prelaminated stack of a plurality of green films VM Connection means ZK Zinc oxide grains ST Structuring tool